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[87.3.249.180]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-47f85bd850asm25701300f8f.15.2026.07.24.11.43.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 11:43:15 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Christian Marangi , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: clock: airoha: Add PHY binding for Serdes port Date: Fri, 24 Jul 2026 20:43:01 +0200 Message-ID: <20260724184304.192962-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260724184304.192962-1-ansuelsmth@gmail.com> References: <20260724184304.192962-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add PHY cell property for Serdes port selection. Currently supported only for Airoha AN7581 SoC, that support up to 4 Serdes port. The Serdes port can support both PCIe, USB3 or Ethernet mode. - PCIe1 Serdes can support PCIe or Ethernet mode. - PCIe2 Serdes can support PCIe or Ethernet mode. - USB1 Serdes can support USB3 or HSGMII mode. - USB2 Serdes can support USB3 or PCIe mode. Add bindings to permit correct reference of the Serdes ports in DT. Values are just symbolic and enumerates the Serdes port with a specific number for precise reference. The available Serdes port can be selected following the dt-binding header in [2]. [2] Signed-off-by: Christian Marangi --- .../bindings/clock/airoha,en7523-scu.yaml | 24 ++++++++++++++++--- include/dt-bindings/soc/airoha,scu-ssr.h | 11 +++++++++ 2 files changed, 32 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/soc/airoha,scu-ssr.h diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml= b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index eb24a5687639..fc37786ac7ed 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -23,6 +23,7 @@ description: | =20 All these identifiers can be found in: [1]: . + [2]: . =20 The clocks are provided inside a system controller node. =20 @@ -50,6 +51,12 @@ properties: description: ID of the controller reset line const: 1 =20 + '#phy-cells': + description: + The first cell indicates the serdes phy number, see [2] for the + available serdes port. + const: 1 + required: - compatible - reg @@ -65,12 +72,23 @@ allOf: reg: minItems: 2 =20 + '#phy-cells': false + + - if: + properties: + compatible: + const: econet,en751221-scu + then: + properties: + reg: + maxItems: 1 + + '#phy-cells': false + - if: properties: compatible: - enum: - - airoha,en7581-scu - - econet,en751221-scu + const: airoha,en7581-scu then: properties: reg: diff --git a/include/dt-bindings/soc/airoha,scu-ssr.h b/include/dt-bindings= /soc/airoha,scu-ssr.h new file mode 100644 index 000000000000..33c64844ada3 --- /dev/null +++ b/include/dt-bindings/soc/airoha,scu-ssr.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_AIROHA_SCU_SSR_H +#define __DT_BINDINGS_AIROHA_SCU_SSR_H + +#define AIROHA_SCU_SERDES_PCIE1 0 +#define AIROHA_SCU_SERDES_PCIE2 1 +#define AIROHA_SCU_SERDES_USB1 2 +#define AIROHA_SCU_SERDES_USB2 3 + +#endif /* __DT_BINDINGS_AIROHA_SCU_SSR_H */ --=20 2.53.0 From nobody Fri Jul 24 20:51:08 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15EF444E67F for ; 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[87.3.249.180]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-47f85bd850asm25701300f8f.15.2026.07.24.11.43.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 11:43:16 -0700 (PDT) From: Christian Marangi To: Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Christian Marangi , Felix Fietkau , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] clk: en7523: Add support for selecting the Serdes port in SCU Date: Fri, 24 Jul 2026 20:43:02 +0200 Message-ID: <20260724184304.192962-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260724184304.192962-1-ansuelsmth@gmail.com> References: <20260724184304.192962-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the SCU register for clock and reset, there are also some register to select the Serdes port mode. The Airoha AN7581 SoC have 4 different Serdes that can switch between PCIe, USB or Ethernet mode. Add a simple PHY provider that expose the .set_mode OP to toggle the requested mode for the Serdes port. Reviewed-by: Brian Masney Signed-off-by: Christian Marangi --- drivers/clk/Kconfig | 1 + drivers/clk/clk-en7523.c | 218 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 216 insertions(+), 3 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 1717ce75a907..4d58c35d88bc 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -221,6 +221,7 @@ config COMMON_CLK_EN7523 bool "Clock driver for Airoha/EcoNet SoC system clocks" depends on OF depends on ARCH_AIROHA || ECONET || COMPILE_TEST + select GENERIC_PHY default ARCH_AIROHA help This driver provides the fixed clocks and gates present on Airoha diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 1ab0e2eca5d3..183cf7fe4bda 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -6,14 +6,18 @@ #include #include #include +#include +#include #include #include #include +#include #include #include #include #include #include +#include =20 #define RST_NR_PER_BANK 32 =20 @@ -40,9 +44,22 @@ #define REG_HIR_MASK GENMASK(31, 16) /* EN7581 */ #define REG_NP_SCU_PCIC 0x88 +#define REG_NP_SCU_SSR3 0x94 +#define REG_SSUSB_HSGMII_SEL_MASK BIT(29) +#define REG_SSUSB_HSGMII_SEL_HSGMII FIELD_PREP_CONST(REG_SSUSB_HSGMII_SEL_= MASK, 0x0) +#define REG_SSUSB_HSGMII_SEL_USB FIELD_PREP_CONST(REG_SSUSB_HSGMII_SEL_MAS= K, 0x1) #define REG_NP_SCU_SSTR 0x9c #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) +#define REG_PCIE_XSI0_SEL_PCIE FIELD_PREP_CONST(REG_PCIE_XSI0_SEL_MASK, 0= x0) +#define REG_PCIE_XSI0_SEL_XFI FIELD_PREP_CONST(REG_PCIE_XSI0_SEL_MASK, 0x= 1) +#define REG_PCIE_XSI0_SEL_HSGMII FIELD_PREP_CONST(REG_PCIE_XSI0_SEL_MASK, = 0x2) #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) +#define REG_PCIE_XSI1_SEL_PCIE FIELD_PREP_CONST(REG_PCIE_XSI1_SEL_MASK, 0= x0) +#define REG_PCIE_XSI1_SEL_XFI FIELD_PREP_CONST(REG_PCIE_XSI1_SEL_MASK, 0x= 1) +#define REG_PCIE_XSI1_SEL_HSGMII FIELD_PREP_CONST(REG_PCIE_XSI1_SEL_MASK, = 0x2) +#define REG_USB_PCIE_SEL_MASK BIT(3) +#define REG_USB_PCIE_SEL_PCIE FIELD_PREP_CONST(REG_USB_PCIE_SEL_MASK, 0x0) +#define REG_USB_PCIE_SEL_USB FIELD_PREP_CONST(REG_USB_PCIE_SEL_MASK, 0x1) #define REG_CRYPTO_CLKSRC2 0x20c /* EN751221 */ #define EN751221_REG_SPI_DIV 0x0cc @@ -81,6 +98,8 @@ enum en_hir { HIR_MAX =3D 14, }; =20 +#define EN_SERDES_PHY_NUM 4 + struct en_clk_desc { int id; const char *name; @@ -113,6 +132,18 @@ struct en_rst_data { struct reset_controller_dev rcdev; }; =20 +struct en_serdes_phy_instance { + struct phy *phy; + unsigned int serdes_port; +}; + +struct en_clk_priv { + void __iomem *base; + /* protect SCU register */ + spinlock_t lock; + struct en_serdes_phy_instance *serdes_phys[EN_SERDES_PHY_NUM]; +}; + struct en_clk_soc_data { u32 num_clocks; const struct clk_ops pcie_ops; @@ -830,12 +861,179 @@ static int en7581_reset_register(struct device *dev,= void __iomem *base, return devm_reset_controller_register(dev, &rst_data->rcdev); } =20 +static int en7581_serdes_phy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct en_serdes_phy_instance *instance =3D phy_get_drvdata(phy); + struct en_clk_priv *priv =3D dev_get_drvdata(phy->dev.parent); + u32 reg, mask, sel, val; + unsigned long flags; + + switch (instance->serdes_port) { + case AIROHA_SCU_SERDES_PCIE1: + reg =3D REG_NP_SCU_SSTR; + mask =3D REG_PCIE_XSI0_SEL_MASK; + + if (mode !=3D PHY_MODE_ETHERNET && mode !=3D PHY_MODE_PCIE) + return -EINVAL; + + if (mode =3D=3D PHY_MODE_ETHERNET) { + switch (submode) { + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + sel =3D REG_PCIE_XSI0_SEL_XFI; + break; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + sel =3D REG_PCIE_XSI0_SEL_HSGMII; + break; + default: + return -EINVAL; + } + } else { + sel =3D REG_PCIE_XSI0_SEL_PCIE; + } + + break; + case AIROHA_SCU_SERDES_PCIE2: + reg =3D REG_NP_SCU_SSTR; + mask =3D REG_PCIE_XSI1_SEL_MASK; + + if (mode !=3D PHY_MODE_ETHERNET && mode !=3D PHY_MODE_PCIE) + return -EINVAL; + + if (mode =3D=3D PHY_MODE_ETHERNET) { + switch (submode) { + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + sel =3D REG_PCIE_XSI1_SEL_XFI; + break; + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + sel =3D REG_PCIE_XSI1_SEL_HSGMII; + break; + default: + return -EINVAL; + } + } else { + sel =3D REG_PCIE_XSI1_SEL_PCIE; + } + + break; + case AIROHA_SCU_SERDES_USB1: + reg =3D REG_NP_SCU_SSR3; + mask =3D REG_SSUSB_HSGMII_SEL_MASK; + + if (mode !=3D PHY_MODE_ETHERNET && mode !=3D PHY_MODE_USB_DEVICE && + mode !=3D PHY_MODE_USB_DEVICE_SS) + return -EINVAL; + + if (mode =3D=3D PHY_MODE_ETHERNET) + sel =3D REG_SSUSB_HSGMII_SEL_HSGMII; + else + sel =3D REG_SSUSB_HSGMII_SEL_USB; + + break; + case AIROHA_SCU_SERDES_USB2: + reg =3D REG_NP_SCU_SSTR; + mask =3D REG_USB_PCIE_SEL_MASK; + + if (mode !=3D PHY_MODE_PCIE && mode !=3D PHY_MODE_USB_DEVICE && + mode !=3D PHY_MODE_USB_DEVICE_SS) + return -EINVAL; + + if (mode =3D=3D PHY_MODE_PCIE) + sel =3D REG_USB_PCIE_SEL_PCIE; + else + sel =3D REG_USB_PCIE_SEL_USB; + + break; + default: + return -EINVAL; + } + + spin_lock_irqsave(&priv->lock, flags); + val =3D readl(priv->base + reg); + val &=3D ~mask; + val |=3D sel; + writel(val, priv->base + reg); + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static const struct phy_ops en7581_serdes_phy_ops =3D { + .set_mode =3D en7581_serdes_phy_set_mode, + .owner =3D THIS_MODULE, +}; + +static struct phy *en7581_serdes_phy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct en_clk_priv *priv =3D dev_get_drvdata(dev); + struct en_serdes_phy_instance *instance; + unsigned int serdes_port; + + if (args->args_count !=3D 1) { + dev_err(dev, "invalid number of cells in 'phy' property\n"); + return ERR_PTR(-EINVAL); + } + + serdes_port =3D args->args[0]; + if (serdes_port >=3D EN_SERDES_PHY_NUM) { + dev_err(dev, "invalid serdes port: %d\n", serdes_port); + return ERR_PTR(-EINVAL); + } + + instance =3D priv->serdes_phys[serdes_port]; + if (!instance) { + dev_err(dev, "failed to find appropriate serdes phy\n"); + return ERR_PTR(-EINVAL); + } + + return instance->phy; +} + +static int en7581_serdes_phy_register(struct device *dev) +{ + struct en_clk_priv *priv =3D dev_get_drvdata(dev); + struct phy_provider *phy_provider; + int i; + + for (i =3D 0; i < EN_SERDES_PHY_NUM; i++) { + struct en_serdes_phy_instance *instance; + + instance =3D devm_kzalloc(dev, sizeof(*instance), + GFP_KERNEL); + if (!instance) + return -ENOMEM; + + instance->phy =3D devm_phy_create(dev, NULL, + &en7581_serdes_phy_ops); + if (IS_ERR(instance->phy)) + return dev_err_probe(dev, PTR_ERR(instance->phy), "failed to create phy= \n"); + + instance->serdes_port =3D i; + priv->serdes_phys[i] =3D instance; + + phy_set_drvdata(instance->phy, instance); + } + + phy_provider =3D devm_of_phy_provider_register(dev, en7581_serdes_phy_xla= te); + + return PTR_ERR_OR_ZERO(phy_provider); +} + static int en7581_clk_hw_init(struct platform_device *pdev, struct clk_hw_onecell_data *clk_data) { + struct en_clk_priv *priv =3D platform_get_drvdata(pdev); struct regmap *map; void __iomem *base; u32 val; + int ret; =20 map =3D syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); if (IS_ERR(map)) @@ -845,6 +1043,8 @@ static int en7581_clk_hw_init(struct platform_device *= pdev, if (IS_ERR(base)) return PTR_ERR(base); =20 + priv->base =3D base; + en7581_register_clocks(&pdev->dev, clk_data, map, base); =20 val =3D readl(base + REG_NP_SCU_SSTR); @@ -853,9 +1053,12 @@ static int en7581_clk_hw_init(struct platform_device = *pdev, val =3D readl(base + REG_NP_SCU_PCIC); writel(val | 3, base + REG_NP_SCU_PCIC); =20 - return en7581_reset_register(&pdev->dev, base, en7581_rst_map, - ARRAY_SIZE(en7581_rst_map), - en7581_rst_ofs); + ret =3D en7581_reset_register(&pdev->dev, base, en7581_rst_map, + ARRAY_SIZE(en7581_rst_map), en7581_rst_ofs); + if (ret) + return ret; + + return en7581_serdes_phy_register(&pdev->dev); } =20 static enum en_hir get_hw_id(void __iomem *np_base) @@ -962,16 +1165,25 @@ static int en7523_clk_probe(struct platform_device *= pdev) struct device_node *node =3D pdev->dev.of_node; const struct en_clk_soc_data *soc_data; struct clk_hw_onecell_data *clk_data; + struct en_clk_priv *priv; int r; =20 soc_data =3D device_get_match_data(&pdev->dev); =20 + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->lock); + clk_data =3D devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, soc_data->num_clocks), GFP_KERNEL); if (!clk_data) return -ENOMEM; =20 + platform_set_drvdata(pdev, priv); + clk_data->num =3D soc_data->num_clocks; r =3D soc_data->hw_init(pdev, clk_data); if (r) --=20 2.53.0