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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1d0a73520csm74444366b.1.2026.07.24.08.12.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:21 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v2 01/14] iommufd: Convert struct iommufd_sw_msi_maps to a growable bitmap Date: Fri, 24 Jul 2026 17:12:05 +0200 Message-ID: <20260724151218.965929-2-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: aT0OyEBBZKy4pPGVVU5JNEbUg7cJHr8S X-Proofpoint-GUID: aT0OyEBBZKy4pPGVVU5JNEbUg7cJHr8S X-Authority-Analysis: v=2.4 cv=e/k2j6p/ c=1 sm=1 tr=0 ts=6a6380d8 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=GdI9VHRvGUSwsDbnIz4A:9 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX2mDhtv+nzEOZ 5ql0K/LBoDExOtMx916aoGyPv3gu7oJnfGu+D+mK4pRzGVancqNJUBWoT1ULIv3GppAym1R5s7w 3DSuZAw+jZrvL84Q+INmvkAh85fJlAKfe8t55H3yt5wU5ty7skqiABsmOJC5T18RSsYcJC88/pp POiYe8ssZEdx+IMS50lNV5K1PwT8oM7H2pcNp9NQM/l1ZjAcxoo3NsHWocmJ46CSL+ZIxsKcm5S 6r4Yufc/ko9z7hrabq8sBzvq+82GfJqLoUzhhTbhfkUSPyv0C6yeBgdfJkZBfJaDPzJIcv0AQpT OqqyRB+Qr26RJfwiy+4hsdgKg9YXqF8KnOko9DxVKcDcXyPNp0cUk/yfIG6UDiB0u72dXbayGNr FUO1Dtwy7e3ja2Sa98sn3JYw+2FRB8314yeWHbbR+H2bQ1DM8IfxPhsqD7+BSNfi48wnVXv4gEw tlwwNhMuoEg+SX0mATw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfXxZU2kC6/nrkK vAQfsq869/rhqLBXjID6XdyDHhezF8/9SX0LizT5Gb+nP8N+9DqSQudEY5Y8hLIaSZ1gA+33vSi 5SeNgWSEd3Gk2VuBCORD452L0vujIyI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" struct iommufd_sw_msi_maps currently uses a fixed 64-bit bitmap, capping the number of distinct SW MSI mappings a context or hwpt can track. An upcoming caller needs one mapping per possible CPU. Convert the fixed bitmap to a pointer plus size that grows on demand via iommufd_sw_msi_maps_ensure(). Add iommufd_sw_msi_maps_test_bit() alongside it: unlike the __set_bit() call sites, which always follow their own successful iommufd_sw_msi_maps_ensure() call on the same id, iommufd_group_setup_msi() tests an id from the fd-global sw_msi_list against a specific group's required_sw_msi map, which may not have been grown to cover that id yet. Signed-off-by: Andrew Jones --- drivers/iommu/iommufd/device.c | 3 +- drivers/iommu/iommufd/driver.c | 38 ++++++++++++++++--------- drivers/iommu/iommufd/hw_pagetable.c | 1 + drivers/iommu/iommufd/iommufd_private.h | 38 +++++++++++++++++++++++-- 4 files changed, 64 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c index 170a7005f0bc..402251c7b887 100644 --- a/drivers/iommu/iommufd/device.c +++ b/drivers/iommu/iommufd/device.c @@ -34,6 +34,7 @@ static void iommufd_group_release(struct kref *kref) NULL, GFP_KERNEL); iommu_group_put(igroup->group); mutex_destroy(&igroup->lock); + kfree(igroup->required_sw_msi.bitmap); kfree(igroup); } =20 @@ -384,7 +385,7 @@ static int iommufd_group_setup_msi(struct iommufd_group= *igroup, int rc; =20 if (cur->sw_msi_start !=3D igroup->sw_msi_start || - !test_bit(cur->id, igroup->required_sw_msi.bitmap)) + !iommufd_sw_msi_maps_test_bit(&igroup->required_sw_msi, cur->id)) continue; =20 rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, cur); diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 3b8067976eac..3cd617dfc351 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -196,13 +196,15 @@ iommufd_sw_msi_get_map(struct iommufd_ctx *ictx, phys= _addr_t msi_addr, list_for_each_entry(cur, &ictx->sw_msi_list, sw_msi_item) { if (cur->sw_msi_start !=3D sw_msi_start) continue; + if (cur->pgoff =3D=3D UINT_MAX) + return ERR_PTR(-EOVERFLOW); max_pgoff =3D max(max_pgoff, cur->pgoff + 1); if (cur->msi_addr =3D=3D msi_addr) return cur; } =20 - if (ictx->sw_msi_id >=3D - BITS_PER_BYTE * sizeof_field(struct iommufd_sw_msi_maps, bitmap)) + if (ictx->sw_msi_id =3D=3D UINT_MAX || + max_pgoff > (ULONG_MAX - sw_msi_start) / PAGE_SIZE) return ERR_PTR(-EOVERFLOW); =20 cur =3D kzalloc_obj(*cur); @@ -222,21 +224,26 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, struct iommufd_sw_msi_map *msi_map) { unsigned long iova; + int rc; =20 lockdep_assert_held(&ictx->sw_msi_lock); =20 + if (iommufd_sw_msi_maps_test_bit(&hwpt_paging->present_sw_msi, + msi_map->id)) + return 0; + iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; - if (!test_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap)) { - int rc; - - rc =3D iommu_map(hwpt_paging->common.domain, iova, - msi_map->msi_addr, PAGE_SIZE, - IOMMU_WRITE | IOMMU_READ | IOMMU_MMIO, - GFP_KERNEL_ACCOUNT); - if (rc) - return rc; - __set_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); - } + rc =3D iommufd_sw_msi_maps_ensure(&hwpt_paging->present_sw_msi, msi_map->= id); + if (rc) + return rc; + + rc =3D iommu_map(hwpt_paging->common.domain, iova, + msi_map->msi_addr, PAGE_SIZE, + IOMMU_WRITE | IOMMU_READ | IOMMU_MMIO, + GFP_KERNEL_ACCOUNT); + if (rc) + return rc; + __set_bit(msi_map->id, hwpt_paging->present_sw_msi.bitmap); return 0; } EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); @@ -290,6 +297,11 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, if (IS_ERR(msi_map)) return PTR_ERR(msi_map); =20 + rc =3D iommufd_sw_msi_maps_ensure(&handle->idev->igroup->required_sw_msi, + msi_map->id); + if (rc) + return rc; + rc =3D iommufd_sw_msi_install(ictx, hwpt_paging, msi_map); if (rc) return rc; diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/h= w_pagetable.c index 623cc608ca0c..54873de43eb0 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -32,6 +32,7 @@ void iommufd_hwpt_paging_destroy(struct iommufd_object *o= bj) } =20 __iommufd_hwpt_destroy(&hwpt_paging->common); + kfree(hwpt_paging->present_sw_msi.bitmap); refcount_dec(&hwpt_paging->ioas->obj.users); } =20 diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommuf= d/iommufd_private.h index 43fbc5bed8de..44d6dc94fb6b 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -29,11 +29,45 @@ struct iommufd_sw_msi_map { unsigned int id; }; =20 -/* Bitmap of struct iommufd_sw_msi_map::id */ +/* Bitmap of struct iommufd_sw_msi_map::id; starts empty, grows on demand.= */ struct iommufd_sw_msi_maps { - DECLARE_BITMAP(bitmap, 64); + unsigned long *bitmap; + unsigned int nbits; }; =20 +/* Grow bitmap to accommodate id. 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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69fb51c98c5sm150836a12.11.2026.07.24.08.12.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:23 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v2 02/14] iommufd: Add iommufd_sw_map_msi() Date: Fri, 24 Jul 2026 17:12:06 +0200 Message-ID: <20260724151218.965929-3-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: nlO8fwtJDcSOhkCoaAVkRUDgDyaqOtGn X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX9Vd0XVSgGnDI uKbwLSDErXTuwDm+YfpNP4xgppWp1CHC5h1rOWtuO32yUVhOGSWbsLe+oyBLjLLDY9mXQqj5bdp d7QVc/UgcVAh5qI9iXQKa9DfIMyYeKw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX9/QKDuNnBRqk W6xUlGdO7NdPrCg2Zcy15ONGdZQ57FndcOwwrqJ43JBBCN5RWXIAYr+cNKPuzTrlmvr8DRa+kwU 1gkKiR0j0GL1lGhaqujlR4zjpWxiy5ugurvFn4n8+YXl5nRuMCSBXZsjowqpL2uo8O4LzxuvSZY 80XlrBPsPNZ/2dOR1nRIoHBpewCCj/7Mt3mwnaunYfXOh5F0WfppmfDmf7iNhyX/XivH6KJw4Lv lSlO69jwbKlSlK+5MmRZn5Jj0OLirnTRkFi5AQiI6WMq9PItqZWY1RmZW1fSy/lB79rhFkacNdG 6HRN+SOfZjonpAwm/StMb5cvX6eNscyjWvmpyZvsvxbDPtgiBaX+saOmcP9hbhOoI64z2co6pbl XLrFx8gWHWDcQyII8Lgwce2XQ1REXMsAPajmIpdcJdYgRa8gFfrqJ347BdzaqBKcrLiyHIpk1pU jztx5Gn6F1XT8pKrPag== X-Proofpoint-GUID: nlO8fwtJDcSOhkCoaAVkRUDgDyaqOtGn X-Authority-Analysis: v=2.4 cv=GMA41ONK c=1 sm=1 tr=0 ts=6a6380d9 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=5IMjXt7tboKol454yg4A:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" Add a descriptor-free counterpart to iommufd_sw_msi(). The existing function is tied to a struct msi_desc and stores the result in the descriptor. This variant returns the IOVA directly so callers can pre-map MSI targets before any descriptor has been allocated. Signed-off-by: Andrew Jones --- drivers/iommu/iommu-priv.h | 11 +++++++ drivers/iommu/iommufd/driver.c | 59 +++++++++++++++++++++++++--------- 2 files changed, 55 insertions(+), 15 deletions(-) diff --git a/drivers/iommu/iommu-priv.h b/drivers/iommu/iommu-priv.h index aaffad5854fc..f60373cd2f70 100644 --- a/drivers/iommu/iommu-priv.h +++ b/drivers/iommu/iommu-priv.h @@ -55,12 +55,23 @@ int iommu_replace_group_handle(struct iommu_group *grou= p, #if IS_ENABLED(CONFIG_IOMMUFD_DRIVER_CORE) && IS_ENABLED(CONFIG_IRQ_MSI_IO= MMU) int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, phys_addr_t msi_addr); +int iommufd_sw_map_msi(struct iommu_domain *domain, struct device *dev, + phys_addr_t msi_addr, size_t required_size, + dma_addr_t *msi_iova, unsigned int *msi_shift); #else /* !CONFIG_IOMMUFD_DRIVER_CORE || !CONFIG_IRQ_MSI_IOMMU */ static inline int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, phys_addr_t msi_addr) { return -EOPNOTSUPP; } + +static inline int iommufd_sw_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) +{ + return -EOPNOTSUPP; +} #endif /* CONFIG_IOMMUFD_DRIVER_CORE && CONFIG_IRQ_MSI_IOMMU */ =20 int iommu_replace_device_pasid(struct iommu_domain *domain, diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index 3cd617dfc351..9aad5c69d4ac 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -249,15 +249,22 @@ int iommufd_sw_msi_install(struct iommufd_ctx *ictx, EXPORT_SYMBOL_NS_GPL(iommufd_sw_msi_install, "IOMMUFD_INTERNAL"); =20 /* - * Called by the irq code if the platform translates the MSI address throu= gh the - * IOMMU. msi_addr is the physical address of the MSI page. iommufd will - * allocate a fd global iova for the physical page that is the same on all - * domains and devices. + * Descriptor-free counterpart to iommufd_sw_msi(). Maps an MSI physical p= age + * into the domain and returns the IOVA. Used for pre-mapping MSI targets = before + * any MSI descriptor has been set (e.g. IMSIC doorbell pages). The IOVA is + * global to the iommufd file descriptor: every domain and device using the + * same MSI parameters gets the same IOVA. + * + * msi_addr is the exact byte offset of the MSI doorbell; the caller must = have + * verified it is contained within an MMIO region safe to map at PAGE_SIZE= . If + * required_size is non-zero it must equal PAGE_SIZE. + * + * The caller must hold @dev's iommu group mutex. */ -int iommufd_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) +int iommufd_sw_map_msi(struct iommu_domain *domain, struct device *dev, + phys_addr_t msi_addr, size_t required_size, + dma_addr_t *msi_iova, unsigned int *msi_shift) { - struct device *dev =3D msi_desc_to_dev(desc); struct iommufd_hwpt_paging *hwpt_paging; struct iommu_attach_handle *raw_handle; struct iommufd_attach_handle *handle; @@ -266,6 +273,12 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, unsigned long iova; int rc; =20 + *msi_iova =3D 0; + *msi_shift =3D 0; + + if (required_size && required_size !=3D PAGE_SIZE) + return -EOPNOTSUPP; + /* * It is safe to call iommu_attach_handle_get() here because the iommu * core code invokes this under the group mutex which also prevents any @@ -286,13 +299,7 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, =20 ictx =3D handle->idev->ictx; guard(mutex)(&ictx->sw_msi_lock); - /* - * The input msi_addr is the exact byte offset of the MSI doorbell, we - * assume the caller has checked that it is contained with a MMIO region - * that is secure to map at PAGE_SIZE. - */ - msi_map =3D iommufd_sw_msi_get_map(handle->idev->ictx, - msi_addr & PAGE_MASK, + msi_map =3D iommufd_sw_msi_get_map(ictx, msi_addr & PAGE_MASK, handle->idev->igroup->sw_msi_start); if (IS_ERR(msi_map)) return PTR_ERR(msi_map); @@ -308,7 +315,29 @@ int iommufd_sw_msi(struct iommu_domain *domain, struct= msi_desc *desc, __set_bit(msi_map->id, handle->idev->igroup->required_sw_msi.bitmap); =20 iova =3D msi_map->sw_msi_start + msi_map->pgoff * PAGE_SIZE; - msi_desc_set_iommu_msi_iova(desc, iova, PAGE_SHIFT); + *msi_iova =3D iova; + *msi_shift =3D PAGE_SHIFT; + return 0; +} +EXPORT_SYMBOL_NS_GPL(iommufd_sw_map_msi, "IOMMUFD"); + +/* + * Called by the irq layer when the platform translates MSI addresses thro= ugh + * the IOMMU. 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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69fb5958ea0sm88142a12.31.2026.07.24.08.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:25 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v2 03/14] iommu/dma: Add iommu_dma_sw_map_msi() Date: Fri, 24 Jul 2026 17:12:07 +0200 Message-ID: <20260724151218.965929-4-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: AqB9GDbN-EfBrK4ciDPjM-A-j9GqVxrg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX/lUzaN+quzF/ anVBeG8uVosZ/3YM2u2omRn9hR3ch56oCLOEipAH8Epfr7LnYvLbcnExnSs0J5WB3KEUTkSpTxP ZmMz/o73kc6QVrNsc8SeufPkG8iLa63P6hbLNv9lH8zU8tKSB9McmeklYfEf/Dp3T7xmmPlDTFV t77DJeRPEL4GoGW4wgnJZlJIb6598WN7FXu8Qhg7ewe8jzmQTVyqReWbmIVmQ+TeQteUeuqFAhk 1+1EpRZdCXI8pFBc0n5QBXNDsZMCAOVYSTUBSu11RIZsfHkYr6YYL3s6Tenc/GmgZaeI1fKfx44 uGGHB3ODXPDJEXJJldaSbDi/eoomjIAVG/8GNMRDxvuZ3DYd7a29NGqDVlxSpgH5KPTB0i0bnb8 l5FbSRaQPtpYd7iKvVDYfCCY/wlYByVN3MRIaw7gK5S8v9Kb9hiS8xHsoKQ2TFp3jwNXvqhAB5d VUTHmHbSErU15lVV89Q== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfXw04Pr69J2QiC 2OukwGEPjEpM0wMuNM4OcfcVMnE8PM35Clv93LmTU6h/ikdtgDsPz7rRXaAZdTJFaY5HxudmL58 wJ3HKC7PIcOTLBX+QunCmTUUnEU4QVA= X-Authority-Analysis: v=2.4 cv=DLW/JSNb c=1 sm=1 tr=0 ts=6a6380db cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=B9hF7e9JpKM1iJhnVVUA:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-ORIG-GUID: AqB9GDbN-EfBrK4ciDPjM-A-j9GqVxrg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" Add a descriptor-free counterpart to iommu_dma_sw_msi(). The existing function is tied to a struct msi_desc and stores the result in the descriptor. This variant returns the IOVA directly so callers can pre-map MSI targets before any descriptor has been allocated. Callers may pass a required mapping size so MSI doorbells that must not share a larger IOMMU leaf, such as RISC-V IMSIC files, can fail before a mapping is installed. Signed-off-by: Andrew Jones --- drivers/iommu/dma-iommu.c | 39 +++++++++++++++++++++++++++++++-------- drivers/iommu/dma-iommu.h | 12 ++++++++++++ 2 files changed, 43 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 9abaec0703ef..c26b071d744a 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -2234,24 +2234,47 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi= _page(struct device *dev, return NULL; } =20 -int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, - phys_addr_t msi_addr) +int iommu_dma_sw_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) { - struct device *dev =3D msi_desc_to_dev(desc); const struct iommu_dma_msi_page *msi_page; + size_t size; =20 - if (!has_msi_cookie(domain)) { - msi_desc_set_iommu_msi_iova(desc, 0, 0); + *msi_iova =3D 0; + *msi_shift =3D 0; + + if (!has_msi_cookie(domain)) return 0; - } + + size =3D cookie_msi_granule(domain); + if (required_size && size !=3D required_size) + return -EOPNOTSUPP; =20 iommu_group_mutex_assert(dev); msi_page =3D iommu_dma_get_msi_page(dev, msi_addr, domain); if (!msi_page) return -ENOMEM; =20 - msi_desc_set_iommu_msi_iova(desc, msi_page->iova, - ilog2(cookie_msi_granule(domain))); + *msi_iova =3D msi_page->iova; + *msi_shift =3D ilog2(size); + return 0; +} + +int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc, + phys_addr_t msi_addr) +{ + struct device *dev =3D msi_desc_to_dev(desc); + dma_addr_t msi_iova; + unsigned int msi_shift; + int ret; + + ret =3D iommu_dma_sw_map_msi(domain, dev, msi_addr, 0, &msi_iova, &msi_sh= ift); + if (ret) + return ret; + + msi_desc_set_iommu_msi_iova(desc, msi_iova, msi_shift); return 0; } =20 diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h index 040d00252563..3e1adeafdcac 100644 --- a/drivers/iommu/dma-iommu.h +++ b/drivers/iommu/dma-iommu.h @@ -19,6 +19,10 @@ int iommu_dma_init_fq(struct iommu_domain *domain); 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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69fb50bd30fsm159683a12.5.2026.07.24.08.12.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:27 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v2 04/14] iommu/dma: Add iommu_dma_map_msi() Date: Fri, 24 Jul 2026 17:12:08 +0200 Message-ID: <20260724151218.965929-5-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: z_0SYjLK7RKQdvcnw-UY3xfdQ65IOMav X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX12EmzFfY6Svk 6zyw7KHiwr6JEW/UGwLzg52vORH9EhFPA321ALAu7U5i1aVdvq0h8Iahpeb2+y3zY2VZb9yHmO9 BmDqrDnGi2wKVJIoKWfLzgs9K7BKP+d73D8h0d+I8GEjz5DyQWaDw8iPn1WJmOTEx1WO0tDB2vI tpxQxZnh3SnZvw6WUXgoP6KH1u0nUzoh1ZyVHFzqkU8iRuz3z62hllEfygNifHf4SxTKsag1KSN Scr1Si5SFRZOpeF3ja6WyrP+c7CvprOP6qU+Gfr2cP3vi3S0szxaBhqy8boshfZDIdPM6xF2IgA PHNo28TtUsDO9nIRCKSfHC9Ax3jp3IL3rZIj7iI43sjd8A9QSGBvzM5GPQbj8EfwKA/mavBCfWj NtwibeXmnAUxdva7Pgr2kj4Sxk4jTsCjRXWVvinBb0fT0rEjWlscRwYUiShdci+EkL7sU+QSuWI M8ZhgN3oGtBRle/ccrw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfXwqxgDAqV0GzR vxjsaBLtnUsWGSr4oG0jULLzUgTi9m7PULu/pG//3WWmEYljmhL7oiiEWcndZIb5psW5vAjymNP Lr55xdsU7XSLIEkhReXB2a+59Q5NW84= X-Authority-Analysis: v=2.4 cv=DLW/JSNb c=1 sm=1 tr=0 ts=6a6380de cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=vjeZBn8P1qzF27HCuS4A:9 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: z_0SYjLK7RKQdvcnw-UY3xfdQ65IOMav X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" Add iommu_dma_map_msi() to map an MSI doorbell and return the IOVA and granule shift to callers that need their own PA->IOVA lookup, dispatching to the DMA-IOMMU or iommufd cookie implementation as appropriate. Callers may pass a required mapping size so MSI doorbells that must not share a larger IOMMU leaf, such as RISC-V IMSIC files, can fail before a mapping is installed. iommu_dma_map_msi() requires the caller to hold @dev's iommu group mutex, but struct iommu_group is private to drivers/iommu/iommu.c, so a caller outside the core (e.g. an interrupt-remapping driver building a table of mappings ahead of any MSI descriptor existing) has no way to take it. Add iommu_group_mutex_lock()/iommu_group_mutex_unlock() to bridge that gap, next to the existing iommu_group_mutex_assert(). Signed-off-by: Andrew Jones --- drivers/iommu/iommu.c | 86 +++++++++++++++++++++++++++++++++++++++++-- include/linux/iommu.h | 22 +++++++++++ 2 files changed, 104 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index e8f13dcebbde..b980c11dcfe8 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -1364,15 +1364,46 @@ void iommu_group_remove_device(struct device *dev) } EXPORT_SYMBOL_GPL(iommu_group_remove_device); =20 -#if IS_ENABLED(CONFIG_LOCKDEP) && IS_ENABLED(CONFIG_IOMMU_API) +#if IS_ENABLED(CONFIG_IOMMU_API) +/* + * iommu_group_mutex_lock(), iommu_group_mutex_unlock(), and + * iommu_group_mutex_assert() must be called after device group param is + * set. + */ + +/** + * iommu_group_mutex_lock - Lock the iommu group mutex for a device + * @dev: the device whose group mutex should be locked + * + * Callers that need to invoke a function documented as requiring the + * device's iommu group mutex (e.g. iommu_dma_map_msi()) from outside + * drivers/iommu/ use this instead of reaching into struct iommu_group, + * which is private to the core. Must be paired with + * iommu_group_mutex_unlock(). + */ +void iommu_group_mutex_lock(struct device *dev) +{ + mutex_lock(&dev->iommu_group->mutex); +} +EXPORT_SYMBOL_GPL(iommu_group_mutex_lock); + +/** + * iommu_group_mutex_unlock - Unlock the iommu group mutex for a device + * @dev: the device whose group mutex should be unlocked + */ +void iommu_group_mutex_unlock(struct device *dev) +{ + mutex_unlock(&dev->iommu_group->mutex); +} +EXPORT_SYMBOL_GPL(iommu_group_mutex_unlock); + +#if IS_ENABLED(CONFIG_LOCKDEP) /** * iommu_group_mutex_assert - Check device group mutex lock * @dev: the device that has group param set * * This function is called by an iommu driver to check whether it holds * group mutex lock for the given device or not. - * - * Note that this function must be called after device group param is set. */ void iommu_group_mutex_assert(struct device *dev) { @@ -1381,7 +1412,8 @@ void iommu_group_mutex_assert(struct device *dev) lockdep_assert_held(&group->mutex); } EXPORT_SYMBOL_GPL(iommu_group_mutex_assert); -#endif +#endif /* CONFIG_LOCKDEP */ +#endif /* CONFIG_IOMMU_API */ =20 static struct device *iommu_group_first_dev(struct iommu_group *group) { @@ -4223,6 +4255,52 @@ void pci_dev_reset_iommu_done(struct pci_dev *pdev) EXPORT_SYMBOL_GPL(pci_dev_reset_iommu_done); =20 #if IS_ENABLED(CONFIG_IRQ_MSI_IOMMU) +/** + * iommu_dma_map_msi() - Map an MSI page in an IOMMU domain + * @domain: IOMMU domain to map into + * @dev: Device used to allocate the IOVA + * @msi_addr: MSI target address to be mapped + * @required_size: Required mapping size, or 0 to accept any size + * @msi_iova: IOVA for @msi_addr, or 0 for passthrough + * @msi_shift: Mapping granule shift, or 0 for passthrough + * + * The caller must hold @dev's iommu group mutex, e.g. via + * iommu_group_mutex_lock()/iommu_group_mutex_unlock(). This function does + * not take the mutex itself because callers building a table of mappings + * (e.g. one IOVA per possible CPU's IMSIC page) call it in a loop; locking + * inside would mean re-acquiring the mutex on every iteration and would n= ot + * stop the domain from changing between iterations, leaving the table + * inconsistent. The caller locks once around the whole loop instead. + * + * Return: 0 on success or negative error code if the mapping failed. + */ +int iommu_dma_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift) +{ + *msi_iova =3D 0; + *msi_shift =3D 0; + + if (!domain) + return -EINVAL; + + if (domain->type =3D=3D IOMMU_DOMAIN_IDENTITY) + return 0; + + switch (domain->cookie_type) { + case IOMMU_COOKIE_DMA_MSI: + case IOMMU_COOKIE_DMA_IOVA: + return iommu_dma_sw_map_msi(domain, dev, msi_addr, + required_size, msi_iova, msi_shift); + case IOMMU_COOKIE_IOMMUFD: + return iommufd_sw_map_msi(domain, dev, msi_addr, + required_size, msi_iova, msi_shift); + default: + return -EOPNOTSUPP; + } +} + /** * iommu_dma_prepare_msi() - Map the MSI page in the IOMMU domain * @desc: MSI descriptor, will store the MSI page diff --git a/include/linux/iommu.h b/include/linux/iommu.h index d20aa6f6863a..c36540b75072 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -1561,8 +1561,22 @@ static inline void pci_dev_reset_iommu_done(struct p= ci_dev *pdev) =20 #ifdef CONFIG_IRQ_MSI_IOMMU #ifdef CONFIG_IOMMU_API +int iommu_dma_map_msi(struct iommu_domain *domain, + struct device *dev, phys_addr_t msi_addr, + size_t required_size, dma_addr_t *msi_iova, + unsigned int *msi_shift); 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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1c32f151fbsm365176566b.56.2026.07.24.08.12.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:30 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com, Nutty Liu Subject: [PATCH v2 05/14] genirq/msi: Provide DOMAIN_BUS_MSI_REMAP Date: Fri, 24 Jul 2026 17:12:09 +0200 Message-ID: <20260724151218.965929-6-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: klNeAvMHdJ5sB0DffSpyERyDx7nwvN7L X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfXx94VQUueE4xC iV/qQjpJe+i87jAQG+4FJAHi0RYazSBx1Jt2Dpdce5JqWAouNkBrEpZrDNehEWAxje0TGJHU34Q a738V0mgNYM/8949LiHZsX0T+HpVpmwigYD/sqCkJglUkwGoDf7zca2E1to3bIZ42jiLdnQbAeW ggbmbdhXfGsserqua61CRwzustNEcNQqHywU2JFFIjhH5uHd0WZFtVFRBZUMh708H9PhmrVHt1J xBzsMlayQTBqajQ+roFY0IxBAd1YCWSNsgoWMKj0Gn2m9/E+/8mOteooM08MBYZ6Fyr5RhQFsKR 20RZ4Iru/BsgrEraqCh6+Fe07F3lyBW0Gekv0SvmLhCXGHQnTHqtPiYQeL93hrdfyNTl3rr5cxh DS62M8etj1tCr0yOkfyIrYiTXO7PpWoaiG9g4WqrgYzhiJTcK2Zf1BXOVu9RhMLpfdgR+gCdXhU uw7SkpCwGRnF9A+zE1g== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX2rvtYDBAWdRN p41jRZOO0RhmyiScWvN/OoYQt1G1iBhPRWdXx2yYo4afXEWXA+MI6/k/VbSFyn/Cs6uI58xn4+N KNWczltGtWxSfLXNkuGszkwTkpg1VKQ= X-Authority-Analysis: v=2.4 cv=DLW/JSNb c=1 sm=1 tr=0 ts=6a6380e0 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=69EAbJreAAAA:8 a=cHhBG6FuOey2j-0mYlgA:9 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-ORIG-GUID: klNeAvMHdJ5sB0DffSpyERyDx7nwvN7L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" Add a bus token for MSI domains that remap interrupts, needed by the upcoming RISC-V IOMMU interrupt-remapping domain to distinguish itself from NEXUS domains. The token is generic because remapping itself is the only property that needs to be conveyed -- there is nothing RISC-V-specific about it. Such a domain implements init_dev_msi_info() via msi_parent_init_dev_msi_info(), which leaves 'domain' pointing at the NEXUS domain while 'real_parent' points at the remap domain itself. Accept that combination in msi_lib_init_dev_msi_info(); no other msi-lib changes are needed. Signed-off-by: Andrew Jones Reviewed-by: Nutty Liu --- drivers/irqchip/irq-msi-lib.c | 8 ++++---- include/linux/irqdomain_defs.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-msi-lib.c b/drivers/irqchip/irq-msi-lib.c index 45e0ed3134ce..9027dfbab15e 100644 --- a/drivers/irqchip/irq-msi-lib.c +++ b/drivers/irqchip/irq-msi-lib.c @@ -36,14 +36,14 @@ bool msi_lib_init_dev_msi_info(struct device *dev, stru= ct irq_domain *domain, return false; =20 /* - * MSI parent domain specific settings. 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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1c32af243fsm367656066b.26.2026.07.24.08.12.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:32 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v2 06/14] irqchip/riscv-imsic: Compose MSI updates through the hierarchy Date: Fri, 24 Jul 2026 17:12:10 +0200 Message-ID: <20260724151218.965929-7-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=GJE41ONK c=1 sm=1 tr=0 ts=6a6380e3 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=3qtCRIp3mPeaHrg9mH0A:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX71xG1geMLCV8 zWM1T7i932hs0CKLSC5alKK8fOVO645EOEW+pmJIv4GYPdBbBnjB8nCe8+OMfNsKEH8LMQLk+/3 +/Ac/Cz1hgtXzfOBJdNrDlzkgRXVqOZU6D4ioqKBSrcEA9e9Tv66Ad+BjbAhVCV95EXubrTAckB kowNzmn6OmEB0uj53AAQIazsTXXJg1uBkHjfYvPxvJdVzg4fpyy/ZmjAZf24KmbI5hvps5JIHVp 7lN+1aPa8JkXfEQuO4dm0LX4boVygINeGTSxjsOLG14qiI2fLCqN/0mQJtP5q4g4Z9e2ZlukkUK UbOrLxPGUjt3bIYgorXxy0tyeWFsEY5tq0HNM/PogKjvUzHr/I008Otd9lmvhqGKZdBdFUe4zhM eMZFszl2djPnZMl22xnVAu25bk0kC/8/LuN92UCowe8pyPItSs36sSalzF3o7m9BXstsiOFh74z dytWmV58TJdmUg4Hcqg== X-Proofpoint-ORIG-GUID: e6IBbV42WH1IS12NjRHysaSW3GtM-ud4 X-Proofpoint-GUID: e6IBbV42WH1IS12NjRHysaSW3GtM-ud4 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX23rkcNTZ15vM 7WJCncQErJIQl5t659sjS/m53OrZJwMNZDh9uotbdCqNt07KgKdZIiOC8mn0spRFFuWyCtgCJwM thoN/vuvanFKqZhSCgMpvrMOkcHzpXs= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" imsic_irq_set_affinity() wrote the new IMSIC target straight to the device via imsic_msi_update_msg(), bypassing the irqdomain hierarchy. That skips any intermediate IOMMU irqdomain sitting between IMSIC and the device, so a remapped device would keep the pre-remap physical address after every affinity change. Compose MSI updates via irq_chip_compose_msi_msg() starting from the top of the hierarchy instead, so an intermediate remap domain gets to translate the target before the device is written. For the temporary vector used by non-atomic affinity updates, compose the current vector through the hierarchy before d->chip_data is switched to the new vector, then replace only msg.data with the new local ID. This preserves the required old-address/new-data temporary target while also allowing an intermediate remap domain to refresh or clear any MSI IOVA state cached on the device's MSI descriptor. Moving the final write to after d->chip_data =3D new_vec is required because irq_chip_compose_msi_msg() reads d->chip_data. Keep it before updating effective affinity and migrating vector state so the device is retargeted before the old vector is disabled. Signed-off-by: Andrew Jones --- drivers/irqchip/irq-riscv-imsic-platform.c | 27 ++++++++-------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/i= rq-riscv-imsic-platform.c index 643c8e459611..5634641dc223 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -90,19 +90,12 @@ static void imsic_irq_compose_msg(struct irq_data *d, s= truct msi_msg *msg) } =20 #ifdef CONFIG_SMP -static void imsic_msi_update_msg(struct irq_data *d, struct imsic_vector *= vec) -{ - struct msi_msg msg =3D { }; - - imsic_irq_compose_vector_msg(vec, &msg); - irq_data_get_irq_chip(d)->irq_write_msi_msg(d, &msg); -} - static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask= *mask_val, bool force) { + struct irq_data *top =3D irq_get_irq_data(d->irq); struct imsic_vector *old_vec, *new_vec; - struct imsic_vector tmp_vec; + struct msi_msg msg =3D { }; =20 /* * Requirements for the downstream irqdomains (or devices): @@ -153,20 +146,20 @@ static int imsic_irq_set_affinity(struct irq_data *d,= const struct cpumask *mask */ if (!irq_can_move_in_process_context(d) && new_vec->local_id !=3D old_vec->local_id) { - /* Setup temporary vector */ - tmp_vec.cpu =3D old_vec->cpu; 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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69fb5543aacsm101916a12.14.2026.07.24.08.12.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:35 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v2 07/14] iommu/riscv: Add IRQ domain for interrupt remapping Date: Fri, 24 Jul 2026 17:12:11 +0200 Message-ID: <20260724151218.965929-8-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: oMJFz0FCsSxaYrVTYV3MeNx1d_Y924cT X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX9uKScbsO6xR5 C/DPTScfnzA9W09QAoODG7NLlVMUZNdjvqtja1+K/wEbnnSithzlRY5T6yRSnJFGrQefn9rch94 inVlp9A0WF5JdqBfRxgHdlEij7wQw3E= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX4EAMIm2BXxi5 2go5azMHh/1pUrClF/e5hYvaa0mJA3Bm2WbvfBdZjjfGrcXeYi1G/UwgOxzkDdOUwGUyPTYWAOW A7TbQSIJbS8r9l6DniJQBGh6bVruLOOLDqa4lcSSj0B8TJr57A3biIXNY1+gJwnbw2sRJ/VJqwJ pLHzaDyFVeOW7904xafNmgFRH+NNq0vyJQGv+j5WR2vzqB/saB81802p0XcN30EUeVDVdRHQC+6 o6iFyVuv2pRSC0AM2eJnhlTpz9ScDufBNI/Bl42OsEoNsC2DHLc9R+LKYC3agV4R6BThRG3aJlg t/LhRpwlRBNCHbtaV4qkpIn3c1omORuR2sjcDuO4Bbn1mlUMUMCrBbBa/xiwZFIbuYtIObRekGN yBrV11d/IZ+bcVWiX/ozx3K0rVjfeXl9U73S9ObywFw5yVGv9Vb8MGyvsDntkEXO0/nvD1h6+dJ 0L34lsrrCJbVDAtTRcg== X-Proofpoint-GUID: oMJFz0FCsSxaYrVTYV3MeNx1d_Y924cT X-Authority-Analysis: v=2.4 cv=GMA41ONK c=1 sm=1 tr=0 ts=6a6380e5 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=qlKvAlJJmACmlsHknIYA:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" Create a per-device MSI parent irqdomain as the hierarchy hook for future interrupt remapping. The remapping tables will be owned by the attached paging domain since the MSI IOVA mappings live in its page tables. The domain is installed from probe_device() and removed from release_device(). This is only the initial skeleton: it does not remap interrupts yet, and non-paging IOMMU domains will fall back to the raw IMSIC physical address when remapping is added. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/Makefile | 2 +- drivers/iommu/riscv/iommu-ir.c | 119 ++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 46 ++++++----- drivers/iommu/riscv/iommu.h | 27 +++++++ include/linux/irqchip/riscv-imsic.h | 7 ++ 5 files changed, 182 insertions(+), 19 deletions(-) create mode 100644 drivers/iommu/riscv/iommu-ir.c diff --git a/drivers/iommu/riscv/Makefile b/drivers/iommu/riscv/Makefile index b5929f9f23e6..9c83f877d50f 100644 --- a/drivers/iommu/riscv/Makefile +++ b/drivers/iommu/riscv/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D iommu.o iommu-platform.o +obj-y +=3D iommu.o iommu-ir.o iommu-platform.o obj-$(CONFIG_RISCV_IOMMU_PCI) +=3D iommu-pci.o diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c new file mode 100644 index 000000000000..5873addf2a1b --- /dev/null +++ b/drivers/iommu/riscv/iommu-ir.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * IOMMU Interrupt Remapping + * + * Copyright (c) 2026 Qualcomm Technologies, Inc. + */ +#include +#include +#include + +#include "iommu.h" + +static struct irq_chip riscv_iommu_ir_irq_chip =3D { + .name =3D "IOMMU-IR", + .irq_ack =3D irq_chip_ack_parent, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, +}; + +static int riscv_iommu_ir_irq_domain_alloc_irqs(struct irq_domain *irqdoma= in, + unsigned int irq_base, unsigned int nr_irqs, + void *arg) +{ + struct irq_data *data; + int i, ret; + + ret =3D irq_domain_alloc_irqs_parent(irqdomain, irq_base, nr_irqs, arg); + if (ret) + return ret; + + for (i =3D 0; i < nr_irqs; i++) { + data =3D irq_domain_get_irq_data(irqdomain, irq_base + i); + data->chip =3D &riscv_iommu_ir_irq_chip; + } + + return 0; +} + +static const struct irq_domain_ops riscv_iommu_ir_irq_domain_ops =3D { + .alloc =3D riscv_iommu_ir_irq_domain_alloc_irqs, + .free =3D irq_domain_free_irqs_parent, +}; + +static const struct msi_parent_ops riscv_iommu_ir_msi_parent_ops =3D { + .prefix =3D "IR-", + .supported_flags =3D MSI_GENERIC_FLAGS_MASK | + MSI_FLAG_PCI_MSIX, + .required_flags =3D MSI_FLAG_USE_DEF_DOM_OPS | + MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSI_MASK_PARENT, + .chip_flags =3D MSI_CHIP_FLAG_SET_ACK, + .init_dev_msi_info =3D msi_parent_init_dev_msi_info, +}; + +struct irq_domain *riscv_iommu_ir_irq_domain_create(struct device *dev, + struct riscv_iommu_info *info) +{ + struct irq_domain *irqparent =3D dev_get_msi_domain(dev); + struct irq_domain *irqdomain; + struct fwnode_handle *fn; + char *fwname __free(kfree) =3D NULL; + + if (!irqparent) + return NULL; + + fwname =3D kasprintf(GFP_KERNEL, "IOMMU-IR-%s", dev_name(dev)); + if (!fwname) + return ERR_PTR(-ENOMEM); + + fn =3D irq_domain_alloc_named_fwnode(fwname); + if (!fn) + return ERR_PTR(-ENOMEM); + + irqdomain =3D irq_domain_create_hierarchy(irqparent, 0, 0, fn, + &riscv_iommu_ir_irq_domain_ops, + info); + if (!irqdomain) { + irq_domain_free_fwnode(fn); + return ERR_PTR(-ENOMEM); + } + + /* + * The RISC-V IOMMU doesn't validate MSI data, so we can't set + * IRQ_DOMAIN_FLAG_ISOLATED_MSI. This means VFIO requires + * allow_unsafe_interrupts. + */ + irqdomain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; + irqdomain->msi_parent_ops =3D &riscv_iommu_ir_msi_parent_ops; + irq_domain_update_bus_token(irqdomain, DOMAIN_BUS_MSI_REMAP); + + dev_set_msi_domain(dev, irqdomain); + + return irqdomain; +} + +void riscv_iommu_ir_irq_domain_remove(struct device *dev, struct riscv_iom= mu_info *info) +{ + struct fwnode_handle *fn; + + if (!info->irqdomain) + return; + + dev_set_msi_domain(dev, info->irqdomain->parent); + fn =3D info->irqdomain->fwnode; + irq_domain_remove(info->irqdomain); + info->irqdomain =3D NULL; + irq_domain_free_fwnode(fn); +} + +int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain,= struct device *dev, + struct iommu_domain *old) +{ + return 0; +} + +void riscv_iommu_ir_free_paging_domain(struct iommu_domain *iommu_domain) +{ +} diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index cec3ddd7ab10..bfe606a0cb9a 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -19,9 +19,9 @@ #include #include #include +#include #include #include -#include =20 #include "../iommu-pages.h" #include "iommu-bits.h" @@ -810,26 +810,9 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iom= mu_device *iommu, return 0; } =20 -/* This struct contains protection domain specific IOMMU driver data. */ -struct riscv_iommu_domain { - union { - struct iommu_domain domain; - struct pt_iommu_riscv_64 riscvpt; - }; - struct list_head bonds; - spinlock_t lock; /* protect bonds list updates. */ - int pscid; -}; -PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.iommu, domain); - #define iommu_domain_to_riscv(iommu_domain) \ container_of(iommu_domain, struct riscv_iommu_domain, domain) =20 -/* Private IOMMU data for managed devices, dev_iommu_priv_* */ -struct riscv_iommu_info { - struct riscv_iommu_domain *domain; -}; - /* * Linkage between an iommu_domain and attached devices. * @@ -1258,6 +1241,8 @@ static void riscv_iommu_free_paging_domain(struct iom= mu_domain *iommu_domain) =20 WARN_ON(!list_empty(&domain->bonds)); =20 + riscv_iommu_ir_free_paging_domain(iommu_domain); + if ((int)domain->pscid > 0) ida_free(&riscv_iommu_pscids, domain->pscid); =20 @@ -1289,6 +1274,7 @@ static int riscv_iommu_attach_paging_domain(struct io= mmu_domain *iommu_domain, struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); struct pt_iommu_riscv_64_hw_info pt_info; u64 fsc, ta; + int ret; =20 pt_iommu_riscv_64_hw_info(&domain->riscvpt, &pt_info); =20 @@ -1303,6 +1289,12 @@ static int riscv_iommu_attach_paging_domain(struct i= ommu_domain *iommu_domain, if (riscv_iommu_bond_link(domain, dev)) return -ENOMEM; =20 + ret =3D riscv_iommu_ir_attach_paging_domain(iommu_domain, dev, old); + if (ret) { + riscv_iommu_bond_unlink(domain, dev); + return ret; + } + riscv_iommu_iodir_update(iommu, dev, fsc, ta); riscv_iommu_bond_unlink(info->domain, dev); info->domain =3D domain; @@ -1430,6 +1422,7 @@ static int riscv_iommu_of_xlate(struct device *dev, c= onst struct of_phandle_args static struct iommu_device *riscv_iommu_probe_device(struct device *dev) { struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev); + struct irq_domain *irqdomain =3D NULL; struct riscv_iommu_device *iommu; struct riscv_iommu_info *info; struct riscv_iommu_dc *dc; @@ -1453,6 +1446,21 @@ static struct iommu_device *riscv_iommu_probe_device= (struct device *dev) info =3D kzalloc_obj(*info); if (!info) return ERR_PTR(-ENOMEM); + + if (imsic_enabled()) { + irqdomain =3D riscv_iommu_ir_irq_domain_create(dev, info); + if (IS_ERR(irqdomain)) { + kfree(info); + return ERR_CAST(irqdomain); + } + } + + /* + * irqdomain is NULL when it's not necessary; either there aren't + * any IMSICs or no MSI domain has been set up for the device. + */ + info->irqdomain =3D irqdomain; + /* * Allocate and pre-configure device context entries in * the device directory. Do not mark the context valid yet. @@ -1461,6 +1469,7 @@ static struct iommu_device *riscv_iommu_probe_device(= struct device *dev) for (i =3D 0; i < fwspec->num_ids; i++) { dc =3D riscv_iommu_get_dc(iommu, fwspec->ids[i]); if (!dc) { + riscv_iommu_ir_irq_domain_remove(dev, info); kfree(info); return ERR_PTR(-ENODEV); } @@ -1478,6 +1487,7 @@ static void riscv_iommu_release_device(struct device = *dev) { struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); =20 + riscv_iommu_ir_irq_domain_remove(dev, info); kfree_rcu_mightsleep(info); } =20 diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 46df79dd5495..5d83537911b6 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -14,9 +14,29 @@ #include #include #include +#include +#include =20 #include "iommu-bits.h" =20 +/* This struct contains protection domain specific IOMMU driver data. */ +struct riscv_iommu_domain { + union { + struct iommu_domain domain; + struct pt_iommu_riscv_64 riscvpt; + }; + struct list_head bonds; + spinlock_t lock; /* protect bonds list updates. */ + int pscid; +}; +PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.iommu, domain); + +/* Private IOMMU data for managed devices, dev_iommu_priv_* */ +struct riscv_iommu_info { + struct riscv_iommu_domain *domain; + struct irq_domain *irqdomain; +}; + struct riscv_iommu_device; =20 struct riscv_iommu_queue { @@ -66,6 +86,13 @@ int riscv_iommu_init(struct riscv_iommu_device *iommu); void riscv_iommu_remove(struct riscv_iommu_device *iommu); void riscv_iommu_disable(struct riscv_iommu_device *iommu); =20 +struct irq_domain *riscv_iommu_ir_irq_domain_create(struct device *dev, + struct riscv_iommu_info *info); +void riscv_iommu_ir_irq_domain_remove(struct device *dev, struct riscv_iom= mu_info *info); +int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain,= struct device *dev, + struct iommu_domain *old); +void riscv_iommu_ir_free_paging_domain(struct iommu_domain *iommu_domain); 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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69fb51c9691sm151975a12.7.2026.07.24.08.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:37 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v2 08/14] iommu/riscv: Prepare info->domain for concurrent RCU read access Date: Fri, 24 Jul 2026 17:12:12 +0200 Message-ID: <20260724151218.965929-9-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX4T3tmqCDPZT+ pLF19wJhnia9imRdFAY3BFxrZxOgWhPNeuC90gfOlQmgMIhKBsxkgFTDoSbwii1jmtbvVgy6rYp CADDYnbNwSFh6NsdtPtglBy5oPqWock= X-Authority-Analysis: v=2.4 cv=TvrWQjXh c=1 sm=1 tr=0 ts=6a6380e7 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=j3M2sUOd0rYxyD8OH6gA:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: tByg_NTYWOvXS4yMHGtQq77HXWaiH1RS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX8aL8FfUhGK7J dXQddHGU2/0bWJKIlfwB8TbPkoyDgVWSSZruQVXBCq8OR6Gc/qhkHojJruYXHSmheSIp6RM/D3i 6GVyotdwEcRp0ChOrOJSd+8x564VYOwPUtJvJ558LnDwjbcmeK/We0nA2dJTR26aZ11MDM5r1ld iErF8ffYNkHD8M49SFcBomvT2Me4hks1Y7VyxJ1Kc3fo9xndAQCuQlCjONjsV5ow4DNtmGno94h wjkGeXjBxbqVXLx7+p73yNH39FPIEecdmXonWEi/+qbKMRXc8DnyR6it133EAI94x3Ojx8uRGwc kiSCUOx96STsbRLecSpJ4VXF69k2y1JcDiSsAhy7KFOwlDmPDsjIc86ghDd2jQaw/5cjNy1/BrY bo5xUNUschIGuapUk5gA3525Rs5y7M42/U/yPkSURpHGbhUVSV3z2CM7/M1/mo+LTuHyvpSLqOy X1rwRiGZqnobbuzu8xA== X-Proofpoint-ORIG-GUID: tByg_NTYWOvXS4yMHGtQq77HXWaiH1RS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" An upcoming compose_msi_msg() implementation reads info->domain from potentially atomic context, concurrent with domain switches. Apply RCU in preparation. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 14 ++++++++------ drivers/iommu/riscv/iommu.h | 3 ++- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index bfe606a0cb9a..27dfd60834ac 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1241,6 +1241,8 @@ static void riscv_iommu_free_paging_domain(struct iom= mu_domain *iommu_domain) =20 WARN_ON(!list_empty(&domain->bonds)); =20 + synchronize_rcu(); + riscv_iommu_ir_free_paging_domain(iommu_domain); =20 if ((int)domain->pscid > 0) @@ -1296,8 +1298,8 @@ static int riscv_iommu_attach_paging_domain(struct io= mmu_domain *iommu_domain, } =20 riscv_iommu_iodir_update(iommu, dev, fsc, ta); - riscv_iommu_bond_unlink(info->domain, dev); - info->domain =3D domain; + riscv_iommu_bond_unlink(rcu_access_pointer(info->domain), dev); + rcu_assign_pointer(info->domain, domain); =20 return 0; } @@ -1373,8 +1375,8 @@ static int riscv_iommu_attach_blocking_domain(struct = iommu_domain *iommu_domain, =20 /* Make device context invalid, translation requests will fault w/ #258 */ riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, 0); - riscv_iommu_bond_unlink(info->domain, dev); - info->domain =3D NULL; + riscv_iommu_bond_unlink(rcu_access_pointer(info->domain), dev); + rcu_assign_pointer(info->domain, NULL); =20 return 0; } @@ -1394,8 +1396,8 @@ static int riscv_iommu_attach_identity_domain(struct = iommu_domain *iommu_domain, struct riscv_iommu_info *info =3D dev_iommu_priv_get(dev); =20 riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, RISCV_IOMMU_PC= _TA_V); - riscv_iommu_bond_unlink(info->domain, dev); - info->domain =3D NULL; + riscv_iommu_bond_unlink(rcu_access_pointer(info->domain), dev); + rcu_assign_pointer(info->domain, NULL); =20 return 0; } diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 5d83537911b6..ded18aec8010 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -15,6 +15,7 @@ #include #include #include +#include #include =20 #include "iommu-bits.h" @@ -33,7 +34,7 @@ PT_IOMMU_CHECK_DOMAIN(struct riscv_iommu_domain, riscvpt.= iommu, domain); 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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1c32a76fcdsm364218566b.4.2026.07.24.08.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:39 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v2 09/14] iommu/riscv: Publish IOMMU_RESV_SW_MSI region for iommufd MSI remapping Date: Fri, 24 Jul 2026 17:12:13 +0200 Message-ID: <20260724151218.965929-10-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=GJE41ONK c=1 sm=1 tr=0 ts=6a6380e9 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=2xh-_RnL3qr1f2O9miIA:9 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfXw7u1mGaFGD0O T7WZaOE0ifi5K6UQpYfSyo8wQksbj4VB5F4NNTSWyayDjpiHYmdSOePmkOHd9e9wrcxKvFa6EUc bNP823gYgGoCnkCcyPqXKNDHbYrM9k1JAxsZSVnXNpMDgIvOFxN/nXaF3AZmC704JeeYFBNGLKI sBHpHR/HDpaly7g6F2bwFG/0rmmIN2uhr7WdWY+DjsuXEMAA5mpuMmNk2ekVti8RaF1qkVigcdF D2dwAbjGkR1CeoFS+WUdFQ+zk/LUbDmaWn4QxiW8yzKzCJ71xzT3rHTK31Ss0V1Ealo9M5+BfE5 mpqIceNPpkTY5RREOf/P0Vk/1yIiX7Uwt8dSuEV9dhkdC5mHZAIYKQN1M8YecXdPoqJTUbgSgOt c0TufrODXZ+t3pwFyAn0+//vOYUibrslfPgaBHWN3VKkTgo4V1pyjkB5HvF6IzBrRyXk+nql9BE Z/0tliMwhutf4dvpulw== X-Proofpoint-ORIG-GUID: _7_6Ycqa0ZaJjpB2HZsIMAgCZEcs-IFU X-Proofpoint-GUID: _7_6Ycqa0ZaJjpB2HZsIMAgCZEcs-IFU X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfXxTMk7g0LLpO2 H+/rd9zCq473bbfXLhmwA0LxMbRv4iPG/HLFVRlBi5FMEBKMHh6taZkkX3wo/c3WyYHv4xLVk0f cjGUjpi8YSqMqyYJkvu/juhfekr86VU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" iommufd's SW MSI path (iommufd_sw_map_msi) requires an IOMMU_RESV_SW_MSI reservation region to know the IOVA base (sw_msi_start) for MSI page mappings. Without it, sw_msi_start stays at PHYS_ADDR_MAX and iommufd_sw_map_msi silently returns passthrough. Add a get_resv_regions callback that, when IMSIC-based MSI is in use, reserves an IOVA range of num_possible_cpus() pages starting at RISCV_IOMMU_MSI_IOVA_BASE. This is large enough to hold one 4 KiB IMSIC supervisor page per hart. RISCV_IOMMU_MSI_IOVA_BASE is set to 128 MiB, matching the ARM SMMU convention. That value is arbitrary for ARM too; its introducing commit (f3ebee80b313) calls it an "arbitrary MSI IOVA window", so there is nothing riscv-specific lost by reusing it here. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 16 ++++++++++++++++ drivers/iommu/riscv/iommu.h | 3 +++ 2 files changed, 19 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 27dfd60834ac..98ce9ec50e65 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1493,6 +1493,21 @@ static void riscv_iommu_release_device(struct device= *dev) kfree_rcu_mightsleep(info); } =20 +static void riscv_iommu_get_resv_regions(struct device *dev, struct list_h= ead *head) +{ + struct iommu_resv_region *region; + + if (!imsic_enabled()) + return; + + region =3D iommu_alloc_resv_region(RISCV_IOMMU_MSI_IOVA_BASE, + (size_t)num_possible_cpus() * PAGE_SIZE, + IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO, + IOMMU_RESV_SW_MSI, GFP_KERNEL); + if (region) + list_add_tail(®ion->list, head); +} + static const struct iommu_ops riscv_iommu_ops =3D { .of_xlate =3D riscv_iommu_of_xlate, .identity_domain =3D &riscv_iommu_identity_domain, @@ -1502,6 +1517,7 @@ static const struct iommu_ops riscv_iommu_ops =3D { .device_group =3D riscv_iommu_device_group, .probe_device =3D riscv_iommu_probe_device, .release_device =3D riscv_iommu_release_device, + .get_resv_regions =3D riscv_iommu_get_resv_regions, }; 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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69fb5746e98sm92883a12.22.2026.07.24.08.12.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:41 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v2 10/14] iommu/riscv: Pre-map IMSIC MSI targets Date: Fri, 24 Jul 2026 17:12:14 +0200 Message-ID: <20260724151218.965929-11-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=GJE41ONK c=1 sm=1 tr=0 ts=6a6380ec cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=xZf72DcWP4T9vyFnQ2MA:9 a=O8hF6Hzn-FEA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX0SzJCvF/dXSv WJzSSUAaq2jKr69xr07b+ybaT/bQ6rDTxY+Ai5R20dWxOiwVytJhT+t9tiUpgdSvYzUIBmL4Pad NMh4f1LMTfqSr+u+im2M4UCuUN6wpt03YPgVVifYGqHc4xZUc3NsZJ90wUBZjmM3PaXX4J9JULZ Pff8lB/eSMcZOguUL4bawdE+Fh+xshcPi2cqdrkIiKnRKMX16gnsyE0jyZabkE//hR7fUj+280d Ol6SmI7MGz2kW7lMtCYw2SU72JtTW4o162Zt6cG+MpSHLSUgZopfQfzZl1qZV7oYKnVgfZWOEBA yEk4vc1FxxsY/bv+q1Ki2LOPRBNKG5r9s4eFQLbuOnyJJBefYnjAX/PIW/X6lA93urMN2q4wdNb +pmn5jMhzZ9XzK8PQ2N/jl+p4v/OXUadY3g9UAQnzv28lbRPtNavhIAjjUusY8WTo6gyhCcSwZc T/hVLTNEa8kPEFcMkIQ== X-Proofpoint-ORIG-GUID: W38XH8fVQ6q168AeTQDbhvR1bpLuLdII X-Proofpoint-GUID: W38XH8fVQ6q168AeTQDbhvR1bpLuLdII X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX7jpVLBMdJiN2 Qs7DMuu5+Ug6kCiS6ZTgUk4f4/kxFfv813B/2LosUa1mQHiBZrbTieswsvxvEQEWicR/ZKJRlwE RsrRB8Y5lKEldWiYpxpBzKMo6Vm/6Ew= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" Prepare for irq_compose_msi_msg() to redirect IMSIC-targeted MSIs through the IOMMU with an O(1) lookup. Unlike fixed-target MSI controllers, IMSIC target PAs change on irq_set_affinity(), which may run in atomic context, so compose cannot map the selected target on demand. Pre-map each populated IMSIC MSI target page into a domain-local IOVA table when the device's paging domain first allocates IMSIC-remapped IRQs, so every possible target IOVA is available at lookup time. The table is indexed by a transformed IMSIC physical address using the same transformation defined in the IOMMU specification for the MSI table (and the function will be used for the MSI table when that support is added later). The table is sized by riscv_iommu_ir_msi_iova_count(), i.e. BIT(group_index_bits + hart_index_bits), rather than num_possible_cpus(). This is because riscv_iommu_ir_msi_iova_idx() derives its index from hart_index_bits and group_index_bits, which are sized for the group with the most harts, i.e. there may be a sparse mapping. Select IRQ_MSI_IOMMU so iommu_dma_map_msi() and iommufd_sw_map_msi() are available to the driver. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/Kconfig | 1 + drivers/iommu/riscv/iommu-ir.c | 108 +++++++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 12 +++- drivers/iommu/riscv/iommu.h | 6 ++ 4 files changed, 124 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/riscv/Kconfig b/drivers/iommu/riscv/Kconfig index b86e5ab94183..f557b55c2c14 100644 --- a/drivers/iommu/riscv/Kconfig +++ b/drivers/iommu/riscv/Kconfig @@ -10,6 +10,7 @@ config RISCV_IOMMU select GENERIC_PT select IOMMU_PT select IOMMU_PT_RISCV64 + select IRQ_MSI_IOMMU help Support for implementations of the RISC-V IOMMU architecture that complements the RISC-V MMU capabilities, providing similar address diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 5873addf2a1b..39ca4c89a2a3 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -5,11 +5,100 @@ * Copyright (c) 2026 Qualcomm Technologies, Inc. */ #include +#include #include #include =20 #include "iommu.h" =20 +/* + * Compute the MSI index for an MSI physical address using the + * IOMMU "extract" function (RISC-V IOMMU spec section 2.3.3). + */ +static size_t riscv_iommu_ir_extract_msi_idx(phys_addr_t pa) +{ + const struct imsic_global_config *global =3D imsic_get_global_config(); + phys_addr_t mask, addr =3D pa >> 12; + size_t idx; + + mask =3D BIT(global->hart_index_bits + global->guest_index_bits) - 1; + idx =3D addr & mask; + + if (global->group_index_bits) { + phys_addr_t group_mask =3D BIT(global->group_index_bits) - 1; + phys_addr_t group_shift =3D global->group_index_shift - 12; + phys_addr_t group =3D (addr >> group_shift) & group_mask; + + idx |=3D group << fls64(mask); + } + + return idx; +} + +static size_t riscv_iommu_ir_msi_iova_idx(phys_addr_t pa) +{ + const struct imsic_global_config *global =3D imsic_get_global_config(); + + /* msi_iova[] is only used for the host imsics */ + return riscv_iommu_ir_extract_msi_idx(pa) >> global->guest_index_bits; +} + +static size_t riscv_iommu_ir_msi_iova_count(void) +{ + const struct imsic_global_config *global =3D imsic_get_global_config(); + + return BIT(global->group_index_bits + global->hart_index_bits); +} + +static int riscv_iommu_ir_build_msi_iova(struct riscv_iommu_domain *domain= , struct device *dev) +{ + const struct imsic_global_config *global =3D imsic_get_global_config(); + struct iommu_domain *d =3D &domain->domain; + dma_addr_t *msi_iova; + unsigned int cpu; + size_t idx; + int ret; + + guard(mutex)(&domain->mutex); + + if (domain->msi_iova) + return 0; + + switch (d->cookie_type) { + case IOMMU_COOKIE_DMA_IOVA: + case IOMMU_COOKIE_DMA_MSI: + case IOMMU_COOKIE_IOMMUFD: + break; + default: + return 0; + } + + msi_iova =3D kcalloc(riscv_iommu_ir_msi_iova_count(), sizeof(*msi_iova), = GFP_KERNEL); + if (!msi_iova) + return -ENOMEM; + + for_each_possible_cpu(cpu) { + const struct imsic_local_config *local =3D per_cpu_ptr(global->local, cp= u); + phys_addr_t pa =3D local->msi_pa; + unsigned int shift; + + if (!pa) + continue; + + idx =3D riscv_iommu_ir_msi_iova_idx(pa); + ret =3D iommu_dma_map_msi(d, dev, pa, IMSIC_MMIO_PAGE_SZ, &msi_iova[idx]= , &shift); + if (ret) + goto err_free; + } + + domain->msi_iova =3D msi_iova; + return 0; + +err_free: + kfree(msi_iova); + return ret; +} + static struct irq_chip riscv_iommu_ir_irq_chip =3D { .name =3D "IOMMU-IR", .irq_ack =3D irq_chip_ack_parent, @@ -22,9 +111,25 @@ static int riscv_iommu_ir_irq_domain_alloc_irqs(struct = irq_domain *irqdomain, unsigned int irq_base, unsigned int nr_irqs, void *arg) { + struct riscv_iommu_info *info =3D irqdomain->host_data; + struct riscv_iommu_domain *domain; struct irq_data *data; int i, ret; =20 + /* + * MSI IOVAs are domain-local, just like DMA IOVAs. The device must be + * quiesced, including MSI teardown, before switching away from or freeing + * the domain. iommu_dma_map_msi() requires the group mutex to be held; + * take it around the domain lookup too so info->domain can't change + * out from under the build. + */ + iommu_group_mutex_lock(info->dev); + domain =3D rcu_access_pointer(info->domain); + ret =3D domain ? riscv_iommu_ir_build_msi_iova(domain, info->dev) : 0; + iommu_group_mutex_unlock(info->dev); + if (ret) + return ret; + ret =3D irq_domain_alloc_irqs_parent(irqdomain, irq_base, nr_irqs, arg); if (ret) return ret; @@ -116,4 +221,7 @@ int riscv_iommu_ir_attach_paging_domain(struct iommu_do= main *iommu_domain, struc =20 void riscv_iommu_ir_free_paging_domain(struct iommu_domain *iommu_domain) { + struct riscv_iommu_domain *domain =3D iommu_domain_to_riscv(iommu_domain); + + kfree(domain->msi_iova); } diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 98ce9ec50e65..5631af2c9ab1 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -810,9 +810,6 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iomm= u_device *iommu, return 0; } =20 -#define iommu_domain_to_riscv(iommu_domain) \ - container_of(iommu_domain, struct riscv_iommu_domain, domain) - /* * Linkage between an iommu_domain and attached devices. * @@ -1336,6 +1333,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_= domain(struct device *dev) if (!domain) return ERR_PTR(-ENOMEM); =20 + mutex_init(&domain->mutex); + INIT_LIST_HEAD_RCU(&domain->bonds); spin_lock_init(&domain->lock); /* @@ -1449,6 +1448,13 @@ static struct iommu_device *riscv_iommu_probe_device= (struct device *dev) if (!info) return ERR_PTR(-ENOMEM); =20 + /* + * Set info->dev before creating the irqdomain: riscv_iommu_ir_irq_domain= _create() + * publishes the irqdomain via dev_set_msi_domain(), making the .alloc ca= llback + * (which dereferences info->dev) reachable. + */ + info->dev =3D dev; + if (imsic_enabled()) { irqdomain =3D riscv_iommu_ir_irq_domain_create(dev, info); if (IS_ERR(irqdomain)) { diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 9a8fd5300675..5f79e4cba375 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -31,14 +31,20 @@ struct riscv_iommu_domain { }; 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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1c32a7ad1esm362480066b.3.2026.07.24.08.12.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:43 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v2 11/14] iommu/riscv: Copy MSI IOVA table when replacing an iommufd domain Date: Fri, 24 Jul 2026 17:12:15 +0200 Message-ID: <20260724151218.965929-12-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfXyrHQR7Qv3FbI Nq3eq6SZ+pfzWGjx+Sv/XCCbo/XpnU8ZtpJv101wrOhof+2yYv+AJi+ylrAoFom/q/TLgue43jT vnh053lDjBWrVi3T19gU85a1fvEfos9Ga3rlwYEj0pnJPFWghbxU+OPPMgLIyhgrpYjuvlGNGSI z2djM/PyNagu3SGgW+OO8a+YzzoECI2x03A+YBxJaDJuPXsHkQ7XUphpjOQVsvmN0G9jfgprZGl VX5eravrwnC8n06C89JIfMvd49k7WEZrFZPPgTdvbGYuKJ488c501dEWOfJenxAUculPktDUe3k UvaaJ6WuOTs9rMVLT27JaPUomDWVk+d+0iJTB16K97QW7XqbI9yElEVF5tLUAkpN6DSnbkC7euL WvfHVuvw+iBVBNVnE1gWeSi8an1wTQi0PvpGZNF0epGRTk+Bid5X9kloKPWkzN9SbPW8u3NaCMj 8zs/yGFXNoCitsBF5GQ== X-Authority-Analysis: v=2.4 cv=RJeD2Yi+ c=1 sm=1 tr=0 ts=6a6380ee cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=6pi3hbU58VXC-MSegPwA:9 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-ORIG-GUID: qR0zpqSGUoTu_enW81vNvlJX4B0v3Ams X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX5j0HZ7kcaGiK BKFyB/aoU7dMHGVwdWJWUh2N2Ew2iWqx/2CeSXdL5UkB6vTetEDZh+Nznb7i7xsJzkKvdjySnj+ +ihgBnCob+hgAlR4DsL1c6aHccI/2R0= X-Proofpoint-GUID: qR0zpqSGUoTu_enW81vNvlJX4B0v3Ams X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 spamscore=0 phishscore=0 bulkscore=0 impostorscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" iommufd may replace one paging domain with another on a device while leaving the device otherwise operational, e.g. when converting a device's HWPT. If the old domain already had a populated MSI IOVA table then the new domain must inherit that table rather than wait to build its own, since the MSI IOVAs are only built on the next irq_domain_alloc_irqs(), which does not happen on a domain replacement. Only copy from an old domain that is a genuine RISC-V paging domain; iommu.c already has riscv_iommu_paging_domain_ops in scope to check this, so do the check there and pass NULL down on a mismatch. This keeps riscv_iommu_ir_attach_paging_domain() simple: a non-NULL old is always safe to cast with iommu_domain_to_riscv(). Only iommufd cookie domains are copied from and to, since VFIO type1 and DMA API domains build their own tables from irq_domain_alloc_irqs() before any device is attached, and are never replaced while a device is live. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 29 +++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 5 ++++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index 39ca4c89a2a3..bb1bc4c2bcec 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -216,6 +216,35 @@ void riscv_iommu_ir_irq_domain_remove(struct device *d= ev, struct riscv_iommu_inf int riscv_iommu_ir_attach_paging_domain(struct iommu_domain *iommu_domain,= struct device *dev, struct iommu_domain *old) { + struct riscv_iommu_domain *domain =3D iommu_domain_to_riscv(iommu_domain); + struct riscv_iommu_domain *old_domain =3D old ? iommu_domain_to_riscv(old= ) : NULL; + dma_addr_t *msi_iova; + + if (!old_domain) + return 0; + + if (old_domain->domain.cookie_type !=3D IOMMU_COOKIE_IOMMUFD || + iommu_domain->cookie_type !=3D IOMMU_COOKIE_IOMMUFD) + return 0; + + scoped_guard(mutex, &old_domain->mutex) { + if (!old_domain->msi_iova) + return 0; + + msi_iova =3D kmemdup(old_domain->msi_iova, + riscv_iommu_ir_msi_iova_count() * sizeof(*msi_iova), + GFP_KERNEL); + if (!msi_iova) + return -ENOMEM; + } + + guard(mutex)(&domain->mutex); + + if (domain->msi_iova) + kfree(msi_iova); + else + domain->msi_iova =3D msi_iova; + return 0; } =20 diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 5631af2c9ab1..d3b5d985887e 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1264,11 +1264,14 @@ static bool riscv_iommu_pt_supported(struct riscv_i= ommu_device *iommu, int pgd_m return false; } =20 +static const struct iommu_domain_ops riscv_iommu_paging_domain_ops; + static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_dom= ain, struct device *dev, struct iommu_domain *old) { struct riscv_iommu_domain *domain =3D iommu_domain_to_riscv(iommu_domain); + bool old_is_paging =3D old && old->ops =3D=3D &riscv_iommu_paging_domain_= ops; struct riscv_iommu_device *iommu =3D dev_to_iommu(dev); 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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1c32eb8036sm351216966b.45.2026.07.24.08.12.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:46 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v2 12/14] iommu/riscv: Implement irq_compose_msi_msg for IMSIC remapping Date: Fri, 24 Jul 2026 17:12:16 +0200 Message-ID: <20260724151218.965929-13-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: ganhw0YO8pHgPdNsA6rEGexjeAKZDaeu X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX30tnkrxUzohI vDUaJZDY0sPnPO0aMve5zdA8WjpiVQBb82D8AJv/M67oQ8255qtD5OnrqrG5RSqkWobh/HupBeZ cgk7ngxX06NLUcSu5/+Y1totYOU6nOvM2QcO8yasJlN6XXA34OfzeXu4CVRiJxE3fyIh5Hkgg5k MmgVwjQEhyb4U8ISayyKEeUWqdHQC3yzONVOyTlq02Nf3zNDQ3OMPRWInBNG25YaAljoMxBQKdm P6BFCQJoEdu/2yrT9nnA9mSEcIoR73gxVrDWqbqP3WQAHoqix55FOFVp9CVn4jphGTxQ7t+iipA juIoaLBDjQpdiV8XnzlCu0YfekGXwqiMyrilu969Qh2fdlbMLFG13SKuTsauC5l7Gj6vCgqbLhD q9dPqXsOIqJlZkWLKI0smeCCaJ1s88BMO4uJnKXzWmdqCDwvds11AAMDM/kJ8uTr006y8YBC8iL pwW99bikXKFm6y6rqJg== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX0aHx0O7VerJ/ hSKxDsGn+KzpgLwXanI6eaQLIgR/avjlCd/2AvvalI9E5V7hHQjQHDzr0hi6OUh0SwasTtFrZKB eujewh440Vwvj/6uIdkfw+A2l6BZR1k= X-Authority-Analysis: v=2.4 cv=DLW/JSNb c=1 sm=1 tr=0 ts=6a6380f0 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=wDfzXBFmrApTGnkBQMcA:9 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-ORIG-GUID: ganhw0YO8pHgPdNsA6rEGexjeAKZDaeu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" Wire up irq_compose_msi_msg() on the IOMMU-IR irq chip to look up the pre-mapped IOVA for the target IMSIC page and rewrite the composed message to use it, redirecting MSI writes through the IOMMU instead of landing at the raw IMSIC physical address. The lookup is O(1), since the "extract" function used to build the table's index is also used here, which is necessary since the number of IMSICs may eventually be in the hundreds and irq_compose_msi_msg() may run in atomic context. domain->msi_iova is read here without domain->mutex, since compose can run in atomic context, and RCU only protects info->domain itself. Pair smp_store_release()/smp_load_acquire() on domain->msi_iova to ensure it's observably filled before publishing its pointer. That guarantees a non-NULL domain->msi_iova observed here is safe to use. The WARN_ON_ONCE(!msi_iova) is defensive: a live paging domain should not reach compose without a populated table. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 50 +++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index bb1bc4c2bcec..eb2b7953055e 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -91,7 +91,9 @@ static int riscv_iommu_ir_build_msi_iova(struct riscv_iom= mu_domain *domain, stru goto err_free; } =20 - domain->msi_iova =3D msi_iova; + /* Pair with the smp_load_acquire() in riscv_iommu_ir_compose_msi_msg() */ + smp_store_release(&domain->msi_iova, msi_iova); + return 0; =20 err_free: @@ -99,12 +101,50 @@ static int riscv_iommu_ir_build_msi_iova(struct riscv_= iommu_domain *domain, stru return ret; } =20 +static void riscv_iommu_ir_compose_msi_msg(struct irq_data *data, struct m= si_msg *msg) +{ + struct riscv_iommu_info *info =3D data->domain->host_data; + struct riscv_iommu_domain *domain; + dma_addr_t *msi_iova; + struct msi_desc *desc; + phys_addr_t pa; + size_t idx; + + BUG_ON(irq_chip_compose_msi_msg(data->parent_data, msg)); + + desc =3D irq_data_get_msi_desc(data); + if (WARN_ON_ONCE(!desc)) + return; + + guard(rcu)(); + + domain =3D rcu_dereference(info->domain); + if (!domain) { + msi_desc_set_iommu_msi_iova(desc, 0, 0); + return; + } + + /* Pair with the smp_store_release() in riscv_iommu_ir_build_msi_iova() */ + msi_iova =3D smp_load_acquire(&domain->msi_iova); + if (WARN_ON_ONCE(!msi_iova)) { + msi_desc_set_iommu_msi_iova(desc, 0, 0); + return; + } + + pa =3D ((u64)msg->address_hi << 32) | msg->address_lo; + idx =3D riscv_iommu_ir_msi_iova_idx(pa); + + msi_desc_set_iommu_msi_iova(desc, msi_iova[idx], IMSIC_MMIO_PAGE_SHIFT); + msi_msg_set_addr(desc, msg, pa); +} + static struct irq_chip riscv_iommu_ir_irq_chip =3D { .name =3D "IOMMU-IR", .irq_ack =3D irq_chip_ack_parent, .irq_mask =3D irq_chip_mask_parent, .irq_unmask =3D irq_chip_unmask_parent, .irq_set_affinity =3D irq_chip_set_affinity_parent, + .irq_compose_msi_msg =3D riscv_iommu_ir_compose_msi_msg, }; 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[86.49.247.5]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1c4ec7849fsm230083466b.5.2026.07.24.08.12.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:12:50 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev, tjeznach@rivosinc.com, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com, fangyu.yu@linux.alibaba.com Subject: [PATCH v2 14/14] riscv: defconfig: Enable IOMMUFD and VFIO Date: Fri, 24 Jul 2026 17:12:18 +0200 Message-ID: <20260724151218.965929-15-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> References: <20260724151218.965929-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 0VBWq39UK8Yf5y5jTEIA1UaMieOC2JmE X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfXxr1bp+r+hnkZ qdc4qDQTakXiDzDRXC81LB9fvoESdVODUDsmjQk08iTfm9wh6gj/qKx1RVSjrqgTUOKZNaaYMqR 4ZUrW3HneXIPNvYMVlm/hpOwfHFz4U8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNyBTYWx0ZWRfX6ptGFoMTle2u oPUEKiWMxT5MhEC15FG7pi5A7SsuHMD/+Ml5IapLYaOv9as4w95OLJ7WYIpdZk+P9yAxK+BBK6L IlNI6ID+xGwTJuw534Ou2iHjLjuT5J6iC/P/qbrU+CyZJomX+8NFaYp+oTtj9WKLFTTkLQ8FGDB RQkr7tS9KKZVfsJY+yRU9ZaOxUxPmWgNkGqyyX00V2CZd4Zl9iD210EYSJ/obupi/Q18UOeT4dn 7Rb0NChYn6B0L9Cb9Wn1aOhRbWPff0nJ8UTlGZj0plcwFooBR/lHgf1wRTwZ4khAYc0TBZO3EX4 bsk/CQtDyQFinh7jhNnCFU+IoLcG57KTarBsVUsGj3QNxfCiBioo3+yiGibB+uaRgcUvZN0hv+c 3RMCzEZ5ASGjXJGFjpHqAoUYj4WFYSvHF+CvDpHjgSe2BJlxdLBunIJN2w+QGo621EIC8R92KyN 6iC4h4W78ifjlRHpn2g== X-Proofpoint-GUID: 0VBWq39UK8Yf5y5jTEIA1UaMieOC2JmE X-Authority-Analysis: v=2.4 cv=GMA41ONK c=1 sm=1 tr=0 ts=6a6380f5 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=aYZ+cQcEYoLAp2L633VOig==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=GqzxFy3tBpXcAUtZkFUA:9 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240137 Content-Type: text/plain; charset="utf-8" Now that the RISC-V IOMMU driver supports MSI remapping through iommufd enable IOMMUFD and VFIO. Signed-off-by: Andrew Jones --- arch/riscv/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ed605b5e3162..fb3cea5712b2 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -249,6 +249,9 @@ CONFIG_DMADEVICES=3Dy CONFIG_DMA_SUN6I=3Dm CONFIG_DW_AXI_DMAC=3Dy CONFIG_MMP_PDMA=3Dm +CONFIG_IOMMUFD=3Dy +CONFIG_VFIO=3Dy +CONFIG_VFIO_PCI=3Dy CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO_BALLOON=3Dy CONFIG_VIRTIO_INPUT=3Dy --=20 2.43.0