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charset="utf-8" Add a new clock ID, LPASS_HW_LPR_VOTE, to represent the LPASS low-power resource (LPR) vote through the PRM interface. The LPASS PRM supports a resource voting mechanism to control low-power states via PARAM_ID_RSC_CPU_LPR. Exposing this as a q6prm clock ID allows clients to request the LPR vote using the existing qcom,q6prm clock provider interface. This functionality is required on newer platforms (e.g. Hawi) where LPASS clients need to explicitly manage LPR resource voting via PRM. Acked-by: Krzysztof Kozlowski Signed-off-by: Prasad Kumpatla --- include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/d= t-bindings/sound/qcom,q6dsp-lpass-ports.h index 7b553a73bc92..8e04106d48be 100644 --- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -236,6 +236,7 @@ #define LPASS_HW_AVTIMER_VOTE 101 #define LPASS_HW_MACRO_VOTE 102 #define LPASS_HW_DCODEC_VOTE 103 +#define LPASS_HW_LPR_VOTE 104 =20 #define LPASS_CLK_ATTRIBUTE_INVALID 0x0 #define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 --=20 2.34.1 From nobody Fri Jul 24 21:29:57 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B8AE43A7FC; Fri, 24 Jul 2026 14:17:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Q6DSP_MAX_CLK_ID defines the upper bound of supported clock identifiers in the qdsp6 LPASS clock driver. Increase the maximum clock ID value to accommodate the LPASS LPR vote clock identifier. Signed-off-by: Prasad Kumpatla --- sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c b/sound/soc/qcom/qds= p6/q6dsp-lpass-clocks.c index 03838582aead..ab7d20580638 100644 --- a/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c @@ -12,7 +12,7 @@ #include #include "q6dsp-lpass-clocks.h" =20 -#define Q6DSP_MAX_CLK_ID 104 +#define Q6DSP_MAX_CLK_ID 105 #define Q6DSP_LPASS_CLK_ROOT_DEFAULT 0 =20 =20 --=20 2.34.1 From nobody Fri Jul 24 21:29:57 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B7BB423E9C; Fri, 24 Jul 2026 14:17:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Add support for issuing LPASS low-power resource (LPR) votes through the PRM interface. Some platforms (e.g. Hawi) require the LPASS to be kept active via LPR resource voting instead of the existing hardware core vote mechanism. Handle this by introducing support for PARAM_ID_RSC_CPU_LPR when the LPR vote clock ID is requested. For LPR requests, use the appropriate parameter ID and payload format to disable CPU subsystem sleep, ensuring that the LPASS register space remains accessible. Also add the corresponding clock mapping for LPASS_HW_LPR_VOTE. Reviewed-by: Srinivas Kandagatla Signed-off-by: Prasad Kumpatla --- sound/soc/qcom/qdsp6/q6prm-clocks.c | 2 ++ sound/soc/qcom/qdsp6/q6prm.c | 16 +++++++++++++--- sound/soc/qcom/qdsp6/q6prm.h | 1 + 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/sound/soc/qcom/qdsp6/q6prm-clocks.c b/sound/soc/qcom/qdsp6/q6p= rm-clocks.c index 4c574b48ab00..2b2b3872ed1c 100644 --- a/sound/soc/qcom/qdsp6/q6prm-clocks.c +++ b/sound/soc/qcom/qdsp6/q6prm-clocks.c @@ -63,6 +63,8 @@ static const struct q6dsp_clk_init q6prm_clks[] =3D { "LPASS_HW_MACRO"), Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC, "LPASS_HW_DCODEC"), + Q6DSP_VOTE_CLK(LPASS_HW_LPR_VOTE, Q6PRM_HW_LPR_VOTE, + "LPASS_HW_LPR_VOTE"), }; =20 static const struct q6dsp_clk_desc q6dsp_clk_q6prm __maybe_unused =3D { diff --git a/sound/soc/qcom/qdsp6/q6prm.c b/sound/soc/qcom/qdsp6/q6prm.c index 04892fb4423f..1f3ce4cc0837 100644 --- a/sound/soc/qcom/qdsp6/q6prm.c +++ b/sound/soc/qcom/qdsp6/q6prm.c @@ -31,10 +31,16 @@ struct q6prm { #define PARAM_ID_RSC_HW_CORE 0x08001032 #define PARAM_ID_RSC_LPASS_CORE 0x0800102B #define PARAM_ID_RSC_AUDIO_HW_CLK 0x0800102C +#define PARAM_ID_RSC_CPU_LPR 0x08001A6E + +#define LPR_CPU_SS_SLEEP_DISABLE 0x1 =20 struct prm_cmd_request_hw_core { struct apm_module_param_data param_data; - uint32_t hw_clk_id; + union { + u32 hw_clk_id; + u32 lpr_state; + }; } __packed; =20 struct prm_cmd_request_rsc { @@ -62,6 +68,7 @@ static int q6prm_set_hw_core_req(struct device *dev, uint= 32_t hw_block_id, bool struct prm_cmd_request_hw_core *req; gpr_device_t *gdev =3D prm->gdev; uint32_t opcode, rsp_opcode; + bool lpr_req =3D (hw_block_id =3D=3D Q6PRM_HW_LPR_VOTE); =20 if (enable) { opcode =3D PRM_CMD_REQUEST_HW_RSC; @@ -82,10 +89,13 @@ static int q6prm_set_hw_core_req(struct device *dev, ui= nt32_t hw_block_id, bool =20 param_data->module_instance_id =3D GPR_PRM_MODULE_IID; param_data->error_code =3D 0; - param_data->param_id =3D PARAM_ID_RSC_HW_CORE; + param_data->param_id =3D lpr_req ? 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charset="utf-8" Add bindings for the pin controller in Low Power Audio SubSystem (LPASS) of Qualcomm Hawi SoC. The controller has 23 GPIOs (gpio0-gpio22) with functions including SoundWire, I2S, DMIC, VA I2S, ext_mclk1, slimbus and lpass_lpi_dbg_clk. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Prasad Kumpatla --- .../pinctrl/qcom,hawi-lpass-lpi-pinctrl.yaml | 109 ++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpa= ss-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpass-lpi-= pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpass-lp= i-pinctrl.yaml new file mode 100644 index 000000000000..af68581750cf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpass-lpi-pinctrl= .yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-lpass-lpi-pinctrl.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hawi SoC LPASS LPI TLMM + +maintainers: + - Krzysztof Kozlowski + - Srinivas Kandagatla + - Prasad Kumpatla + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSyst= em + (LPASS) Low Power Island (LPI) of Qualcomm Hawi SoC. + +properties: + compatible: + const: qcom,hawi-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + + clocks: + items: + - description: LPASS LPR(Low Power Resource) voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: lpr + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-hawi-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-hawi-lpass-state" + additionalProperties: false + +$defs: + qcom-hawi-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b, + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, + lpass_lpi_dbg_clk, qca_swr_clk, qca_swr_data, slimbus_clk, + slimbus_data, swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_c= lk1, + swr_tx_data, va_i2s0_clk, va_i2s0_data, va_i2s0_ws, + wsa2_swr_clk, wsa2_swr_data, wsa_swr_clk, wsa_swr_data] + description: + Specify the alternative function to be configured for the specif= ied + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + lpass_tlmm: pinctrl@7f60000 { + compatible =3D "qcom,hawi-lpass-lpi-pinctrl"; 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charset="utf-8" Add pin controller driver for the Low Power Audio SubSystem (LPASS) Low Power Island (LPI) of Qualcomm Hawi SoC. The controller has 23 GPIOs with SoundWire, I2S, DMIC, VA I2S, ext_mclk1 and slimbus mux functions. Two pins (gpio13, gpio22) require 6 mux slots due to a test_bus entry occupying a middle hardware slot. Add LPI_PINGROUP6 macro to pinctrl-lpass-lpi.h to support pins with 5 alternate functions. Reviewed-by: Konrad Dybcio Signed-off-by: Prasad Kumpatla --- drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c | 244 ++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 17 ++ 4 files changed, 272 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 18db350222b9..707067b9251f 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -62,6 +62,16 @@ config PINCTRL_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SoCs. =20 +config PINCTRL_HAWI_LPASS_LPI + tristate "Qualcomm Technologies Inc Hawi LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc Hawi + platform. + config PINCTRL_MILOS_LPASS_LPI tristate "Qualcomm Milos LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 43ecd246afe8..987a79f9d4c4 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_APQ8084) +=3D pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_ELIZA) +=3D pinctrl-eliza.o obj-$(CONFIG_PINCTRL_GLYMUR) +=3D pinctrl-glymur.o obj-$(CONFIG_PINCTRL_HAWI) +=3D pinctrl-hawi.o +obj-$(CONFIG_PINCTRL_HAWI_LPASS_LPI) +=3D pinctrl-hawi-lpass-lpi.o obj-$(CONFIG_PINCTRL_IPQ4019) +=3D pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) +=3D pinctrl-ipq5018.o obj-$(CONFIG_PINCTRL_IPQ8064) +=3D pinctrl-ipq8064.o diff --git a/drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c b/drivers/pinctr= l/qcom/pinctrl-hawi-lpass-lpi.c new file mode 100644 index 000000000000..7036bf4c6692 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_dmic4_clk, + LPI_MUX_dmic4_data, + LPI_MUX_ext_mclk1_a, + LPI_MUX_ext_mclk1_b, + LPI_MUX_ext_mclk1_c, + LPI_MUX_ext_mclk1_d, + LPI_MUX_ext_mclk1_e, + LPI_MUX_i2s0_clk, + LPI_MUX_i2s0_data, + LPI_MUX_i2s0_ws, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_lpass_lpi_dbg_clk, + LPI_MUX_qca_swr_clk, + LPI_MUX_qca_swr_data, + LPI_MUX_slimbus_clk, + LPI_MUX_slimbus_data, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_clk1, + LPI_MUX_swr_tx_data, + LPI_MUX_va_i2s0_clk, + LPI_MUX_va_i2s0_data, + LPI_MUX_va_i2s0_ws, + LPI_MUX_wsa2_swr_clk, + LPI_MUX_wsa2_swr_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc hawi_lpi_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), +}; + +static const char * const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", +}; + +static const char * const swr_tx_clk_groups[] =3D { "gpio0" }; +static const char * const i2s0_clk_groups[] =3D { "gpio0" }; +static const char * const swr_tx_data_groups[] =3D { "gpio1", "gpio2", "gp= io14" }; +static const char * const i2s0_ws_groups[] =3D { "gpio1" }; +static const char * const swr_rx_clk_groups[] =3D { "gpio3" }; +static const char * const i2s0_data_groups[] =3D { "gpio2", "gpio3", "gpio= 4", "gpio5" }; +static const char * const swr_rx_data_groups[] =3D { "gpio4", "gpio5" }; +static const char * const ext_mclk1_c_groups[] =3D { "gpio5" }; +static const char * const dmic1_clk_groups[] =3D { "gpio6" }; +static const char * const va_i2s0_clk_groups[] =3D { "gpio6" }; +static const char * const dmic1_data_groups[] =3D { "gpio7" }; +static const char * const va_i2s0_ws_groups[] =3D { "gpio7" }; +static const char * const dmic2_clk_groups[] =3D { "gpio8" }; +static const char * const va_i2s0_data_groups[] =3D { "gpio8", "gpio9" }; +static const char * const dmic2_data_groups[] =3D { "gpio9" }; +static const char * const ext_mclk1_b_groups[] =3D { "gpio9" }; +static const char * const i2s1_clk_groups[] =3D { "gpio10" }; +static const char * const wsa_swr_clk_groups[] =3D { "gpio10" }; +static const char * const i2s1_ws_groups[] =3D { "gpio11" }; +static const char * const wsa_swr_data_groups[] =3D { "gpio11", "gpio21" }; +static const char * const dmic3_clk_groups[] =3D { "gpio12" }; +static const char * const i2s3_clk_groups[] =3D { "gpio12" }; +static const char * const dmic3_data_groups[] =3D { "gpio13" }; +static const char * const i2s3_ws_groups[] =3D { "gpio13" }; +static const char * const ext_mclk1_a_groups[] =3D { "gpio13" }; +static const char * const lpass_lpi_dbg_clk_groups[] =3D { "gpio13" }; +static const char * const swr_tx_clk1_groups[] =3D { "gpio14" }; +static const char * const ext_mclk1_d_groups[] =3D { "gpio14" }; +static const char * const i2s1_data_groups[] =3D { "gpio15", "gpio16", "gp= io21", "gpio22" }; +static const char * const wsa2_swr_clk_groups[] =3D { "gpio15" }; +static const char * const wsa2_swr_data_groups[] =3D { "gpio16", "gpio22" = }; +static const char * const dmic4_clk_groups[] =3D { "gpio17" }; +static const char * const i2s3_data_groups[] =3D { "gpio17", "gpio18" }; +static const char * const dmic4_data_groups[] =3D { "gpio18" }; +static const char * const i2s2_clk_groups[] =3D { "gpio19" }; +static const char * const slimbus_clk_groups[] =3D { "gpio19" }; +static const char * const qca_swr_clk_groups[] =3D { "gpio19" }; +static const char * const i2s2_ws_groups[] =3D { "gpio20" }; +static const char * const slimbus_data_groups[] =3D { "gpio20" }; +static const char * const qca_swr_data_groups[] =3D { "gpio20" }; +static const char * const i2s2_data_groups[] =3D { "gpio21", "gpio22" }; +static const char * const ext_mclk1_e_groups[] =3D { "gpio22" }; + +static const struct lpi_pingroup hawi_groups[] =3D { + LPI_PINGROUP(0, 11, swr_tx_clk, i2s0_clk, _, _), + LPI_PINGROUP(1, 11, swr_tx_data, i2s0_ws, _, _), + LPI_PINGROUP(2, 11, swr_tx_data, i2s0_data, _, _), + LPI_PINGROUP(3, 11, swr_rx_clk, i2s0_data, _, _), + LPI_PINGROUP(4, 11, swr_rx_data, i2s0_data, _, _), + LPI_PINGROUP(5, 11, swr_rx_data, ext_mclk1_c, i2s0_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, va_i2s0_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, va_i2s0_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, va_i2s0_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, va_i2s0_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 11, i2s1_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 11, i2s1_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s3_clk, _, _), + LPI_PINGROUP6(13, LPI_NO_SLEW, dmic3_data, i2s3_ws, ext_mclk1_a, _, lpass= _lpi_dbg_clk), + LPI_PINGROUP(14, 11, swr_tx_data, swr_tx_clk1, ext_mclk1_d, _), + LPI_PINGROUP(15, 11, i2s1_data, wsa2_swr_clk, _, _), + LPI_PINGROUP(16, 11, i2s1_data, wsa2_swr_data, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s3_data, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s3_data, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, i2s2_clk, slimbus_clk, qca_swr_clk, _), + LPI_PINGROUP(20, LPI_NO_SLEW, i2s2_ws, slimbus_data, qca_swr_data, _), + LPI_PINGROUP(21, 11, i2s2_data, _, wsa_swr_data, i2s1_data), + LPI_PINGROUP6(22, 11, i2s2_data, ext_mclk1_e, _, i2s1_data, wsa2_swr_data= ), +}; + +static const struct lpi_function hawi_functions[] =3D { + LPI_FUNCTION(gpio), + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(dmic4_clk), + LPI_FUNCTION(dmic4_data), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_b), + LPI_FUNCTION(ext_mclk1_c), + LPI_FUNCTION(ext_mclk1_d), + LPI_FUNCTION(ext_mclk1_e), + LPI_FUNCTION(i2s0_clk), + LPI_FUNCTION(i2s0_data), + LPI_FUNCTION(i2s0_ws), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(lpass_lpi_dbg_clk), + LPI_FUNCTION(qca_swr_clk), + LPI_FUNCTION(qca_swr_data), + LPI_FUNCTION(slimbus_clk), + LPI_FUNCTION(slimbus_data), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_clk1), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(va_i2s0_clk), + LPI_FUNCTION(va_i2s0_data), + LPI_FUNCTION(va_i2s0_ws), + LPI_FUNCTION(wsa2_swr_clk), + LPI_FUNCTION(wsa2_swr_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data hawi_lpi_data =3D { + .pins =3D hawi_lpi_pins, + .npins =3D ARRAY_SIZE(hawi_lpi_pins), + .groups =3D hawi_groups, + .ngroups =3D ARRAY_SIZE(hawi_groups), + .functions =3D hawi_functions, + .nfunctions =3D ARRAY_SIZE(hawi_functions), + .flags =3D LPI_FLAG_SLEW_RATE_SAME_REG, +}; + +static const struct of_device_id lpi_pinctrl_of_match[] =3D { + { + .compatible =3D "qcom,hawi-lpass-lpi-pinctrl", + .data =3D &hawi_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static struct platform_driver lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-hawi-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), + }, + .probe =3D lpi_pinctrl_probe, + .remove =3D lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("Qualcomm Hawi LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.h index 6ba0c4eba984..056c4a774389 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -92,6 +92,23 @@ struct pinctrl_pin_desc; .pin_offset =3D 0, \ } =20 +#define LPI_PINGROUP6(id, soff, f1, f2, f3, f4, f5) \ + { \ + .pin =3D id, \ + .slew_offset =3D soff, \ + .slew_base_spare_1 =3D false, \ + .funcs =3D (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + LPI_MUX_##f5, \ + }, \ + .nfuncs =3D 6, \ + .pin_offset =3D 0, \ + } + /* * Slew rate control is done in the same register as rest of the * pin configuration. --=20 2.34.1