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bh=5vaO/GM91G3rNsV69zS2AeHYbUZzZm3t2t1r+BkuECs=; b=iInyA7bi4kZSnS6rEumt7ravpL FZaKQB5TWF+3Xtil21ZpRPm1ZrKVlYNynjC8SDdILactGS6Xmx0gjpmBR6FAZ/yHRHWlZ+WzISwgt zEKAEL4YoyHQ+8zuAhFen3nCy1p+/3CYiNmCdw0JitE6dVHAxGQa5bBtBitEf11Ja/A7QIzSSzT0n sIuwyMe2o7xyooVO3fCVxhXdLknLvI3r9CCW/fewyYg1/DG5tVEnZHdTS3FemqrmXZ4klOScFpRhw 3FwxLqulFjMhr8wazTh1z4ARESJi/EYfeTCYL8eB7Vruz8zujFYcZPe+xsBZwLgDGXmei7k933Mhu g0FYDM3g==; Received: from [193.77.36.193] (port=41890 helo=rok-trip.kanardia.eu) by th8.neoserv.si with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.99.4) (envelope-from ) id 1wnAxL-0000000AcoX-0Be1; Fri, 24 Jul 2026 10:08:31 +0200 From: Rok Markovic To: Heiko Stuebner , Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alibek Omarov , Rok Markovic Subject: [PATCH v2 1/4] drm/rockchip: lvds: propagate bus_flags to the CRTC state Date: Fri, 24 Jul 2026 10:08:21 +0200 Message-ID: <20260724080824.115260-2-rok@kanardia.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724080824.115260-1-rok@kanardia.eu> References: <20260724080824.115260-1-rok@kanardia.eu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Authentication-Results: th8.neoserv.si; auth=pass (PLAIN) smtp.auth=rok@kanardia.eu X-NEOSERV-MailScanner-Information: Please contact the ISP for more information X-NEOSERV-MailScanner-ID: 1wnAxL-0000000AcoX-0Be1 X-NEOSERV-MailScanner: Found to be clean X-NEOSERV-MailScanner-SpamCheck: not spam, SpamAssassin (not cached, score=1.31, required 7, ALL_TRUSTED -1.00, BAYES_50 0.80, KAM_DMARC_QUARANTINE 1.50, KAM_DMARC_STATUS 0.01) X-NEOSERV-MailScanner-SpamScore: s X-NEOSERV-MailScanner-From: rok@kanardia.eu X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - th8.neoserv.si X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - kanardia.eu X-Get-Message-Sender-Via: th8.neoserv.si: authenticated_id: rok@kanardia.eu X-Authenticated-Sender: th8.neoserv.si: rok@kanardia.eu Content-Type: text/plain; charset="utf-8" rockchip_lvds_encoder_atomic_check() sets output_mode and output_type but never copies the connector's bus_flags into the Rockchip CRTC state, unlike dw_dp-rockchip.c and dw-mipi-dsi2-rockchip.c which both do. panel-lvds parses pixelclk-active from the DT display timing and publishes it on the connector as DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE. VOP2 reads that flag back out of the CRTC state to decide POLFLAG_DCLK_INV. With the flag dropped here, vcstate->bus_flags is always zero, so a panel that asks to be clocked on the falling edge is driven on the rising one, and there is no way to express the panel's requirement from DT at all. No functional change for the SoCs currently supported by this driver: rk3288 and px30 pair with the VOP1 driver (rockchip_drm_vop.c), which never reads bus_flags - only VOP2 consumes it. The flag becomes live with the RK3568 support added later in this series. Signed-off-by: Rok Markovic Assisted-by: Claude:claude-opus-4-8 --- No changes since v1. drivers/gpu/drm/rockchip/rockchip_lvds.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/roc= kchip/rockchip_lvds.c index 75f898a..95fa0a9 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -129,7 +129,15 @@ rockchip_lvds_encoder_atomic_check(struct drm_encoder = *encoder, struct drm_connector_state *conn_state) { struct rockchip_crtc_state *s =3D to_rockchip_crtc_state(crtc_state); - + struct drm_connector *connector =3D conn_state->connector; + + /* + * The VOP derives the pixel clock polarity from this. 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Fri, 24 Jul 2026 10:08:31 +0200 From: Rok Markovic To: Heiko Stuebner , Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alibek Omarov , Rok Markovic Subject: [PATCH v2 2/4] dt-bindings: display: rockchip,lvds: add RK3568 Date: Fri, 24 Jul 2026 10:08:22 +0200 Message-ID: <20260724080824.115260-3-rok@kanardia.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724080824.115260-1-rok@kanardia.eu> References: <20260724080824.115260-1-rok@kanardia.eu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Authentication-Results: th8.neoserv.si; auth=pass (PLAIN) smtp.auth=rok@kanardia.eu X-NEOSERV-MailScanner-Information: Please contact the ISP for more information X-NEOSERV-MailScanner-ID: 1wnAxL-0000000AcoX-0PoU X-NEOSERV-MailScanner: Found to be clean X-NEOSERV-MailScanner-SpamCheck: not spam, SpamAssassin (not cached, score=1.31, required 7, ALL_TRUSTED -1.00, BAYES_50 0.80, KAM_DMARC_QUARANTINE 1.50, KAM_DMARC_STATUS 0.01) X-NEOSERV-MailScanner-SpamScore: s X-NEOSERV-MailScanner-From: rok@kanardia.eu X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - th8.neoserv.si X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - kanardia.eu X-Get-Message-Sender-Via: th8.neoserv.si: authenticated_id: rok@kanardia.eu X-Authenticated-Sender: th8.neoserv.si: rok@kanardia.eu Content-Type: text/plain; charset="utf-8" The RK3568 LVDS transmitter has no register block of its own: it is programmed entirely through the GRF and re-uses the MIPI DSI0 D-PHY (rockchip,rk3568-dsi-dphy) in LVDS mode. It therefore takes the same shape as px30: phys/phy-names, no reg, and no clock of its own. Since the block exposes no MMIO, nothing in the LVDS path is clocked from the DSI controller's APB clock; that gate is held off while LVDS scans out. It has no analog supplies of its own and no pinctrl either: the lanes are dedicated D-PHY pins, not muxable GPIOs. Signed-off-by: Rok Markovic Assisted-by: Claude:claude-opus-4-8 --- Changes in v2: - RK3568 now takes no clock (clocks/clock-names disabled, as for px30): the block has no register space, so nothing consumes the DSI controller's APB clock. .../display/rockchip/rockchip,lvds.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,lv= ds.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.= yaml index 03b002a..b77d4fa 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml @@ -15,6 +15,7 @@ properties: enum: - rockchip,px30-lvds - rockchip,rk3288-lvds + - rockchip,rk3568-lvds =20 reg: maxItems: 1 @@ -121,6 +122,27 @@ allOf: - avdd1v8-supply - avdd3v3-supply =20 + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-lvds + + then: + properties: + reg: false + clocks: false + clock-names: false + avdd1v0-supply: false + avdd1v8-supply: false + avdd3v3-supply: false + pinctrl-names: false + pinctrl-0: false + + required: + - phys + - phy-names + additionalProperties: false =20 examples: --=20 2.43.0 From nobody Fri Jul 24 21:53:37 2026 Received: from th8-b.mail-neoserv.si (th8-b.mail-neoserv.si [152.89.234.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53AB13C1092; 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Received: from [193.77.36.193] (port=41890 helo=rok-trip.kanardia.eu) by th8.neoserv.si with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.99.4) (envelope-from ) id 1wnAxL-0000000AcoX-0f6c; Fri, 24 Jul 2026 10:08:31 +0200 From: Rok Markovic To: Heiko Stuebner , Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alibek Omarov , Rok Markovic Subject: [PATCH v2 3/4] drm/rockchip: lvds: add RK3568 support Date: Fri, 24 Jul 2026 10:08:23 +0200 Message-ID: <20260724080824.115260-4-rok@kanardia.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724080824.115260-1-rok@kanardia.eu> References: <20260724080824.115260-1-rok@kanardia.eu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Authentication-Results: th8.neoserv.si; auth=pass (PLAIN) smtp.auth=rok@kanardia.eu X-NEOSERV-MailScanner-Information: Please contact the ISP for more information X-NEOSERV-MailScanner-ID: 1wnAxL-0000000AcoX-0f6c X-NEOSERV-MailScanner: Found to be clean X-NEOSERV-MailScanner-SpamCheck: not spam, SpamAssassin (not cached, score=1.31, required 7, ALL_TRUSTED -1.00, BAYES_50 0.80, KAM_DMARC_QUARANTINE 1.50, KAM_DMARC_STATUS 0.01) X-NEOSERV-MailScanner-SpamScore: s X-NEOSERV-MailScanner-From: rok@kanardia.eu X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - th8.neoserv.si X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - kanardia.eu X-Get-Message-Sender-Via: th8.neoserv.si: authenticated_id: rok@kanardia.eu X-Authenticated-Sender: th8.neoserv.si: rok@kanardia.eu Content-Type: text/plain; charset="utf-8" The RK3568 LVDS transmitter has no register block of its own. It is driven entirely through the GRF and re-uses the MIPI DSI0 D-PHY in PHY_MODE_LVDS, which phy-rockchip-inno-dsidphy already supports. Based on Alibek Omarov's earlier posting [1], with the changes below. Power the D-PHY from the encoder enable path rather than from probe. phy_power_on() runs the phy driver's whole LVDS bring-up: PLL and bandgap power-on, a settle, PLL mode select, then a reset pulse of the serializer and the lane enables. None of that is safe at probe time - the GRF has not yet switched the block to LVDS mode (LVDS0_MODE_EN is set from rk3568_lvds_poweron(), i.e. the enable path) and the VOP is not driving dclk. The serializer is clocked from dclk and latches its state coming out of that reset, so it comes up dead and stays dead. The failure is silent: every register in the phy, the GRF and the VOP reads back exactly as on a working system while the lanes sit at common mode and never toggle. Program RK3568_LVDS0_DCLK_INV_SEL from the CRTC state's bus_flags so the panel's declared pixelclk-active is honoured on the LVDS block as well as on the VOP pin polarity. Both have to agree with the edge the panel samples on. Re-assert RK3568_LVDS0_P2S_EN in rk3568_lvds_poweron(). rk3568_lvds_poweroff() clears MODE_EN and P2S_EN together, so setting P2S_EN once at probe would leave the parallel-to-serial converter off after the first disable/enable cycle. Use regmap_write() rather than regmap_update_bits() for the GRF. These registers are write-masked - the upper 16 bits select which of the lower 16 a write may change - so there is nothing to preserve and no reason to read first. Passing a FIELD_PREP_WM16() value as both the mask and the value of an update_bits() applies the masking twice and only works by accident. Take no clock. The block exposes no MMIO of its own, so there is nothing for the DSI controller's APB clock to reach; the vendor BSP scans out LVDS with PCLK_DSITX_0's gate off, and so does this driver. Between the above, nothing needs programming at probe at all: the GRF is written entirely from the enable path, so px30_lvds_probe() is left alone rather than being refactored into a shared phy helper. Track the enabled state so that a .enable() that bails out unwinds itself and the .disable() that the atomic helpers still call afterwards becomes a no-op, rather than underflowing the phy power count and the runtime-PM count of an encoder that never came up. [1] https://lore.kernel.org/all/20230119184807.171132-1-a1ba.omarov@gmail.c= om/ Co-developed-by: Alibek Omarov Signed-off-by: Alibek Omarov Signed-off-by: Rok Markovic Assisted-by: Claude:claude-opus-4-8 --- Changes in v2: - Drop the clock. rk3568_lvds_poweron() no longer enables a pclk; the block has no MMIO for the DSI APB clock to reach, and the vendor BSP scans out with PCLK_DSITX_0 gated off. - Merge rk3568_lvds_grf_config() into rk3568_lvds_poweron(): a single masked write to VO_CON2 instead of two, and check the output type before resuming runtime PM. - Balance the enable/disable teardown so a .enable() that fails partway does not underflow the phy power and runtime-PM counts when the atomic helpers then call .disable(). - Use pm_runtime_resume_and_get(), matching the rk3288/px30 paths. - Drop the in-code comments restating phy_set_mode() internals and the write-masked GRF convention; the ordering rationale is in the commit message. drivers/gpu/drm/rockchip/rockchip_lvds.c | 124 +++++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_lvds.h | 10 ++ 2 files changed, 134 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/roc= kchip/rockchip_lvds.c index 95fa0a9..9af21fc 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -51,6 +51,7 @@ struct rockchip_lvds { struct regmap *grf; struct clk *pclk; struct phy *dphy; + bool enabled; const struct rockchip_lvds_soc_data *soc_data; int output; /* rgb lvds or dual lvds output */ int format; /* vesa or jeida format */ @@ -435,6 +436,100 @@ static void px30_lvds_encoder_disable(struct drm_enco= der *encoder) drm_panel_unprepare(lvds->panel); } =20 +static int rk3568_lvds_poweron(struct drm_encoder *encoder) +{ + struct rockchip_lvds *lvds =3D encoder_to_lvds(encoder); + struct rockchip_crtc_state *s =3D + to_rockchip_crtc_state(encoder->crtc->state); + bool negedge =3D !!(s->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); + int ret; + + if (lvds->output !=3D DISPLAY_OUTPUT_LVDS) { + DRM_DEV_ERROR(lvds->dev, "Unsupported display output %d\n", + lvds->output); + return -EINVAL; + } + + ret =3D pm_runtime_resume_and_get(lvds->dev); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); + return ret; + } + + regmap_write(lvds->grf, RK3568_GRF_VO_CON2, + RK3568_LVDS0_MODE_EN(1) | RK3568_LVDS0_P2S_EN(1) | + RK3568_LVDS0_DCLK_INV_SEL(negedge)); + regmap_write(lvds->grf, RK3568_GRF_VO_CON0, + RK3568_LVDS0_SELECT(lvds->format) | + RK3568_LVDS0_MSBSEL(1)); + + return 0; +} + +static void rk3568_lvds_poweroff(struct rockchip_lvds *lvds) +{ + regmap_write(lvds->grf, RK3568_GRF_VO_CON2, + RK3568_LVDS0_MODE_EN(0) | RK3568_LVDS0_P2S_EN(0)); + + pm_runtime_put(lvds->dev); +} + +static void rk3568_lvds_encoder_enable(struct drm_encoder *encoder) +{ + struct rockchip_lvds *lvds =3D encoder_to_lvds(encoder); + int ret; + + drm_panel_prepare(lvds->panel); + + ret =3D rk3568_lvds_poweron(encoder); + if (ret) { + DRM_DEV_ERROR(lvds->dev, "failed to power on LVDS: %d\n", ret); + goto err_unprepare; + } + + /* The GRF must be in LVDS mode with dclk running before the phy. */ + ret =3D phy_set_mode(lvds->dphy, PHY_MODE_LVDS); + if (ret) { + DRM_DEV_ERROR(lvds->dev, "failed to set phy mode: %d\n", ret); + goto err_poweroff; + } + + ret =3D phy_power_on(lvds->dphy); + if (ret) { + DRM_DEV_ERROR(lvds->dev, "failed to power on phy: %d\n", ret); + goto err_poweroff; + } + + lvds->enabled =3D true; + drm_panel_enable(lvds->panel); + return; + +err_poweroff: + rk3568_lvds_poweroff(lvds); +err_unprepare: + drm_panel_unprepare(lvds->panel); +} + +static void rk3568_lvds_encoder_disable(struct drm_encoder *encoder) +{ + struct rockchip_lvds *lvds =3D encoder_to_lvds(encoder); + + /* + * .enable() cannot report failure, so the atomic helpers call this even + * when it bailed out and already unwound itself. Tear down only what an + * enable that ran to completion left behind, or the phy power count and + * the runtime-PM count of a half-enabled encoder underflow. + */ + if (!lvds->enabled) + return; + + drm_panel_disable(lvds->panel); + phy_power_off(lvds->dphy); + rk3568_lvds_poweroff(lvds); + drm_panel_unprepare(lvds->panel); + lvds->enabled =3D false; +} + static const struct drm_encoder_helper_funcs rk3288_lvds_encoder_helper_funcs =3D { .enable =3D rk3288_lvds_encoder_enable, @@ -449,6 +544,13 @@ struct drm_encoder_helper_funcs px30_lvds_encoder_help= er_funcs =3D { .atomic_check =3D rockchip_lvds_encoder_atomic_check, }; =20 +static const +struct drm_encoder_helper_funcs rk3568_lvds_encoder_helper_funcs =3D { + .enable =3D rk3568_lvds_encoder_enable, + .disable =3D rk3568_lvds_encoder_disable, + .atomic_check =3D rockchip_lvds_encoder_atomic_check, +}; + static int rk3288_lvds_probe(struct platform_device *pdev, struct rockchip_lvds *lvds) { @@ -512,6 +614,17 @@ static int px30_lvds_probe(struct platform_device *pde= v, return phy_power_on(lvds->dphy); } =20 +static int rk3568_lvds_probe(struct platform_device *pdev, + struct rockchip_lvds *lvds) +{ + /* The phy is powered on from the encoder enable path, not here. */ + lvds->dphy =3D devm_phy_get(&pdev->dev, "dphy"); + if (IS_ERR(lvds->dphy)) + return PTR_ERR(lvds->dphy); + + return phy_init(lvds->dphy); +} + static const struct rockchip_lvds_soc_data rk3288_lvds_data =3D { .probe =3D rk3288_lvds_probe, .helper_funcs =3D &rk3288_lvds_encoder_helper_funcs, @@ -522,6 +635,11 @@ static const struct rockchip_lvds_soc_data px30_lvds_d= ata =3D { .helper_funcs =3D &px30_lvds_encoder_helper_funcs, }; =20 +static const struct rockchip_lvds_soc_data rk3568_lvds_data =3D { + .probe =3D rk3568_lvds_probe, + .helper_funcs =3D &rk3568_lvds_encoder_helper_funcs, +}; + static const struct of_device_id rockchip_lvds_dt_ids[] =3D { { .compatible =3D "rockchip,rk3288-lvds", @@ -531,6 +649,10 @@ static const struct of_device_id rockchip_lvds_dt_ids[= ] =3D { .compatible =3D "rockchip,px30-lvds", .data =3D &px30_lvds_data }, + { + .compatible =3D "rockchip,rk3568-lvds", + .data =3D &rk3568_lvds_data + }, {} }; MODULE_DEVICE_TABLE(of, rockchip_lvds_dt_ids); @@ -601,6 +723,8 @@ static int rockchip_lvds_bind(struct device *dev, struc= t device *master, encoder =3D &lvds->encoder.encoder; encoder->possible_crtcs =3D drm_of_find_possible_crtcs(drm_dev, dev->of_node); + rockchip_drm_encoder_set_crtc_endpoint_id(&lvds->encoder, + dev->of_node, 0, 0); =20 ret =3D drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_LVDS); if (ret < 0) { diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.h b/drivers/gpu/drm/roc= kchip/rockchip_lvds.h index 2d92447..93d3415 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.h +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.h @@ -121,4 +121,14 @@ #define PX30_LVDS_P2S_EN(val) FIELD_PREP_WM16(BIT(6), (val)) #define PX30_LVDS_VOP_SEL(val) FIELD_PREP_WM16(BIT(1), (val)) =20 +#define RK3568_GRF_VO_CON0 0x0360 +#define RK3568_LVDS0_SELECT(val) FIELD_PREP_WM16(GENMASK(5, 4), (val)) +#define RK3568_LVDS0_MSBSEL(val) FIELD_PREP_WM16(BIT(3), (val)) + +#define RK3568_GRF_VO_CON2 0x0368 +#define RK3568_LVDS0_DCLK_INV_SEL(val) FIELD_PREP_WM16(BIT(9), (val)) +#define RK3568_LVDS0_DCLK_DIV2_SEL(val) FIELD_PREP_WM16(BIT(8), (val)) +#define RK3568_LVDS0_MODE_EN(val) FIELD_PREP_WM16(BIT(1), (val)) +#define RK3568_LVDS0_P2S_EN(val) FIELD_PREP_WM16(BIT(0), (val)) + #endif /* _ROCKCHIP_LVDS_ */ --=20 2.43.0 From nobody Fri Jul 24 21:53:37 2026 Received: from th8-b.mail-neoserv.si (th8-b.mail-neoserv.si [152.89.234.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8C3A3B4EA9; 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Received: from [193.77.36.193] (port=41890 helo=rok-trip.kanardia.eu) by th8.neoserv.si with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.99.4) (envelope-from ) id 1wnAxL-0000000AcoX-0w1h; Fri, 24 Jul 2026 10:08:31 +0200 From: Rok Markovic To: Heiko Stuebner , Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alibek Omarov , Rok Markovic Subject: [PATCH v2 4/4] arm64: dts: rockchip: rk356x: add LVDS node Date: Fri, 24 Jul 2026 10:08:24 +0200 Message-ID: <20260724080824.115260-5-rok@kanardia.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260724080824.115260-1-rok@kanardia.eu> References: <20260724080824.115260-1-rok@kanardia.eu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Authentication-Results: th8.neoserv.si; auth=pass (PLAIN) smtp.auth=rok@kanardia.eu X-NEOSERV-MailScanner-Information: Please contact the ISP for more information X-NEOSERV-MailScanner-ID: 1wnAxL-0000000AcoX-0w1h X-NEOSERV-MailScanner: Found to be clean X-NEOSERV-MailScanner-SpamCheck: not spam, SpamAssassin (not cached, score=1.31, required 7, ALL_TRUSTED -1.00, BAYES_50 0.80, KAM_DMARC_QUARANTINE 1.50, KAM_DMARC_STATUS 0.01) X-NEOSERV-MailScanner-SpamScore: s X-NEOSERV-MailScanner-From: rok@kanardia.eu X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - th8.neoserv.si X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - kanardia.eu X-Get-Message-Sender-Via: th8.neoserv.si: authenticated_id: rok@kanardia.eu X-Authenticated-Sender: th8.neoserv.si: rok@kanardia.eu Content-Type: text/plain; charset="utf-8" This commit adds the LVDS transmitter node for the RK356x SoC, assigning its D-PHY, GRF handle and power domain. The block has no register block and no clock of its own. It is left disabled by default, to be enabled by specific board files. Signed-off-by: Rok Markovic Assisted-by: Claude:claude-opus-4-8 --- Changes in v2: - Drop the clock from the LVDS node; the block takes none. arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index 64bdd8b..61a932a 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -878,6 +878,29 @@ }; }; =20 + lvds: lvds { + compatible =3D "rockchip,rk3568-lvds"; + phys =3D <&dsi_dphy0>; + phy-names =3D "dphy"; + power-domains =3D <&power RK3568_PD_VO>; + rockchip,grf =3D <&grf>; + rockchip,output =3D "lvds"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + lvds_in: port@0 { + reg =3D <0>; + }; + + lvds_out: port@1 { + reg =3D <1>; + }; + }; + }; + qos_gpu: qos@fe128000 { compatible =3D "rockchip,rk3568-qos", "syscon"; reg =3D <0x0 0xfe128000 0x0 0x20>; --=20 2.43.0