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charset="utf-8" The ENST start/on/off time register definitions for Q0 and Q1 are not referenced anywhere in the driver. The driver calculates these register addresses from the ENST base offset and the queue index instead of using fixed defines, removing the unused macros. Signed-off-by: Vineeth Karumanchi Reviewed-by: Nicolai Buchwitz Reviewed-by: Th=C3=A9o Lebrun --- drivers/net/ethernet/cadence/macb.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cad= ence/macb.h index 2de56017ee0d..a11052565436 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -184,12 +184,6 @@ #define GEM_DCFG8 0x029C /* Design Config 8 */ #define GEM_DCFG10 0x02A4 /* Design Config 10 */ #define GEM_DCFG12 0x02AC /* Design Config 12 */ -#define GEM_ENST_START_TIME_Q0 0x0800 /* ENST Q0 start time */ -#define GEM_ENST_START_TIME_Q1 0x0804 /* ENST Q1 start time */ -#define GEM_ENST_ON_TIME_Q0 0x0820 /* ENST Q0 on time */ -#define GEM_ENST_ON_TIME_Q1 0x0824 /* ENST Q1 on time */ -#define GEM_ENST_OFF_TIME_Q0 0x0840 /* ENST Q0 off time */ -#define GEM_ENST_OFF_TIME_Q1 0x0844 /* ENST Q1 off time */ #define GEM_ENST_CONTROL 0x0880 /* ENST control register */ #define GEM_USX_CONTROL 0x0A80 /* High speed PCS control register */ #define GEM_USX_STATUS 0x0A88 /* High speed PCS status register */ --=20 2.44.4 From nobody Fri Jul 24 22:18:16 2026 Received: from CY7PR03CU001.outbound.protection.outlook.com (mail-westcentralusazon11010042.outbound.protection.outlook.com [40.93.198.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 439BC368D4B; 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charset="utf-8" The initial "tc" command was not overwriting the reset value of ENST registers if only a subset of queues were configured, leading to an invalid setup. To fix this, configure all queues unconditionally. Unconfigured queues are zero-initialized via kcalloc(), ensuring a complete and consistent configuration. The queue_id field in struct macb_queue_enst_config becomes redundant once the array is indexed by queue id, so drop it. Key changes: - Drop queue_id from struct macb_queue_enst_config - Allocate enst_queue[] based on bp->num_queues instead of conf->num_entries - Index enst_queue[] directly with the queue number - Program ENST registers for all queues Fixes: 89934dbf169e ("net: macb: Add TAPRIO traffic scheduling support") Signed-off-by: Vineeth Karumanchi --- drivers/net/ethernet/cadence/macb.h | 2 -- drivers/net/ethernet/cadence/macb_main.c | 20 +++++++++----------- 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cad= ence/macb.h index a11052565436..4cc9aa9b2f9e 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -1490,7 +1490,6 @@ struct macb_platform_data { * @start_time_mask: Bitmask representing the start time for the queue * @on_time_bytes: "on" time nsec expressed in bytes * @off_time_bytes: "off" time nsec expressed in bytes - * @queue_id: Identifier for the queue * * This structure holds the configuration parameters for an ENST queue, * used to control time-based transmission scheduling in the MACB driver. @@ -1499,7 +1498,6 @@ struct macb_queue_enst_config { u32 start_time_mask; u32 on_time_bytes; u32 off_time_bytes; - u8 queue_id; }; =20 #endif /* _MACB_H */ diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/etherne= t/cadence/macb_main.c index d394f1f43b68..d58430fe9c41 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -4329,7 +4329,7 @@ static int macb_taprio_setup_replace(struct net_devic= e *ndev, struct macb_queue *queue; u32 queue_mask; u8 queue_id; - size_t i; + size_t i, q; int err; =20 if (conf->num_entries > bp->num_queues) { @@ -4357,7 +4357,7 @@ static int macb_taprio_setup_replace(struct net_devic= e *ndev, return -EINVAL; } =20 - enst_queue =3D kcalloc(conf->num_entries, sizeof(*enst_queue), GFP_KERNEL= ); + enst_queue =3D kcalloc(bp->num_queues, sizeof(*enst_queue), GFP_KERNEL); if (unlikely(!enst_queue)) return -ENOMEM; =20 @@ -4416,13 +4416,12 @@ static int macb_taprio_setup_replace(struct net_dev= ice *ndev, goto cleanup; } =20 - enst_queue[i].queue_id =3D queue_id; - enst_queue[i].start_time_mask =3D + enst_queue[queue_id].start_time_mask =3D (start_time_sec << GEM_START_TIME_SEC_OFFSET) | start_time_nsec; - enst_queue[i].on_time_bytes =3D + enst_queue[queue_id].on_time_bytes =3D enst_ns_to_hw_units(entry->interval, speed); - enst_queue[i].off_time_bytes =3D + enst_queue[queue_id].off_time_bytes =3D enst_ns_to_hw_units(conf->cycle_time - entry->interval, speed); =20 configured_queues |=3D entry->gate_mask; @@ -4448,15 +4447,14 @@ static int macb_taprio_setup_replace(struct net_dev= ice *ndev, gem_writel(bp, ENST_CONTROL, queue_mask << GEM_ENST_DISABLE_QUEUE_OFFSET); =20 - for (i =3D 0; i < conf->num_entries; i++) { - queue =3D &bp->queues[enst_queue[i].queue_id]; + for (q =3D 0, queue =3D bp->queues; q < bp->num_queues; ++q, ++queue) { /* Configure queue timing registers */ queue_writel(queue, ENST_START_TIME, - enst_queue[i].start_time_mask); + enst_queue[q].start_time_mask); queue_writel(queue, ENST_ON_TIME, - enst_queue[i].on_time_bytes); + enst_queue[q].on_time_bytes); queue_writel(queue, ENST_OFF_TIME, - enst_queue[i].off_time_bytes); + enst_queue[q].off_time_bytes); } =20 /* Enable ENST for all configured queues in one write */ --=20 2.44.4