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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf8efe3afbsm45993805ad.33.2026.07.24.00.18.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 00:18:48 -0700 (PDT) From: Pragnesh Papaniya Date: Fri, 24 Jul 2026 12:48:06 +0530 Subject: [PATCH RFC 01/10] firmware: arm_scmi: Add SCMI QCOM Generic Extension Protocol documentation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-rfc_v8_scmi_memlat-v1-1-cb732bcff1f4@oss.qualcomm.com> References: <20260724-rfc_v8_scmi_memlat-v1-0-cb732bcff1f4@oss.qualcomm.com> In-Reply-To: <20260724-rfc_v8_scmi_memlat-v1-0-cb732bcff1f4@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784877514; l=58108; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=NVwa6oaza24/Csd5TLISWX6+QzD3TmEvlvRTB2GzPf0=; b=1vcG58oBTHxKWyCUb/QHgPOpMkgL3KjhIwtMHGGndu9s6uMtvJ9Qe8KDa6zTXcpqruAcM03Hz FPbRJXA/IhZBllzWljEh6MUolyQMYGpAKKsOG3PA9CMLVV5JuUhSs6X X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDA2NSBTYWx0ZWRfX98eU1PANyi6D /njVJA5hk+EGzQrdHsnHieg7HQgPy0JcW5SjoSBx/mdPE71AUTNrshdmErJtruzClhpnDcwfyow wU01G3B1Gxp+LgNVK4r7mrgf33ZSWqM= X-Proofpoint-ORIG-GUID: jQxO3Lq-sLQ_0G54CUFu6zUIKzZ96Nzd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDA2NSBTYWx0ZWRfXzX7VQjOze3T5 h5fg5rlZRdPQ5DpaoTFqg65Cy+53mhkwEoDnL1IohS5Hdke4xcL66DNweiCxOfvNRV7GsycRzCS pwjb+vWFdPRMYklqAu6ShEzg8uksOlbhz2X98/DEwBkaI4cdpZZK/+b20Xxo4SlDaMsG9mdNoC4 IsIJ49/Y/NdR35Aip3NhbRoU8V7uMDSNc4NsgLuYXtXI0J2FbOnWApNwd+koZjyvPzI5YkdZvUR bv1SYL+BaqTGf/rTMhe/IqRpm+fq9j2giY5+YpcubXOHUUA10XPGMkn765IIVln3BZvqfZ6JOCC 2Vj0/QkRmw4gTEuv+RD3EvhIbRgwVjapwofyZXFzdesWEjCrLgE7mzgd1qbP/Thi3PFUtLaw+sT wbbUqk+CrMTunAWqSFfV/NHRXIkUbK3OPZwSN7XHTu1z2C2RmOeSA05Zw7UBH7WjR4CAASVgUP1 rgjzZpw9vM0iYLu1/dQ== X-Authority-Analysis: v=2.4 cv=PtejqQM3 c=1 sm=1 tr=0 ts=6a6311e0 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=xn6pn0MgdEpbbIXp4LUA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: jQxO3Lq-sLQ_0G54CUFu6zUIKzZ96Nzd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_01,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240065 Add System Control Management Interface (SCMI) Qualcomm Generic Extension Protocol documentation. It consists of a small set of generic SET/GET/ START/STOP commands, which is used to turn on/off and configure Qualcomm SoC specific algorithms that run on the SCP. It currently only supports MEMLAT (memory latency governor) algorithm. The immutable pairing of the MEMLAT algorithm string with the supported param_ids associated with it are documented here. Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya --- .../arm_scmi/vendors/qcom/qcom_generic.rst | 954 +++++++++++++++++= ++++ 1 file changed, 954 insertions(+) diff --git a/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst b/driv= ers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst new file mode 100644 index 000000000000..42e327d53841 --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst @@ -0,0 +1,954 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D +System Control and Management Interface (SCMI) Qualcomm Generic Extension = Protocol +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +:Copyright: |copy| Qualcomm Technologies, Inc. and/or its subsidiaries. + +:Authors: + - Sibi Sankar + - Pragnesh Papaniya + +System Control and Management Interface Qualcomm Generic Extension Vendor = Protocol +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +System Control Management Interface (SCMI) Qualcomm Generic Extension Prot= ocol +consists of a small set of generic SET/GET/START/STOP commands, which is u= sed to +turn on/off and configure Qualcomm SoC specific algorithms that run on the= SCP. +Each algorithm is identified through an algorithm string and has an immuta= ble list +of param_ids. All supported algorithms (currently just MEMLAT) have their = own +dedicated section and are listed after the generic commands. + +Commands: +_________ + +PROTOCOL_VERSION +~~~~~~~~~~~~~~~~ + +message_id: 0x0 +protocol_id: 0x80 + ++---------------+---------------------------------------------------------= -----+ +|Return values = | ++---------------+---------------------------------------------------------= -----+ +|Name |Description = | ++---------------+---------------------------------------------------------= -----+ +|int32 status |See ARM SCMI Specification for status code definitions. = | ++---------------+---------------------------------------------------------= -----+ +|uint32 version |For this revision of the specification, this value must b= e | +| |0x10000. = | ++---------------+---------------------------------------------------------= -----+ + +PROTOCOL_ATTRIBUTES +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x1 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |See ARM SCMI Specification for status code definitions= . | ++------------------+------------------------------------------------------= -----+ +|uint32 attributes |Bits[31:16] Reserved, must be set to 0. = | +| |Bits[15:8] Number of agents in the system. Must match = the | +| |value reported by the standard BASE protocol's = | +| |PROTOCOL_ATTRIBUTES response. = | +| |Bits[7:0] Number of algorithmic strings supported by t= he | +| |system. Only "MEMLAT" is currently supported hence it = | +| |returns 1. = | ++------------------+------------------------------------------------------= -----+ + +PROTOCOL_MESSAGE_ATTRIBUTES +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x2 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |See ARM SCMI Specification for status code definitions= . | ++------------------+------------------------------------------------------= -----+ +|uint32 attributes |For all message IDs the parameter has a value of 0. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_SET_PARAM +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x10 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g | +| |and is used to set various parameters supported by it.= | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload for the specified param_id and = | +| |algorithm string pair. The payload size depends on the= | +| |(algorithm string, param_id) pair; see the per-algorit= hm | +| |sections below. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the param_id and buf[] is parsed successfu= lly | +| |by the chosen algorithm string. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches. = | +| |INVALID_PARAMETERS: if the param_id and the buf[] pass= ed | +| |is rejected by the algorithm string. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_GET_PARAM +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x11 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g. | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload and store of value for the speci= fied | +| |param_id and algorithm string pair. The payload size = | +| |depends on the (algorithm string, param_id) pair; see = the | +| |per-algorithm sections below. The response payload is = | +| |returned in the same buffer, overwriting the request = | +| |contents on success. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the param_id and buf[] is parsed successfu= lly | +| |by the chosen algorithm string and the result is copie= d | +| |into buf[]. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches. = | +| |INVALID_PARAMETERS: if the param_id and the buf[] pass= ed | +| |is rejected by the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Holds the payload of the result of the query, returned= in | +| |the same buffer used to send the request. Size depends= on | +| |the (algorithm string, param_id) pair. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_START_ACTIVITY +~~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x12 +protocol_id: 0x80 + +The activity to be started is defined by the algorithm string; see the +per-algorithm sections (e.g. MEMLAT_START_TIMER) for valid param_ids. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g | +| |and is generally used to start the activity performed = by | +| |the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload for the specified param_id and = | +| |algorithm string pair. The payload size depends on the= | +| |(algorithm string, param_id) pair; see the per-algorit= hm | +| |sections below. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the activity performed by the algorithm st= ring | +| |starts successfully, or if it was already running. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_STOP_ACTIVITY +~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x13 +protocol_id: 0x80 + +The activity to be stopped is defined by the algorithm string; see the +per-algorithm sections (e.g. MEMLAT_STOP_TIMER) for valid param_ids. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g | +| |and is generally used to stop the activity performed b= y | +| |the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload for the specified param_id and = | +| |algorithm string pair. The payload size depends on the= | +| |(algorithm string, param_id) pair; see the per-algorit= hm | +| |sections below. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the activity performed by the algorithm st= ring | +| |stops successfully, or if it was not running. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT: Memory Latency algorithm +________________________________ + +The MEMLAT algorithm (0x4d454d4c4154, ASCII "MEMLAT") scales the DDR, LLCC= and +DDR_QOS buses in response to memory-latency-bound workloads. It runs on th= e CPUCP: +every sampling window it reads the per-CPU AMU counters, derives its stati= stics +(instructions-per-miss, back-end stall, write-back ratio), maps that to a = target +level and votes for it directly on the DDR/LLCC/DDR_QOS interconnect. The = kernel +never issues a frequency request in that loop. The 6-byte value is treated= as a +64-bit algorithm string and split into two uint32 fields on the wire: algo= _low +carries its lower 32 bits and algo_high its upper 32 bits. + +With a distinct need to have the memory buses scaling done in SCP in respo= nse to +memory-latency-bound workloads, none of the existing SCMI solutions could = be used +as-is. MPAM does not apply either: it is not enabled on all of the affecte= d parts +(e.g. Hamoa). The role split between SCP and client driver is described ne= xt. + +MEMLAT client driver pseudo-code: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: text + + probe(): + SET_COMMON_EV_MAP # AMU events (all groups) + for each memory group (DDR / LLCC / DDR_QOS): + SET_MEM_GROUP # bind group to interconnect + SET_GRP_EV_MAP # per-group AMU events + for each monitor in the group: + SET_MONITOR # topology, cpumask, name + IPM_CEIL / BE_STALL_FLOOR # per-monitor tuneables + MON_FREQ_MAP # cpufreq -> memfreq map + SET_MIN_FREQ / SET_MAX_FREQ # clamps + SAMPLE_MS # sampling period + SET_EFFECTIVE_FREQ_METHOD # cpu-freq derivation method + START_TIMER # CPUCP now scales autonomo= usly + + devfreq poll (twice per CPUCP sample period): + GET_CUR_FREQ # read voted freq, per moni= tor + + remove(): + STOP_TIMER + +SCP pseudo-code: +~~~~~~~~~~~~~~~~ + +.. code-block:: text + + every sample_ms: + for each CPU: + sample AMU counters (instructions, cycles, cache-misses, stalls) + derive per-CPU IPM, back-end-stall % and write-back ratio + + for each configured memory group (DDR / LLCC / DDR_QOS): + for each monitor in the group: + best_freq =3D 0 + for each CPU in the monitor's cpumask: + if CPU is memory-bound (IPM/stall/write-back vs. the + monitor's configured thresholds): + freq =3D CPU's cpufreq, optionally scaled toward the ceiling + best_freq =3D max(best_freq, freq) + monitor.target_freq =3D monitor's cpufreq->memfreq map(best_freq) + + group_vote =3D max(target_freq of every monitor in the group) + if group_vote changed since the last sample: + vote group_vote onto the group's interconnect path + + GET_CUR_FREQ returns a monitor's last target_freq + START_TIMER / STOP_TIMER: resume / suspend the loop above + +MEMLAT: Supported memory buses +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The hw_type field carried in most payloads identifies the memory group: + ++----------+--------------------------------------------------------------+ +|hw_type |Group | ++----------+--------------------------------------------------------------+ +|0 |DDR | ++----------+--------------------------------------------------------------+ +|1 |LLCC | ++----------+--------------------------------------------------------------+ +|2 |DDR_QOS_COMPUTE | ++----------+--------------------------------------------------------------+ +|3 |DDR_QOS_MOBILE | ++----------+--------------------------------------------------------------+ + +All multi-byte fields below are little-endian. mon_idx selects a monitor +within the group (0-based, less than the firmware-supported maximum). All +SET commands return the SCMI status word; on success it carries SUCCESS, on +lookup failure INVALID_PARAMETERS, and on an unknown param_id NOT_SUPPORTE= D. + +Frequency units are not uniform across commands (kHz, MHz or a raw 0/1 +DDR_QOS level, depending on the param_id); each command documents its own +units below. + +MEMLAT_SET_MEM_GROUP +~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x10 (16) +command: QCOM_SCMI_SET_PARAM + +Allocates a new memory group on the firmware side and binds it to the +underlying interconnect path (DDR / LLCC / DDR_QOS). + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 cpumask |Bitmask of HW CPU IDs that contribute counters to this= | +| |group (limited to 32 CPUs). = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier (0 =3D DDR, 1 =3D LLCC, = | +| |2 =3D DDR_QOS_COMPUTE, 3 =3D DDR_QOS_MOBILE). = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_type |Reserved for SET_MEM_GROUP (set to 0; populated only o= n | +| |SET_MONITOR). = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Reserved for SET_MEM_GROUP (set to 0). = | ++------------------+------------------------------------------------------= -----+ +|char mon_name[20] |Reserved for SET_MEM_GROUP (zero-filled). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: group allocated. = | +| |BUSY: no free memory group slot (the firmware-supporte= d | +| |maximum number of groups is already configured). = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SET_MONITOR +~~~~~~~~~~~~~~~~~~ + +param_id: 0x11 (17) +command: QCOM_SCMI_SET_PARAM + +Adds a monitor (a CPU subset that votes within an already-configured +group). + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 cpumask |Bitmask of HW CPU IDs assigned to this monitor (must b= e a | +| |subset of the group's cpumask; limited to 32 CPUs). = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier the monitor belongs to. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_type |0 =3D IPM-based latency monitor, 1 =3D compute (passiv= e | +| |governor tracking cpufreq map irrespective of IPM) mon= itor | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Index of the monitor within the group. = | ++------------------+------------------------------------------------------= -----+ +|char mon_name[20] |Human-readable monitor name (NUL-terminated, used in = | +| |firmware log lines). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: monitor created. = | +| |NOT_FOUND: hw_type does not match any configured group= , or | +| |the firmware-supported maximum number of monitors alre= ady | +| |exist for the group. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SET_COMMON_EV_MAP +~~~~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x12 (18) +command: QCOM_SCMI_SET_PARAM + +Configures the common counter IDs (instructions, cycles, stall, etc.) +that the firmware reads on every sample for every CPU. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 num_evs |Number of valid entries in cid[]. = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Set to 0xFF (sentinel for the common-events case). = | ++------------------+------------------------------------------------------= -----+ +|uint8 cid[] |Array of CPUCP counter IDs indexed by INST/CYC/CONST_C= YC/ | +| |FE_STALL/BE_STALL. 0xFF marks an unused slot. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if num_evs exceeds the = | +| |firmware-supported maximum. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SET_GRP_EV_MAP +~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x13 (19) +command: QCOM_SCMI_SET_PARAM + +Configures the per-group event IDs (cache miss / writeback / access) +used by the IPM and write-back computations for the selected hw_type. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 num_evs |Number of valid entries in cid[]. = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint8 cid[] |Array of CPUCP counter IDs indexed by MISS/WB/ACC. 0xF= F | +| |marks an unused slot. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if hw_type is unknown or = | +| |num_evs exceeds the firmware-supported maximum. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_ADAPTIVE_LOW_FREQ +~~~~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x14 (20) +command: QCOM_SCMI_SET_PARAM + +Sets the adaptive low-frequency floor for a group. When the algorithm's +voted frequency falls below this floor the firmware clamps it up to the +adaptive floor instead. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Ignored (group-scoped parameter). = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Adaptive low frequency in kHz (converted to MHz by the= | +| |firmware). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if hw_type does not match= a | +| |configured group. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_ADAPTIVE_HIGH_FREQ +~~~~~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x15 (21) +command: QCOM_SCMI_SET_PARAM + +Sets the adaptive high-frequency floor for a group. Units and behaviour +mirror MEMLAT_ADAPTIVE_LOW_FREQ. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Ignored (group-scoped parameter). = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Adaptive high frequency in kHz (converted to MHz by th= e | +| |firmware). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if hw_type does not match= a | +| |configured group. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_GET_ADAPTIVE_CUR_FREQ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x16 (22) +command: QCOM_SCMI_GET_PARAM + +Reads the group's current adaptive frequency. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if hw_type does not match= a | +| |configured group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 cur_freq |Current adaptive frequency in kHz. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_IPM_CEIL +~~~~~~~~~~~~~~~ + +param_id: 0x17 (23) +command: QCOM_SCMI_SET_PARAM + +Sets the IPM (Instructions-Per-Miss) ceiling for a monitor. CPUs whose +IPM falls at or below this ceiling are considered memory-bound and +contribute their cpufreq into the monitor's voting pool. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |IPM ceiling (instructions per cache miss). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_FE_STALL_FLOOR +~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x18 (24) +command: QCOM_SCMI_SET_PARAM + +Sets the front-end stall floor (in percent) for a monitor. Analogous to +MEMLAT_BE_STALL_FLOOR but for front-end stalls. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Front-end stall floor in percent (0..100). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_BE_STALL_FLOOR +~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x19 (25) +command: QCOM_SCMI_SET_PARAM + +Sets the back-end stall floor (in percent) for a monitor. CPUs whose +back-end stall percentage is at or above this floor are eligible to have +their cpufreq scaled up by the freq-scale knobs below. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Back-end stall floor in percent (0..100). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_WB_PCT +~~~~~~~~~~~~~ + +param_id: 0x1A (26) +command: QCOM_SCMI_SET_PARAM + +Sets the write-back ratio threshold (in percent) for a monitor. A CPU's +write-back ratio must be at or above this value for the monitor to treat +it as memory-bound. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Write-back ratio threshold in percent. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_IPM_FILTER +~~~~~~~~~~~~~~~~~ + +param_id: 0x1B (27) +command: QCOM_SCMI_SET_PARAM + +Sets the IPM filter for a monitor. A CPU's IPM must be at or below this +value (in addition to the write-back check) for the monitor to select it. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |IPM filter (instructions per cache miss). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_FREQ_SCALE_PCT +~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x1C (28) +command: QCOM_SCMI_SET_PARAM + +Sets the frequency-scale percentage for a monitor. When non-zero, a +memory-bound CPU's effective frequency is boosted proportionally to how +far its IPM is below the ceiling, bounded by the scale floor/ceiling +below. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Frequency-scale factor in percent. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_FREQ_SCALE_CEIL_MHZ +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x1D (29) +command: QCOM_SCMI_SET_PARAM + +Sets the upper cpufreq bound (in MHz) for the freq-scale boost above. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Frequency-scale ceiling in MHz. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_FREQ_SCALE_FLOOR_MHZ +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x1E (30) +command: QCOM_SCMI_SET_PARAM + +Sets the lower cpufreq bound (in MHz) for the freq-scale boost above. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Frequency-scale floor in MHz. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SAMPLE_MS +~~~~~~~~~~~~~~~~ + +param_id: 0x1F (31) +command: QCOM_SCMI_SET_PARAM + +Sets the sampling period (in milliseconds) used by the firmware update +loop. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 sample_ms |Sampling period in milliseconds. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_MON_FREQ_MAP +~~~~~~~~~~~~~~~~~~~ + +param_id: 0x20 (32) +command: QCOM_SCMI_SET_PARAM + +Programs the cpufreq to memfreq voting table for a single monitor. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 nr_rows |Number of valid rows in tbl[] (must not exceed the = | +| |firmware-supported maximum). = | ++------------------+------------------------------------------------------= -----+ +|struct { |Per-row mapping. cpu_freq_mhz is the cpufreq trigger i= n | +|u16 cpu_freq_mhz; |MHz; mem_freq_mhz is the resulting memfreq vote (MHz f= or | +|u16 mem_freq_mhz; |DDR/LLCC, a level index 0/1 for DDR_QOS). = | +|} tbl[] | = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) is = | +| |unknown / OUT_OF_RANGE if nr_rows exceeds the = | +| |firmware-supported maximum. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SET_MIN_FREQ +~~~~~~~~~~~~~~~~~~~ + +param_id: 0x21 (33) +command: QCOM_SCMI_SET_PARAM + +Clamps a monitor's vote to a minimum value. Units are kHz for DDR/LLCC and +raw level index for DDR_QOS. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Minimum frequency: kHz for DDR/LLCC, level for DDR_QOS= . | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SET_MAX_FREQ +~~~~~~~~~~~~~~~~~~~ + +param_id: 0x22 (34) +command: QCOM_SCMI_SET_PARAM + +Clamps a monitor's vote to a maximum value. Units identical to +MEMLAT_SET_MIN_FREQ. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Maximum frequency: kHz for DDR/LLCC, level for DDR_QOS= . | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_GET_CUR_FREQ +~~~~~~~~~~~~~~~~~~~ + +param_id: 0x23 (35) +command: QCOM_SCMI_GET_PARAM + +Reads the current target frequency that the firmware is voting for the +selected (hw_type, mon_idx) tuple. The response payload is returned in +the same buffer used to send the request, overwriting it on success. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ +|uint32 cur_freq |Current target frequency in kHz for DDR/LLCC; raw leve= l | +| |(0/1) for DDR_QOS. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_START_TIMER +~~~~~~~~~~~~~~~~~~ + +param_id: 0x24 (36) +command: QCOM_SCMI_START_ACTIVITY + +Starts the firmware sampling and voting loop at the configured +sample_ms interval. Has no payload beyond the QCOM_SCMI_START_ACTIVITY +header. + ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: timer started (or was already running). = | +| |GENERIC_ERROR: events not yet initialized = | +| |(MEMLAT_SET_GRP_EV_MAP not called for any group). = | +| |NOT_SUPPORTED: invalid param_id under START_ACTIVITY. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_STOP_TIMER +~~~~~~~~~~~~~~~~~ + +param_id: 0x25 (37) +command: QCOM_SCMI_STOP_ACTIVITY + +Suspends the firmware sampling and voting loop. Has no payload beyond +the QCOM_SCMI_STOP_ACTIVITY header. The configured monitors and freq +maps are retained, so a subsequent MEMLAT_START_TIMER resumes voting +without re-programming. + ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: timer stopped (or was already stopped). = | +| |NOT_SUPPORTED: invalid param_id under STOP_ACTIVITY. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_GET_TIMESTAMP +~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x26 (38) +command: QCOM_SCMI_GET_PARAM + +Reads the firmware timestamp (nanoseconds). + ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS. = | ++------------------+------------------------------------------------------= -----+ +|uint64 tstamp |Firmware timestamp in nanoseconds. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SET_EFFECTIVE_FREQ_METHOD +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x27 (39) +command: QCOM_SCMI_SET_PARAM + +Selects the algorithm used to derive the per-CPU effective frequency +from the cycle counters. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 method |0: const-cycles method (CPU cycles / const-cycles, sca= led | +| |by the cluster's max frequency). = | +| |1: legacy method (CPU cycles / sampling-window time). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if method is not 0 or 1. = | ++------------------+------------------------------------------------------= -----+ --=20 2.34.1 From nobody Fri Jul 24 21:54:50 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D5983A7D7A for ; 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Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya --- .../devicetree/bindings/firmware/arm,scmi.yaml | 1 + .../bindings/firmware/qcom,generic-scmi.yaml | 27 ++++++++++++++++++= ++++ 2 files changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Doc= umentation/devicetree/bindings/firmware/arm,scmi.yaml index 6fc44105f1c3..85f06a6a7452 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -24,6 +24,7 @@ description: | =20 anyOf: - $ref: /schemas/firmware/nxp,imx95-scmi.yaml + - $ref: /schemas/firmware/qcom,generic-scmi.yaml =20 properties: $nodename: diff --git a/Documentation/devicetree/bindings/firmware/qcom,generic-scmi.y= aml b/Documentation/devicetree/bindings/firmware/qcom,generic-scmi.yaml new file mode 100644 index 000000000000..a50e5e8fdccc --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/qcom,generic-scmi.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/qcom,generic-scmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: System Control and Management Interface (SCMI) Qualcomm Generic Ext= ension Protocol + +maintainers: + - Pragnesh Papaniya + - Sibi Sankar + +properties: + protocol@80: + description: + SCMI Qualcomm Generic Extension Protocol exposes Qualcomm SoC specif= ic + algorithms such as Memory Latency (MEMLAT) bound DDR/LLCC/DDR-QOS bu= s DVFS. + The algorithm runs on the SCP, it can be turned on/off and be config= ured + through a pairing of algorithm strings with an immutable list param_= ids. + $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' + unevaluatedProperties: false + + properties: + reg: + const: 0x80 + +additionalProperties: true --=20 2.34.1 From nobody Fri Jul 24 21:54:50 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C21A3A7F4A for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf8efe3afbsm45993805ad.33.2026.07.24.00.18.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 00:19:03 -0700 (PDT) From: Pragnesh Papaniya Date: Fri, 24 Jul 2026 12:48:08 +0530 Subject: [PATCH RFC 03/10] firmware: arm_scmi: vendors: Add QCOM SCMI Generic Extensions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-rfc_v8_scmi_memlat-v1-3-cb732bcff1f4@oss.qualcomm.com> References: <20260724-rfc_v8_scmi_memlat-v1-0-cb732bcff1f4@oss.qualcomm.com> In-Reply-To: <20260724-rfc_v8_scmi_memlat-v1-0-cb732bcff1f4@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, Amir Vajid , Ramakrishna Gottimukkula X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784877514; l=12506; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=vBs1nrZfnrohzT4k2onMHNTX4TddQbE0+AmlJbHYHu0=; b=LRr4gPrWhvzZt2NhfqsIf1G9MexjRNr+aJ+U6LRom7Y8/B5rsHRtw8EBz76LP/biLifMAsPX1 Ly/y0EflGLXC3JATLvxtAZGXD9CGDQPhHbpdnzVAMGCzX4Izvni0Krp X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Proofpoint-ORIG-GUID: PwMd_3X-eeap9KikvlJO-nRSwrwzqi7W X-Proofpoint-GUID: PwMd_3X-eeap9KikvlJO-nRSwrwzqi7W X-Authority-Analysis: v=2.4 cv=e/k2j6p/ c=1 sm=1 tr=0 ts=6a6311f0 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=3GEwtj1osWxiqG9AIrUA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDA2NSBTYWx0ZWRfXwfdLe1RcZpXs mjV2NT5Gg3o2qORulMB4wI7YY1y0hi/yJS7KooG9CnG3VCe2Gs3XsmPPlznaRMY0ykVvnjoiQ3r RGPUv/7yw5suO/juQCQCj46gHSy+Z4r3wtU+f75eUiS3I6bPgLfJwqVYpx/CZEq1agsVj3xCzwv JWp3ehzuc9v8tMpoB58yjmdqn8utHBiYVco5KHVJpCDYNyQERLFpTstxJV20fCsl0AOval9swSA a65feHecGjV7NydicLsjXQ1kGCCOWE1/4rVRKOPqRHH+PMuDfxvu3YiczeccRFyQ8cy+vjOuJAh H7m0MZGgwJue5mOBOKEYqPPncsuiNYG8X09UFK8QpHmK1DKKBQOgoCdVjc82UeDr91F1R+nI82+ +tWH8CaGcYVbDAi2Pz+7rnb7B/vX231LtP1y5ygE6OwybPvgQFU6kT7kkeXcZXyEDV294iR8HtZ vXNeUmiAibPlsc6SpbQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDA2NSBTYWx0ZWRfX0V48DXofC6PG L8D/42Cg11Glh6bBnkh/tqiwho/ey2CTRCIM9+9BDzMKNBuask6i6RM3v3b8742IimEcKyfAoVy cCg8hN1DCAoePtZv7R5dRa7SsBAvZMg= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_01,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240065 From: Sibi Sankar The System Control Management Interface (SCMI) Qualcomm Generic Extension Protocol consists of a small set of generic SET/GET/ START/STOP commands, which is used to turn on/off and configure Qualcomm SoC specific algorithms that run on the SCP. Co-developed-by: Amir Vajid Signed-off-by: Amir Vajid Co-developed-by: Ramakrishna Gottimukkula Signed-off-by: Ramakrishna Gottimukkula Signed-off-by: Sibi Sankar Co-developed-by: Pragnesh Papaniya Signed-off-by: Pragnesh Papaniya --- MAINTAINERS | 10 ++ drivers/firmware/arm_scmi/Kconfig | 1 + drivers/firmware/arm_scmi/Makefile | 1 + drivers/firmware/arm_scmi/vendors/qcom/Kconfig | 15 ++ drivers/firmware/arm_scmi/vendors/qcom/Makefile | 2 + .../arm_scmi/vendors/qcom/qcom-generic-ext.c | 183 +++++++++++++++++= ++++ include/linux/scmi_qcom_protocol.h | 37 +++++ 7 files changed, 249 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cc3c01eecfa2..265eb99bdc7a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26487,6 +26487,16 @@ S: Maintained F: Documentation/devicetree/bindings/firmware/nxp,*scmi.yaml F: drivers/firmware/arm_scmi/vendors/imx/ =20 +SYSTEM CONTROL MANAGEMENT INTERFACE (SCMI) Qualcomm Generic Extension Prot= ocol driver +M: Pragnesh Papaniya +M: Sibi Sankar +L: arm-scmi@vger.kernel.org +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/firmware/qcom,generic-scmi.yaml +F: drivers/firmware/arm_scmi/vendors/qcom/ +F: include/linux/scmi_qcom_protocol.h + SYSTEM RESET/SHUTDOWN DRIVERS M: Sebastian Reichel L: linux-pm@vger.kernel.org diff --git a/drivers/firmware/arm_scmi/Kconfig b/drivers/firmware/arm_scmi/= Kconfig index 783c24a20e29..3918aa2e7140 100644 --- a/drivers/firmware/arm_scmi/Kconfig +++ b/drivers/firmware/arm_scmi/Kconfig @@ -84,6 +84,7 @@ config ARM_SCMI_QUIRKS =20 source "drivers/firmware/arm_scmi/transports/Kconfig" source "drivers/firmware/arm_scmi/vendors/imx/Kconfig" +source "drivers/firmware/arm_scmi/vendors/qcom/Kconfig" =20 endif #ARM_SCMI_PROTOCOL =20 diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi= /Makefile index 780cd62b2f78..5a0e003c2477 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -13,6 +13,7 @@ scmi-module-objs :=3D $(scmi-driver-y) $(scmi-protocols-y= ) $(scmi-transport-y) =20 obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D transports/ obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D vendors/imx/ +obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D vendors/qcom/ =20 obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D scmi-core.o obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D scmi-module.o diff --git a/drivers/firmware/arm_scmi/vendors/qcom/Kconfig b/drivers/firmw= are/arm_scmi/vendors/qcom/Kconfig new file mode 100644 index 000000000000..8aa0efd6a03d --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "ARM SCMI QCOM Vendor Protocols" + +config QCOM_SCMI_GENERIC_EXT + tristate "Qualcomm Technologies, Inc. SCMI Generic Vendor Protocol" + depends on ARM_SCMI_PROTOCOL || (COMPILE_TEST && OF) + help + The QCOM SCMI vendor protocol provides a generic way of exposing + a number of Qualcomm SoC specific features (like memory bus scaling) + through a mixture of pre-determined algorithm strings and param_id + pairs hosted on the SCMI controller. + + This driver defines/documents the message IDs used for this + communication and also exposes the operations used by the clients. +endmenu diff --git a/drivers/firmware/arm_scmi/vendors/qcom/Makefile b/drivers/firm= ware/arm_scmi/vendors/qcom/Makefile new file mode 100644 index 000000000000..6b98fabbebb8 --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_QCOM_SCMI_GENERIC_EXT) +=3D qcom-generic-ext.o diff --git a/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c b/dr= ivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c new file mode 100644 index 000000000000..7ca920c8da05 --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include "../../common.h" + +/* + * This protocol is intended as a generic way of exposing a number of Qual= comm + * SoC specific features through a mixture of pre-determined algorithm str= ing + * and param_id pairs hosted on the SCMI controller. + * + * The QCOM SCMI Vendor Protocol has the protocol id as 0x80 and vendor id= set + * to Qualcomm and the supported version is set to 0x10000. The PROTOCOL_V= ERSION + * command returns version 1.0. + */ + +/** + * enum qcom_generic_ext_protocol_cmd - vendor specific commands supported= by SCMI Qualcomm + * generic vendor protocol. + * + * @QCOM_SCMI_SET_PARAM: is used to set the parameter of a specific algo_s= tr hosted on + * QCOM SCMI Vendor Protocol. The tx len depends on the algo_str used. + * @QCOM_SCMI_GET_PARAM: is used to get parameter information of a specifi= c algo_str + * hosted on QCOM SCMI Vendor Protocol. The tx and rx len depends + * on the algo_str used. + * @QCOM_SCMI_START_ACTIVITY: is used to start the activity performed by t= he algo_str. + * @QCOM_SCMI_STOP_ACTIVITY: is used to stop a pre-existing activity perfo= rmed by the algo_str. + */ +enum qcom_generic_ext_protocol_cmd { + QCOM_SCMI_SET_PARAM =3D 0x10, + QCOM_SCMI_GET_PARAM =3D 0x11, + QCOM_SCMI_START_ACTIVITY =3D 0x12, + QCOM_SCMI_STOP_ACTIVITY =3D 0x13, +}; + +/** + * struct qcom_scmi_msg - represents the various parameters to be populated + * for using the QCOM SCMI Vendor Protocol + * + * @ext_id: reserved, must be zero + * @algo_low: lower 32 bits of the algo_str + * @algo_high: upper 32 bits of the algo_str + * @param_id: serves as token message id to the specific algo_str + * @buf: serves as the payload to the specified param_id and algo_str pair + */ +struct qcom_scmi_msg { + __le32 ext_id; + __le32 algo_low; + __le32 algo_high; + __le32 param_id; + __le32 buf[]; +}; + +/* + * The firmware only implements a handful of algorithm strings. Keep an + * allowlist so a client cannot push an unsupported (or garbage) string to + * the firmware; extend it as new algorithms are added. + */ +static const u64 qcom_scmi_algo_str[] =3D { + 0x4d454d4c4154ULL, /* "MEMLAT" */ +}; + +static bool qcom_scmi_algo_str_valid(u64 algo_str) +{ + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(qcom_scmi_algo_str); i++) + if (algo_str =3D=3D qcom_scmi_algo_str[i]) + return true; + + return false; +} + +static int qcom_scmi_common_xfer(const struct scmi_protocol_handle *ph, + enum qcom_generic_ext_protocol_cmd cmd_id, void *buf, + size_t buf_len, u64 algo_str, u32 param_id, size_t rx_size) +{ + struct scmi_xfer *t; + struct qcom_scmi_msg *msg; + int ret; + + if (!qcom_scmi_algo_str_valid(algo_str)) + return -EINVAL; + + /* Reject calls where rx_size exceeds buf_len. */ + if (rx_size > buf_len) + return -EINVAL; + + ret =3D ph->xops->xfer_get_init(ph, cmd_id, buf_len + sizeof(*msg), rx_si= ze, &t); + if (ret) + return ret; + + msg =3D t->tx.buf; + msg->ext_id =3D 0; + msg->algo_low =3D cpu_to_le32(lower_32_bits(algo_str)); + msg->algo_high =3D cpu_to_le32(upper_32_bits(algo_str)); + msg->param_id =3D cpu_to_le32(param_id); + if (buf_len) + memcpy(msg->buf, buf, buf_len); + + ret =3D ph->xops->do_xfer(ph, t); + if (!ret && rx_size) { + /* + * The response is returned into the caller's @buf, replacing + * the tx payload. Bound the copy to the caller's buffer since + * t->rx.len is reported by the firmware, and require at least + * the expected rx_size so the caller never reads stale tx data. + */ + if (t->rx.len < rx_size || t->rx.len > buf_len) + ret =3D -EPROTO; + else + memcpy(buf, t->rx.buf, rx_size); + } + ph->xops->xfer_put(ph, t); + + return ret; +} + +static int qcom_scmi_set_param(const struct scmi_protocol_handle *ph, void= *buf, size_t buf_len, + u64 algo_str, u32 param_id) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_SET_PARAM, buf, buf_len, algo_= str, + param_id, 0); +} + +static int qcom_scmi_get_param(const struct scmi_protocol_handle *ph, void= *buf, size_t buf_len, + u64 algo_str, u32 param_id, size_t rx_size) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_GET_PARAM, buf, buf_len, algo_= str, + param_id, rx_size); +} + +static int qcom_scmi_start_activity(const struct scmi_protocol_handle *ph,= void *buf, + size_t buf_len, u64 algo_str, u32 param_id) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_START_ACTIVITY, buf, buf_len, = algo_str, + param_id, 0); +} + +static int qcom_scmi_stop_activity(const struct scmi_protocol_handle *ph, = void *buf, + size_t buf_len, u64 algo_str, u32 param_id) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_STOP_ACTIVITY, buf, buf_len, a= lgo_str, + param_id, 0); +} + +static const struct qcom_generic_ext_ops qcom_proto_ops =3D { + .set_param =3D qcom_scmi_set_param, + .get_param =3D qcom_scmi_get_param, + .start_activity =3D qcom_scmi_start_activity, + .stop_activity =3D qcom_scmi_stop_activity, +}; + +static int qcom_generic_ext_protocol_init(const struct scmi_protocol_handl= e *ph) +{ + dev_dbg(ph->dev, "QCOM Generic Vendor Version %d.%d\n", + PROTOCOL_REV_MAJOR(ph->version), PROTOCOL_REV_MINOR(ph->version)); + + return 0; +} + +static const struct scmi_protocol qcom_generic_ext =3D { + .id =3D SCMI_PROTOCOL_QCOM_GENERIC, + .owner =3D THIS_MODULE, + .instance_init =3D &qcom_generic_ext_protocol_init, + .ops =3D &qcom_proto_ops, + .vendor_id =3D "Qualcomm", + .supported_version =3D 0x10000, +}; +module_scmi_protocol(qcom_generic_ext); + +MODULE_ALIAS("scmi-protocol-" __stringify(SCMI_PROTOCOL_QCOM_GENERIC) "-Qu= alcomm"); +MODULE_AUTHOR("Pragnesh Papaniya "); +MODULE_AUTHOR("Sibi Sankar "); +MODULE_DESCRIPTION("QCOM SCMI Generic Vendor Protocol"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/scmi_qcom_protocol.h b/include/linux/scmi_qcom_p= rotocol.h new file mode 100644 index 000000000000..41632ee7bbc7 --- /dev/null +++ b/include/linux/scmi_qcom_protocol.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SCMI Message Protocol driver QCOM extension header + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _LINUX_SCMI_QCOM_PROTOCOL_H +#define _LINUX_SCMI_QCOM_PROTOCOL_H + +#include + +#define SCMI_PROTOCOL_QCOM_GENERIC 0x80 + +struct scmi_protocol_handle; + +/** + * struct qcom_generic_ext_ops - represents the various operations provided + * by QCOM Generic Vendor Protocol + * + * @set_param: set parameter specified by param_id and algo_str pair. + * @get_param: retrieve parameter specified by param_id and algo_str pair. + * @start_activity: initiate a specific activity defined by algo_str. + * @stop_activity: halt previously initiated activity defined by algo_str. + */ +struct qcom_generic_ext_ops { + int (*set_param)(const struct scmi_protocol_handle *ph, void *buf, size_t= buf_len, + u64 algo_str, u32 param_id); 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf8efe3afbsm45993805ad.33.2026.07.24.00.19.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 00:19:10 -0700 (PDT) From: Pragnesh Papaniya Date: Fri, 24 Jul 2026 12:48:09 +0530 Subject: [PATCH RFC 04/10] PM / devfreq: Add new target_freq attribute flag for governors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-rfc_v8_scmi_memlat-v1-4-cb732bcff1f4@oss.qualcomm.com> References: <20260724-rfc_v8_scmi_memlat-v1-0-cb732bcff1f4@oss.qualcomm.com> In-Reply-To: <20260724-rfc_v8_scmi_memlat-v1-0-cb732bcff1f4@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784877514; l=7716; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=9zK8epQvNbuVk1OIit8CUMNNYQlt7Ism/my5pJtwFUk=; b=nOAw4COlo3kTot+tWkInoVAG4WMWOoJMrZMVGgHNvYlBa1wuSNNnr7Bt15tb0fp2L8/rUxg/o dcNHgIULXzuAkC6FA9umZi+IFucLk0uDWz6TFs4cvfmPfaNyoi36lFN X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDA2NSBTYWx0ZWRfX76v5zmCX/8ax Yb7ay4S0reI7ULjgckGh+6hDaJU935Y1PuRETrSQIFwG3jRAQ6yCtBUpcJyXhkPV/TptiPXv2v4 CRZihMElgYzbAOYSk+Zb1GD+G3lDPkU= X-Authority-Analysis: v=2.4 cv=BIODalQG c=1 sm=1 tr=0 ts=6a6311f2 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=hD80L64hAAAA:8 a=WcTcrbn6WVXM4q_icv8A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: ncW9zGAMwy-dTHGLdQZM4EnBmk6yeC4L X-Proofpoint-GUID: ncW9zGAMwy-dTHGLdQZM4EnBmk6yeC4L X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDA2NSBTYWx0ZWRfX09bSfp+UQNm4 RbscNo5BrLNrtmKpaskZGB9iyg+Zmin99R82/ewswMtHFlylFZ0BeJzGskN2+mBwhKAadKs/QUE 9mlTjDFFYFUIfV6Q8mbbMSzDPn3gUegBJxOVlAu4ThAyTxt6n9BJFzgeLYYGfecv3UJFr3eJV8P vPFPcvMWk50UM0R8Lfkv+ItJmvIHcipEZaMeYYBNPIf9ThNUGBeA+d93pJK8ZaJ4GdXvsFdg47S k73MIE/srEll5ZAh2rafYom1cNk9kyYQd3laYWeNz42WJlt41KJPN341drxBt9mYu9Yk/Rm3tSA K2awQE/ywTak3K0iU7+MYS7jVIl/swanluwSIHJZ6zEdahb2HpWOw083tTamwsrX/KFXdvJNAPq gEyMuLvIktW6puBJrPgpYUxgiFkBlKWQ1b5GaAjPUp2x+wOOEI1f5t12q6aF5hKT1l06ZLtHWng fQ/WtK+KyewkDsq9bZQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_01,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240065 From: Sibi Sankar The target_freq sysfs attribute exposes a governor's predicted next target frequency. Not every devfreq governor has a meaningful value to report there; some merely observe an externally-driven device. Add a DEVFREQ_GOV_ATTR_TARGET_FREQ attribute flag that governors with a meaningful target frequency must opt in to. Gate the existing target_freq sysfs read on the flag and return -EINVAL when the active governor does not advertise it. Tag all in-tree governors so visible behaviour stays unchanged for in-tree users. Out-of-tree governors that drive frequency updates and want to keep target_freq readable need to set the new flag. Signed-off-by: Sibi Sankar Co-developed-by: Pragnesh Papaniya Signed-off-by: Pragnesh Papaniya --- Documentation/ABI/testing/sysfs-class-devfreq | 8 ++++++++ drivers/devfreq/devfreq.c | 6 ++++++ drivers/devfreq/governor_passive.c | 1 + drivers/devfreq/governor_performance.c | 1 + drivers/devfreq/governor_powersave.c | 1 + drivers/devfreq/governor_simpleondemand.c | 1 + drivers/devfreq/governor_userspace.c | 1 + drivers/devfreq/hisi_uncore_freq.c | 1 + drivers/devfreq/tegra30-devfreq.c | 3 ++- include/linux/devfreq-governor.h | 3 +++ 10 files changed, 25 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-class-devfreq b/Documentation/= ABI/testing/sysfs-class-devfreq index df8ba88b9f6a..5be9940a5853 100644 --- a/Documentation/ABI/testing/sysfs-class-devfreq +++ b/Documentation/ABI/testing/sysfs-class-devfreq @@ -37,6 +37,14 @@ Description: The /sys/class/devfreq/.../target_freq shows the next governor predicted target frequency of the corresponding devfreq object. =20 + Reading this attribute returns -EINVAL when the active + governor does not advertise DEVFREQ_GOV_ATTR_TARGET_FREQ. + All in-tree governors that drive frequency transitions tag + this attribute, so existing in-tree behaviour is unchanged. + Out-of-tree governors that previously relied on the + unconditional read of df->previous_freq must opt in by + setting DEVFREQ_GOV_ATTR_TARGET_FREQ in their attrs field. + What: /sys/class/devfreq/.../trans_stat Date: October 2012 Contact: MyungJoo Ham diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index f08fc6966eae..2f27a239e34a 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -1530,6 +1530,12 @@ static ssize_t target_freq_show(struct device *dev, { struct devfreq *df =3D to_devfreq(dev); =20 + guard(mutex)(&devfreq_list_lock); + + if (!df->profile || !df->governor || + !IS_SUPPORTED_ATTR(df->governor->attrs, TARGET_FREQ)) + return -EINVAL; + return sprintf(buf, "%lu\n", df->previous_freq); } static DEVICE_ATTR_RO(target_freq); diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_= passive.c index d7feecd900f1..b75e4bbee4b1 100644 --- a/drivers/devfreq/governor_passive.c +++ b/drivers/devfreq/governor_passive.c @@ -448,6 +448,7 @@ static int devfreq_passive_event_handler(struct devfreq= *devfreq, =20 static struct devfreq_governor devfreq_passive =3D { .name =3D DEVFREQ_GOV_PASSIVE, + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .flags =3D DEVFREQ_GOV_FLAG_IMMUTABLE, .get_target_freq =3D devfreq_passive_get_target_freq, .event_handler =3D devfreq_passive_event_handler, diff --git a/drivers/devfreq/governor_performance.c b/drivers/devfreq/gover= nor_performance.c index fdb22bf512cf..b9ec587f582c 100644 --- a/drivers/devfreq/governor_performance.c +++ b/drivers/devfreq/governor_performance.c @@ -37,6 +37,7 @@ static int devfreq_performance_handler(struct devfreq *de= vfreq, =20 static struct devfreq_governor devfreq_performance =3D { .name =3D DEVFREQ_GOV_PERFORMANCE, + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .get_target_freq =3D devfreq_performance_func, .event_handler =3D devfreq_performance_handler, }; diff --git a/drivers/devfreq/governor_powersave.c b/drivers/devfreq/governo= r_powersave.c index ee2d6ec8a512..69eab1d0a7fc 100644 --- a/drivers/devfreq/governor_powersave.c +++ b/drivers/devfreq/governor_powersave.c @@ -37,6 +37,7 @@ static int devfreq_powersave_handler(struct devfreq *devf= req, =20 static struct devfreq_governor devfreq_powersave =3D { .name =3D DEVFREQ_GOV_POWERSAVE, + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .get_target_freq =3D devfreq_powersave_func, .event_handler =3D devfreq_powersave_handler, }; diff --git a/drivers/devfreq/governor_simpleondemand.c b/drivers/devfreq/go= vernor_simpleondemand.c index ac9c5e9e51a4..65ff9d912ef9 100644 --- a/drivers/devfreq/governor_simpleondemand.c +++ b/drivers/devfreq/governor_simpleondemand.c @@ -118,6 +118,7 @@ static int devfreq_simple_ondemand_handler(struct devfr= eq *devfreq, static struct devfreq_governor devfreq_simple_ondemand =3D { .name =3D DEVFREQ_GOV_SIMPLE_ONDEMAND, .attrs =3D DEVFREQ_GOV_ATTR_POLLING_INTERVAL + | DEVFREQ_GOV_ATTR_TARGET_FREQ | DEVFREQ_GOV_ATTR_TIMER, .get_target_freq =3D devfreq_simple_ondemand_func, .event_handler =3D devfreq_simple_ondemand_handler, diff --git a/drivers/devfreq/governor_userspace.c b/drivers/devfreq/governo= r_userspace.c index 3906ebedbae8..d1b765a7b8e5 100644 --- a/drivers/devfreq/governor_userspace.c +++ b/drivers/devfreq/governor_userspace.c @@ -135,6 +135,7 @@ static int devfreq_userspace_handler(struct devfreq *de= vfreq, =20 static struct devfreq_governor devfreq_userspace =3D { .name =3D DEVFREQ_GOV_USERSPACE, + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .get_target_freq =3D devfreq_userspace_func, .event_handler =3D devfreq_userspace_handler, }; diff --git a/drivers/devfreq/hisi_uncore_freq.c b/drivers/devfreq/hisi_unco= re_freq.c index e1f64b723082..5a2d7e011ad1 100644 --- a/drivers/devfreq/hisi_uncore_freq.c +++ b/drivers/devfreq/hisi_uncore_freq.c @@ -398,6 +398,7 @@ static struct devfreq_governor hisi_platform_governor = =3D { * Set interrupt_driven to skip the devfreq monitor mechanism, though * this governor is not interrupt-driven. */ + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .flags =3D DEVFREQ_GOV_FLAG_IRQ_DRIVEN, .get_target_freq =3D hisi_platform_gov_func, .event_handler =3D hisi_platform_gov_handler, diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-de= vfreq.c index 401aac6a9f07..fcb278c4a74c 100644 --- a/drivers/devfreq/tegra30-devfreq.c +++ b/drivers/devfreq/tegra30-devfreq.c @@ -776,7 +776,8 @@ static int tegra_governor_event_handler(struct devfreq = *devfreq, =20 static struct devfreq_governor tegra_devfreq_governor =3D { .name =3D "tegra_actmon", - .attrs =3D DEVFREQ_GOV_ATTR_POLLING_INTERVAL, + .attrs =3D DEVFREQ_GOV_ATTR_POLLING_INTERVAL + | DEVFREQ_GOV_ATTR_TARGET_FREQ, .flags =3D DEVFREQ_GOV_FLAG_IMMUTABLE | DEVFREQ_GOV_FLAG_IRQ_DRIVEN, .get_target_freq =3D tegra_governor_get_target, diff --git a/include/linux/devfreq-governor.h b/include/linux/devfreq-gover= nor.h index dfdd0160a29f..2853f571dfdf 100644 --- a/include/linux/devfreq-governor.h +++ b/include/linux/devfreq-governor.h @@ -43,9 +43,12 @@ * : Indicate polling_interval sysfs attribute * - DEVFREQ_GOV_ATTR_TIMER * : Indicate timer sysfs attribute + * - DEVFREQ_GOV_ATTR_TARGET_FREQ + * : Indicate the target freq sysfs attribute */ #define DEVFREQ_GOV_ATTR_POLLING_INTERVAL BIT(0) #define DEVFREQ_GOV_ATTR_TIMER BIT(1) +#define DEVFREQ_GOV_ATTR_TARGET_FREQ BIT(2) =20 /** * struct devfreq_governor - Devfreq policy governor --=20 2.34.1 From nobody Fri Jul 24 21:54:50 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A8A13A960A for ; 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In such cases, the device's frequency is already updated by an external entity and devfreq only needs to keep its transition statistics and notifier subscribers in sync. Add a new DEVFREQ_GOV_FLAG_TRACK_REMOTE governor flag. When set, devfreq_set_target() skips the profile->target() update sequence but still emits the DEVFREQ_PRECHANGE/DEVFREQ_POSTCHANGE notification pair and the devfreq_frequency trace event, so transition-notifier subscribers (passive governor, devfreq cooling, etc.) and tracing observe the remote frequency change exactly as they would on the normal path, and the transition statistics are refreshed. Signed-off-by: Sibi Sankar Co-developed-by: Pragnesh Papaniya Signed-off-by: Pragnesh Papaniya --- drivers/devfreq/devfreq.c | 21 +++++++++++++++++++++ include/linux/devfreq-governor.h | 5 +++++ 2 files changed, 26 insertions(+) diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index 2f27a239e34a..71c6ced9e4e1 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -348,6 +348,26 @@ static int devfreq_set_target(struct devfreq *devfreq,= unsigned long new_freq, unsigned long cur_freq; int err =3D 0; =20 + /* + * When a remote agent (e.g. firmware) owns the frequency, skip the + * local profile->target() call. Still emit the PRECHANGE/POSTCHANGE + * pair and the trace event so that transition-notifier subscribers + * (passive governor, devfreq cooling, etc.) and tracing observe the + * frequency change exactly as they would on the normal path. + */ + if (devfreq->governor && + IS_SUPPORTED_FLAG(devfreq->governor->flags, TRACK_REMOTE)) { + freqs.old =3D devfreq->previous_freq; + freqs.new =3D new_freq; + devfreq_notify_transition(devfreq, &freqs, DEVFREQ_PRECHANGE); + + if (trace_devfreq_frequency_enabled() && new_freq !=3D freqs.old) + trace_devfreq_frequency(devfreq, new_freq, freqs.old); + + devfreq_notify_transition(devfreq, &freqs, DEVFREQ_POSTCHANGE); + goto update_status; + } + if (devfreq->profile->get_cur_freq) devfreq->profile->get_cur_freq(devfreq->dev.parent, &cur_freq); else @@ -375,6 +395,7 @@ static int devfreq_set_target(struct devfreq *devfreq, = unsigned long new_freq, freqs.new =3D new_freq; devfreq_notify_transition(devfreq, &freqs, DEVFREQ_POSTCHANGE); =20 +update_status: if (devfreq_update_status(devfreq, new_freq)) dev_warn(&devfreq->dev, "Couldn't update frequency transition information.\n"); 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf8efe3afbsm45993805ad.33.2026.07.24.00.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 00:19:24 -0700 (PDT) From: Pragnesh Papaniya Date: Fri, 24 Jul 2026 12:48:11 +0530 Subject: [PATCH RFC 06/10] PM / devfreq: Add a governor for tracking remote device frequencies Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-rfc_v8_scmi_memlat-v1-6-cb732bcff1f4@oss.qualcomm.com> References: <20260724-rfc_v8_scmi_memlat-v1-0-cb732bcff1f4@oss.qualcomm.com> In-Reply-To: <20260724-rfc_v8_scmi_memlat-v1-0-cb732bcff1f4@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784877514; l=4891; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=L8aBIKJ/12pti7dx2J+q6kxEAWTDwCr7YwrZkrU6k3w=; b=Y5gFfN+ZHt6er8WmQ7b2LGb0q+kTmPmMG2zPz1wNRuU6UxgxdScnYk4GdWAZ1cSBYGPD+eAW4 mArChceiY2CD8MwjYsCRzLmtYshCpoqnm7Xx8Cksh4k8H6zTmEGi2U/ X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDA2NSBTYWx0ZWRfXzfTG0bo3ZRYt UgY66BHIKUK/USupQheUANf0AyqS0c9psMz4j0XQNDTC4B8e/uBco1oBDuyK5HYPbSiKRZpIIZH a4r97fjVLHNmRU6ewVJkcMqNwpi1K2A= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDA2NSBTYWx0ZWRfX0s67D/g6IZ+6 9vt+Lfn68mJCBCCp2ci8EVwHnbu/1wwgOJ6QT3fTQJosLxoXf7Nt8Q7tnb6Hdw+lpFDg/7omqMN aDlRW9hR1YDelWYX0Mgzo7YwSJyx+HZXzIny5dUuBD19jQaejrIzzzyyXyBrcUY7FZ2Dx8gLURF mpk7K+u+W0tdfAHaZNnIbEuLpYJSPNcxFuy77sgpr78Y5tRV6nsVsKKGh6exY+T5W2cCV7Vm/+y C2Od+F15LTj5ElBM2Wl7og4LbAm2t1N/wHldQfvoBISodqf080/wbsTiZtpvA5j45diVwc2Mhre 4FnQU9deM38Z7cbiCHTIFedd5GPqye8ukzTmEhGXonb0ONAykUiUpWDYIpbQS4t1B7fEk5dAh6F Wrx4tN8KzCSX7EAUIw0/EBHCHXIiyN9zjmWm8B50ITXTKmLRpYRbdLkKV0mNrOIG5/+o6SfuXgn tfq3xDybxF+vL4utZcA== X-Authority-Analysis: v=2.4 cv=Z9Dc2nRA c=1 sm=1 tr=0 ts=6a6311fe cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=DkxomDJNIKAFLi0tgcIA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: Rtysplubr6zTRi-BuTTKJ-aVlFybMd3_ X-Proofpoint-ORIG-GUID: Rtysplubr6zTRi-BuTTKJ-aVlFybMd3_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_01,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240065 From: Sibi Sankar On SoCs where the governor and the mechanism to control the frequency for devices like caches is hosted on the System Control Processor (SCP), there exists a need to track the frequency changes in a reliable way and provide ways to tweak parameters on the remote governor. Add a new "remote" devfreq governor that uses the track_remote flag to expose the remote device's frequency to userspace via trans_stat. The governor deliberately does not advertise the DEVFREQ_GOV_ATTR_TARGET_FREQ attribute since the kernel cannot set the frequency on a remote-managed device; reads of the target_freq sysfs node therefore return -EINVAL. Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya --- drivers/devfreq/Kconfig | 8 +++++ drivers/devfreq/Makefile | 1 + drivers/devfreq/governor_remote.c | 73 +++++++++++++++++++++++++++++++++++= ++++ include/linux/devfreq.h | 1 + 4 files changed, 83 insertions(+) diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index c999c4a1e567..2caa87554914 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -56,6 +56,14 @@ config DEVFREQ_GOV_POWERSAVE the DEVFREQ framework returns the lowest frequency available at any time. =20 +config DEVFREQ_GOV_REMOTE + tristate "Remote" + help + A simple governor to track the frequency of devices whose + dvfs control lies outside the kernel. This governor acts + as an observer and provides for ways to track frequency and + set/get information related to the remote dvfs device. + config DEVFREQ_GOV_USERSPACE tristate "Userspace" help diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 404179d79a9d..cde57c8cda76 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PM_DEVFREQ_EVENT) +=3D devfreq-event.o obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) +=3D governor_simpleondemand.o obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) +=3D governor_performance.o obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) +=3D governor_powersave.o +obj-$(CONFIG_DEVFREQ_GOV_REMOTE) +=3D governor_remote.o obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) +=3D governor_userspace.o obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=3D governor_passive.o =20 diff --git a/drivers/devfreq/governor_remote.c b/drivers/devfreq/governor_r= emote.c new file mode 100644 index 000000000000..df3819757e56 --- /dev/null +++ b/drivers/devfreq/governor_remote.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +static int devfreq_remote_track_func(struct devfreq *devfreq, unsigned lon= g *freq) +{ + if (!devfreq->profile->get_cur_freq) + return -ENXIO; + + return devfreq->profile->get_cur_freq(devfreq->dev.parent, freq); +} + +static int devfreq_remote_track_handler(struct devfreq *devfreq, unsigned = int event, void *data) +{ + switch (event) { + case DEVFREQ_GOV_START: + devfreq_monitor_start(devfreq); + break; + + case DEVFREQ_GOV_STOP: + devfreq_monitor_stop(devfreq); + break; + + case DEVFREQ_GOV_UPDATE_INTERVAL: + devfreq_update_interval(devfreq, (unsigned int *)data); + break; + + case DEVFREQ_GOV_SUSPEND: + devfreq_monitor_suspend(devfreq); + break; + + case DEVFREQ_GOV_RESUME: + devfreq_monitor_resume(devfreq); + break; + } + + return 0; +} + +static struct devfreq_governor devfreq_remote_track =3D { + .name =3D DEVFREQ_GOV_REMOTE, + .attrs =3D DEVFREQ_GOV_ATTR_POLLING_INTERVAL + | DEVFREQ_GOV_ATTR_TIMER, + .flags =3D DEVFREQ_GOV_FLAG_IMMUTABLE + | DEVFREQ_GOV_FLAG_TRACK_REMOTE, + .get_target_freq =3D devfreq_remote_track_func, + .event_handler =3D devfreq_remote_track_handler, +}; + +static int __init devfreq_remote_track_init(void) +{ + return devfreq_add_governor(&devfreq_remote_track); +} +subsys_initcall(devfreq_remote_track_init); + +static void __exit devfreq_remote_track_exit(void) +{ + int ret; + + ret =3D devfreq_remove_governor(&devfreq_remote_track); + if (ret) + pr_err("%s: failed to remove governor %d\n", __func__, ret); +} +module_exit(devfreq_remote_track_exit); + +MODULE_DESCRIPTION("DEVFREQ Remote Tracking governor"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h index dc1075dc3446..4d50cf230950 100644 --- a/include/linux/devfreq.h +++ b/include/linux/devfreq.h @@ -21,6 +21,7 @@ #define DEVFREQ_GOV_POWERSAVE "powersave" #define DEVFREQ_GOV_USERSPACE "userspace" #define DEVFREQ_GOV_PASSIVE "passive" +#define DEVFREQ_GOV_REMOTE "remote" =20 /* DEVFREQ notifier interface */ #define DEVFREQ_TRANSITION_NOTIFIER (0) --=20 2.34.1 From nobody Fri Jul 24 21:54:50 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B1823A9D8F for ; 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Every sampling window the CPUCP reads the per-CPU PMU counters, derives its statistics (instructions-per-miss, back-end stall), maps them to a target operating point for the DDR, LLCC and DDR_QOS buses and votes it directly to the interconnect. The kernel is never in that runtime decision loop; the CPUCP algorithm and its controls are reached through the QCOM SCMI Generic Extension Protocol, addressed via the "MEMLAT" algorithm string. Introduce a devfreq SCMI client driver whose role is split in two. At probe it configures the CPUCP algorithm once (event maps, per-monitor tuneables, the cpufreq-to-memfreq maps and min/max clamps) and starts it; this half is required, as without it the CPUCP has no per-SoC data to run the algorithm. Thereafter the driver only reads back the current operating point. Each bus is modelled as a devfreq device and uses the remote devfreq governor precisely for this "observe a frequency someone else drives" case: it exposes the read-back through trans_stat and lets userspace retune the remote governor's parameters. Co-developed-by: Amir Vajid Signed-off-by: Amir Vajid Co-developed-by: Ramakrishna Gottimukkula Signed-off-by: Ramakrishna Gottimukkula Signed-off-by: Sibi Sankar Co-developed-by: Pragnesh Papaniya Signed-off-by: Pragnesh Papaniya --- MAINTAINERS | 8 + drivers/devfreq/Kconfig | 15 + drivers/devfreq/Makefile | 1 + drivers/devfreq/scmi-qcom-memlat-devfreq.c | 1331 ++++++++++++++++++++++++= ++++ 4 files changed, 1355 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 265eb99bdc7a..a58e2219d5df 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22495,6 +22495,14 @@ F: Documentation/networking/device_drivers/cellula= r/qualcomm/rmnet.rst F: drivers/net/ethernet/qualcomm/rmnet/ F: include/linux/if_rmnet.h =20 +QUALCOMM SCMI MEMLAT DEVFREQ DRIVER +M: Pragnesh Papaniya +M: Sibi Sankar +L: linux-arm-msm@vger.kernel.org +L: linux-pm@vger.kernel.org +S: Maintained +F: drivers/devfreq/scmi-qcom-memlat-devfreq.c + QUALCOMM TEE (QCOMTEE) DRIVER M: Amirreza Zarrabi L: linux-arm-msm@vger.kernel.org diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 2caa87554914..fdf6484fc72c 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -169,6 +169,21 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ This adds the DEVFREQ driver for the MBUS controller in some Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs. =20 +config SCMI_QCOM_MEMLAT_DEVFREQ + tristate "Qualcomm SCMI memory latency (memlat) devfreq driver" + depends on QCOM_SCMI_GENERIC_EXT || COMPILE_TEST + select DEVFREQ_GOV_REMOTE + help + Enable memory-bus (DDR/LLCC/DDR_QOS) scaling on Qualcomm Glymur, + X1E/X1P-class and Kaanapali SoCs. The scaling algorithm itself runs + autonomously on the CPU Control Processor (CPUCP); this driver only + configures and starts it at boot and then exposes each bus as a + devfreq device so its operating point is visible via trans_stat and + tunable from userspace. + + Nothing else needs to be enabled for the scaling to take effect. Say Y + or M here on the affected Qualcomm SoCs; otherwise say N. + source "drivers/devfreq/event/Kconfig" =20 endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index cde57c8cda76..b11f94e2f485 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) +=3D mtk-cci-devfr= eq.o obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) +=3D rk3399_dmc.o obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) +=3D sun8i-a33-mbus.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) +=3D tegra30-devfreq.o +obj-$(CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ) +=3D scmi-qcom-memlat-devfreq.o =20 # DEVFREQ Event Drivers obj-$(CONFIG_PM_DEVFREQ_EVENT) +=3D event/ diff --git a/drivers/devfreq/scmi-qcom-memlat-devfreq.c b/drivers/devfreq/s= cmi-qcom-memlat-devfreq.c new file mode 100644 index 000000000000..9ca85b2f4c1a --- /dev/null +++ b/drivers/devfreq/scmi-qcom-memlat-devfreq.c @@ -0,0 +1,1331 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* CPUCP AMU event indices programmed into the common/group event maps. */ +#define MEMLAT_EV_CPU_CYCLES 0 +#define MEMLAT_EV_CNT_CYCLES 1 +#define MEMLAT_EV_INST_RETIRED 2 +#define MEMLAT_EV_STALL_BACKEND_MEM 3 +#define MEMLAT_EV_L2_D_RFILL 5 + +/* Sentinel for an event slot that is not wired to any AMU counter. */ +#define MEMLAT_INVALID_IDX 0xff + +/* hw_type value that targets every group (common events are not group-sco= ped). */ +#define MEMLAT_HW_TYPE_ALL 0xff + +#define MEMLAT_ALGO_STR 0x4d454d4c4154ULL /* "MEMLAT" */ + +/** + * struct scmi_qcom_map_table - one row of a monitor's cpufreq->memfreq map + * @cpu_freq_mhz: CPU frequency threshold, in MHz. When the monitor's busi= est + * CPU is at or above this frequency, the firmware votes the + * paired memory frequency. + * @mem_freq_mhz: memory frequency to vote, in MHz (a 0/1 level for DDR_QO= S). + */ +struct scmi_qcom_map_table { + unsigned int cpu_freq_mhz; + unsigned int mem_freq_mhz; +}; + +struct scmi_qcom_opp_data { + u64 freq; +}; + +struct scmi_qcom_memory_range { + unsigned int min_freq_khz; + unsigned int max_freq_khz; +}; + +enum common_ev_idx { + INST_IDX, + CYC_IDX, + CONST_CYC_IDX, + FE_STALL_IDX, + BE_STALL_IDX, + NUM_COMMON_EVS +}; + +enum grp_ev_idx { + MISS_IDX, + WB_IDX, + ACC_IDX, + NUM_GRP_EVS +}; + +/* + * hw_type identifiers for the memory buses. These are a firmware-defined + * encoding carried in the node/scalar/map/ev messages; the driver only + * mirrors them here. + */ +enum scmi_qcom_memlat_hw_type { + MEMLAT_HW_DDR =3D 0, + MEMLAT_HW_LLCC =3D 1, + MEMLAT_HW_DDR_QOS_COMPUTE =3D 2, + MEMLAT_HW_DDR_QOS_MOBILE =3D 3, +}; + +/** + * struct scmi_qcom_monitor_cfg - per-monitor firmware tuneables + * @table: cpufreq->memfreq voting map for this monitor. + * @name: monitor name, forwarded to the firmware and used in its log line= s. + * @be_stall_floor: back-end-stall gating threshold, in percent. Each samp= le + * window the firmware computes a per-CPU back-end-stall + * percentage (stall cycles / total cycles); a CPU only + * contributes its frequency vote to this monitor when th= at + * percentage is at or above @be_stall_floor. A value of 1 + * therefore means "any stall counts", i.e. the CPU is + * effectively always eligible. + * @cpu_mask: bitmask of CPUs whose counters this monitor aggregates. + * @ipm_ceil: instructions-per-miss ceiling. A CPU is treated as + * memory-latency-bound (and eligible to vote) only when its IP= M is + * at or below this ceiling; a monitor with @ipm_ceil =3D=3D 0 = is a + * "compute" monitor and scales passively with cpufreq. + * @table_len: number of valid rows in @table. + */ +struct scmi_qcom_monitor_cfg { + const struct scmi_qcom_map_table *table; + const char *name; + u32 be_stall_floor; + u32 cpu_mask; + u32 ipm_ceil; + u32 table_len; +}; + +struct scmi_qcom_memory_cfg { + const struct scmi_qcom_monitor_cfg *monitor_cfg; + const struct scmi_qcom_opp_data *mem_table; + struct scmi_qcom_memory_range memory_range; + const u32 *grp_ev; + const char *name; + enum scmi_qcom_memlat_hw_type memory_type; + u32 monitor_cnt; + u32 num_opps; +}; + +struct scmi_qcom_memlat_cfg_data { + const struct scmi_qcom_memory_cfg *memory_cfg; + const u32 *common_ev; + bool cpucp_legacy_freq_method; + u32 cpucp_sample_ms; + u32 memory_cnt; +}; + +#define MEMLAT_MAX_NAME_LEN 20 +#define MEMLAT_MAX_MAP_ENTRIES 10 + +/* + * param_ids of the "MEMLAT" algo_str hosted by the Qualcomm Generic Vendor + * Protocol. MEMLAT detects memory-latency-bound workloads and scales the + * memory buses accordingly; these are the fixed wire-protocol tokens that + * the firmware matches. + * + * MEMLAT_SET_MEM_GROUP: initializes the frequency/level scaling functions= for the memory bus. + * MEMLAT_SET_MONITOR: configures the monitor to work on a specific memory= bus. + * MEMLAT_SET_COMMON_EV_MAP: set up common counters used to monitor the cp= u frequency. + * MEMLAT_SET_GRP_EV_MAP: set up any specific counters used to monitor the= memory bus. + * MEMLAT_ADAPTIVE_LOW_FREQ: set the adaptive low frequency floor of the m= emory bus. + * MEMLAT_ADAPTIVE_HIGH_FREQ: set the adaptive high frequency floor of the= memory bus. + * MEMLAT_GET_ADAPTIVE_CUR_FREQ: query the current adaptive frequency of t= he memory bus. + * MEMLAT_IPM_CEIL: set the IPM (Instruction Per Misses) ceiling per monit= or. + * MEMLAT_FE_STALL_FLOOR: set the front-end stall floor per monitor. + * MEMLAT_BE_STALL_FLOOR: set the back-end stall floor per monitor. + * MEMLAT_WB_PCT: set the write-back percentage threshold per monitor. + * MEMLAT_IPM_FILTER: set the IPM filter used to reject non-latency sample= s per monitor. + * MEMLAT_FREQ_SCALE_PCT: set the frequency scaling percentage per monitor. + * MEMLAT_FREQ_SCALE_CEIL_MHZ: set the cpu frequency ceiling for scaling p= er monitor. + * MEMLAT_FREQ_SCALE_FLOOR_MHZ: set the cpu frequency floor for scaling pe= r monitor. + * MEMLAT_SAMPLE_MS: set the sampling period for all the monitors. + * MEMLAT_MON_FREQ_MAP: setup the cpufreq to memfreq map. + * MEMLAT_SET_MIN_FREQ: set the min frequency of the memory bus. + * MEMLAT_SET_MAX_FREQ: set the max frequency of the memory bus. + * MEMLAT_GET_CUR_FREQ: query the current frequency/level of the memory bu= s. + * MEMLAT_START_TIMER: start all the monitors with the requested sampling = period. + * MEMLAT_STOP_TIMER: stop all the running monitors. + * MEMLAT_GET_TIMESTAMP: query the firmware timestamp. + * MEMLAT_SET_EFFECTIVE_FREQ_METHOD: set the method used to determine cpu = frequency. + */ +#define MEMLAT_SET_MEM_GROUP 16 +#define MEMLAT_SET_MONITOR 17 +#define MEMLAT_SET_COMMON_EV_MAP 18 +#define MEMLAT_SET_GRP_EV_MAP 19 +#define MEMLAT_ADAPTIVE_LOW_FREQ 20 +#define MEMLAT_ADAPTIVE_HIGH_FREQ 21 +#define MEMLAT_GET_ADAPTIVE_CUR_FREQ 22 +#define MEMLAT_IPM_CEIL 23 +#define MEMLAT_FE_STALL_FLOOR 24 +#define MEMLAT_BE_STALL_FLOOR 25 +#define MEMLAT_WB_PCT 26 +#define MEMLAT_IPM_FILTER 27 +#define MEMLAT_FREQ_SCALE_PCT 28 +#define MEMLAT_FREQ_SCALE_CEIL_MHZ 29 +#define MEMLAT_FREQ_SCALE_FLOOR_MHZ 30 +#define MEMLAT_SAMPLE_MS 31 +#define MEMLAT_MON_FREQ_MAP 32 +#define MEMLAT_SET_MIN_FREQ 33 +#define MEMLAT_SET_MAX_FREQ 34 +#define MEMLAT_GET_CUR_FREQ 35 +#define MEMLAT_START_TIMER 36 +#define MEMLAT_STOP_TIMER 37 +#define MEMLAT_GET_TIMESTAMP 38 +#define MEMLAT_SET_EFFECTIVE_FREQ_METHOD 39 + +struct cpucp_map_table { + __le16 cpu_freq_mhz; + __le16 mem_freq_mhz; +}; + +struct map_param_msg { + __le32 hw_type; + __le32 mon_idx; + __le32 nr_rows; + struct cpucp_map_table tbl[MEMLAT_MAX_MAP_ENTRIES]; +}; + +struct node_msg { + __le32 cpumask; + __le32 hw_type; + __le32 mon_type; + __le32 mon_idx; + char mon_name[MEMLAT_MAX_NAME_LEN]; +}; + +struct scalar_param_msg { + __le32 hw_type; + __le32 mon_idx; + __le32 val; +}; + +struct ev_map_msg { + __le32 num_evs; + __le32 hw_type; + __le32 cid[NUM_COMMON_EVS]; +}; + +/* + * MEMLAT_GET_CUR_FREQ reuses the request buffer for its response, so expr= ess + * the in/out aliasing as a union rather than reinterpreting the bytes. + */ +union cur_freq_msg { + struct scalar_param_msg req; + __le32 resp; +}; + +struct scmi_qcom_memory_info { + const struct scmi_qcom_memory_cfg *cfg; + struct devfreq_dev_profile profile; + struct devfreq *devfreq; + struct faux_device *fdev; + struct scmi_protocol_handle *ph; + const struct qcom_generic_ext_ops *ops; +}; + +struct scmi_qcom_memlat_info { + struct scmi_protocol_handle *ph; + const struct qcom_generic_ext_ops *ops; + const struct scmi_qcom_memlat_cfg_data *cfg_data; + struct scmi_qcom_memory_info **memory; + u32 memory_cnt; +}; + +/* + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + * Per-SoC configuration + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + */ + +static const u32 glymur_common_ev[NUM_COMMON_EVS] =3D { + [INST_IDX] =3D MEMLAT_EV_INST_RETIRED, + [CYC_IDX] =3D MEMLAT_EV_CPU_CYCLES, + [CONST_CYC_IDX] =3D MEMLAT_EV_CNT_CYCLES, + [FE_STALL_IDX] =3D MEMLAT_INVALID_IDX, + [BE_STALL_IDX] =3D MEMLAT_EV_STALL_BACKEND_MEM, +}; + +static const u32 glymur_ddr_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D MEMLAT_EV_L2_D_RFILL, + [WB_IDX] =3D MEMLAT_INVALID_IDX, + [ACC_IDX] =3D MEMLAT_INVALID_IDX, +}; + +static const u32 glymur_llcc_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D MEMLAT_EV_L2_D_RFILL, + [WB_IDX] =3D MEMLAT_INVALID_IDX, + [ACC_IDX] =3D MEMLAT_INVALID_IDX, +}; + +static const u32 glymur_ddr_qos_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D MEMLAT_EV_L2_D_RFILL, + [WB_IDX] =3D MEMLAT_INVALID_IDX, + [ACC_IDX] =3D MEMLAT_INVALID_IDX, +}; + +static const u32 hamoa_common_ev[NUM_COMMON_EVS] =3D { + [INST_IDX] =3D MEMLAT_EV_INST_RETIRED, + [CYC_IDX] =3D MEMLAT_EV_CPU_CYCLES, + [CONST_CYC_IDX] =3D MEMLAT_EV_CNT_CYCLES, + [FE_STALL_IDX] =3D MEMLAT_INVALID_IDX, + [BE_STALL_IDX] =3D MEMLAT_EV_STALL_BACKEND_MEM, +}; + +static const u32 hamoa_ddr_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D MEMLAT_EV_L2_D_RFILL, + [WB_IDX] =3D MEMLAT_INVALID_IDX, + [ACC_IDX] =3D MEMLAT_INVALID_IDX, +}; + +static const u32 hamoa_llcc_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D MEMLAT_EV_L2_D_RFILL, + [WB_IDX] =3D MEMLAT_INVALID_IDX, + [ACC_IDX] =3D MEMLAT_INVALID_IDX, +}; + +static const u32 hamoa_ddr_qos_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D MEMLAT_EV_L2_D_RFILL, + [WB_IDX] =3D MEMLAT_INVALID_IDX, + [ACC_IDX] =3D MEMLAT_INVALID_IDX, +}; + +static const u32 kaanapali_common_ev[NUM_COMMON_EVS] =3D { + [INST_IDX] =3D MEMLAT_EV_INST_RETIRED, + [CYC_IDX] =3D MEMLAT_EV_CPU_CYCLES, + [CONST_CYC_IDX] =3D MEMLAT_INVALID_IDX, + [FE_STALL_IDX] =3D MEMLAT_INVALID_IDX, + [BE_STALL_IDX] =3D MEMLAT_INVALID_IDX, +}; + +static const u32 kaanapali_ddr_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D MEMLAT_EV_L2_D_RFILL, + [WB_IDX] =3D MEMLAT_INVALID_IDX, + [ACC_IDX] =3D MEMLAT_INVALID_IDX, +}; + +static const u32 kaanapali_llcc_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D MEMLAT_EV_L2_D_RFILL, + [WB_IDX] =3D MEMLAT_INVALID_IDX, + [ACC_IDX] =3D MEMLAT_INVALID_IDX, +}; + +static const u32 kaanapali_ddr_qos_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D MEMLAT_EV_L2_D_RFILL, + [WB_IDX] =3D MEMLAT_INVALID_IDX, + [ACC_IDX] =3D MEMLAT_INVALID_IDX, +}; + +static const struct scmi_qcom_opp_data glymur_llcc_table[] =3D { + { .freq =3D 315000000 }, + { .freq =3D 479000000 }, + { .freq =3D 545000000 }, + { .freq =3D 725000000 }, + { .freq =3D 840000000 }, + { .freq =3D 959000000 }, + { .freq =3D 1090000000 }, + { .freq =3D 1211000000 }, +}; + +static const struct scmi_qcom_opp_data hamoa_llcc_table[] =3D { + { .freq =3D 300000000 }, + { .freq =3D 466000000 }, + { .freq =3D 600000000 }, + { .freq =3D 806000000 }, + { .freq =3D 933000000 }, + { .freq =3D 1066000000 }, +}; + +static const struct scmi_qcom_opp_data kaanapali_llcc_table[] =3D { + { .freq =3D 282000000 }, + { .freq =3D 350000000 }, + { .freq =3D 533000000 }, + { .freq =3D 605600000 }, + { .freq =3D 806000000 }, + { .freq =3D 933000000 }, + { .freq =3D 1066000000 }, + { .freq =3D 1211000000 }, + { .freq =3D 1350000000 }, +}; + +static const struct scmi_qcom_opp_data glymur_ddr_table[] =3D { + { .freq =3D 200000000 }, + { .freq =3D 547000000 }, + { .freq =3D 1353000000 }, + { .freq =3D 1555000000 }, + { .freq =3D 1708000000 }, + { .freq =3D 2092000000 }, + { .freq =3D 2736000000 }, + { .freq =3D 3187000000 }, + { .freq =3D 3686000000 }, + { .freq =3D 4224000000 }, + { .freq =3D 4761000000 }, +}; + +static const struct scmi_qcom_opp_data hamoa_ddr_table[] =3D { + { .freq =3D 200000000 }, + { .freq =3D 547000000 }, + { .freq =3D 768000000 }, + { .freq =3D 1555000000 }, + { .freq =3D 1708000000 }, + { .freq =3D 2092000000 }, + { .freq =3D 2736000000 }, + { .freq =3D 3187000000 }, + { .freq =3D 3686000000 }, + { .freq =3D 4224000000 }, +}; + +static const struct scmi_qcom_opp_data kaanapali_ddr_table[] =3D { + { .freq =3D 547000000 }, + { .freq =3D 1353000000 }, + { .freq =3D 1555000000 }, + { .freq =3D 1708000000 }, + { .freq =3D 2092000000 }, + { .freq =3D 2736000000 }, + { .freq =3D 3187000000 }, + { .freq =3D 3686000000 }, + { .freq =3D 4224000000 }, + { .freq =3D 4780000000 }, + { .freq =3D 5333000000 }, +}; + +/* + * DDR_QOS is a boolean bus: the firmware reports level 0 (nominal) or 1 + * (boost) rather than a frequency. dev_pm_opp_add_dynamic() rejects a zero + * frequency, so the two OPP entries below use 1 and 100 purely as distinc= t, + * non-zero devfreq keys for the two levels; the values are not real + * frequencies. scmi_qcom_devfreq_get_cur_freq() maps the reported level b= ack + * to the matching OPP frequency. + */ +static const struct scmi_qcom_opp_data glymur_ddr_qos_table[] =3D { + { .freq =3D 1 }, + { .freq =3D 100 }, +}; + +static const struct scmi_qcom_memory_cfg glymur_memory_cfg[] =3D { + { + .memory_type =3D MEMLAT_HW_DDR, + .name =3D "ddr", + .mem_table =3D glymur_ddr_table, + .num_opps =3D ARRAY_SIZE(glymur_ddr_table), + .grp_ev =3D glymur_ddr_grp_ev, + .monitor_cnt =3D 4, + .memory_range =3D { .min_freq_khz =3D 547000, .max_freq_khz =3D 4761000 = }, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0x3f, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 8, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 960, .mem_freq_mhz =3D 547 }, + { .cpu_freq_mhz =3D 1133, .mem_freq_mhz =3D 1353 }, + { .cpu_freq_mhz =3D 1594, .mem_freq_mhz =3D 1555 }, + { .cpu_freq_mhz =3D 1920, .mem_freq_mhz =3D 1708 }, + { .cpu_freq_mhz =3D 2228, .mem_freq_mhz =3D 2736 }, + { .cpu_freq_mhz =3D 2362, .mem_freq_mhz =3D 3187 }, + { .cpu_freq_mhz =3D 2650, .mem_freq_mhz =3D 3686 }, + { .cpu_freq_mhz =3D 2938, .mem_freq_mhz =3D 4761 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xfc0, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 8, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 356, .mem_freq_mhz =3D 547 }, + { .cpu_freq_mhz =3D 1018, .mem_freq_mhz =3D 1353 }, + { .cpu_freq_mhz =3D 1536, .mem_freq_mhz =3D 1555 }, + { .cpu_freq_mhz =3D 1748, .mem_freq_mhz =3D 1708 }, + { .cpu_freq_mhz =3D 2324, .mem_freq_mhz =3D 2736 }, + { .cpu_freq_mhz =3D 2496, .mem_freq_mhz =3D 3187 }, + { .cpu_freq_mhz =3D 2900, .mem_freq_mhz =3D 3686 }, + { .cpu_freq_mhz =3D 3514, .mem_freq_mhz =3D 4761 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0x3f000, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 8, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 356, .mem_freq_mhz =3D 547 }, + { .cpu_freq_mhz =3D 1018, .mem_freq_mhz =3D 1353 }, + { .cpu_freq_mhz =3D 1536, .mem_freq_mhz =3D 1555 }, + { .cpu_freq_mhz =3D 1748, .mem_freq_mhz =3D 1708 }, + { .cpu_freq_mhz =3D 2324, .mem_freq_mhz =3D 2736 }, + { .cpu_freq_mhz =3D 2496, .mem_freq_mhz =3D 3187 }, + { .cpu_freq_mhz =3D 2900, .mem_freq_mhz =3D 3686 }, + { .cpu_freq_mhz =3D 3514, .mem_freq_mhz =3D 4761 }, + } + }, + { + .name =3D "mon_3", + .cpu_mask =3D 0x3ffff, + .table_len =3D 4, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 2823, .mem_freq_mhz =3D 547 }, + { .cpu_freq_mhz =3D 3034, .mem_freq_mhz =3D 1555 }, + { .cpu_freq_mhz =3D 3226, .mem_freq_mhz =3D 1708 }, + { .cpu_freq_mhz =3D 5012, .mem_freq_mhz =3D 2092 }, + } + }, + }, + }, + { + .memory_type =3D MEMLAT_HW_LLCC, + .name =3D "llcc", + .mem_table =3D glymur_llcc_table, + .num_opps =3D ARRAY_SIZE(glymur_llcc_table), + .grp_ev =3D glymur_llcc_grp_ev, + .monitor_cnt =3D 3, + .memory_range =3D { .min_freq_khz =3D 315000, .max_freq_khz =3D 1211000 = }, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0x3f, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 7, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 960, .mem_freq_mhz =3D 315 }, + { .cpu_freq_mhz =3D 1113, .mem_freq_mhz =3D 479 }, + { .cpu_freq_mhz =3D 1594, .mem_freq_mhz =3D 545 }, + { .cpu_freq_mhz =3D 1920, .mem_freq_mhz =3D 725 }, + { .cpu_freq_mhz =3D 2362, .mem_freq_mhz =3D 840 }, + { .cpu_freq_mhz =3D 2650, .mem_freq_mhz =3D 959 }, + { .cpu_freq_mhz =3D 2938, .mem_freq_mhz =3D 1211 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xfc0, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 7, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 356, .mem_freq_mhz =3D 315 }, + { .cpu_freq_mhz =3D 1018, .mem_freq_mhz =3D 479 }, + { .cpu_freq_mhz =3D 1536, .mem_freq_mhz =3D 545 }, + { .cpu_freq_mhz =3D 1748, .mem_freq_mhz =3D 725 }, + { .cpu_freq_mhz =3D 2496, .mem_freq_mhz =3D 840 }, + { .cpu_freq_mhz =3D 2900, .mem_freq_mhz =3D 959 }, + { .cpu_freq_mhz =3D 3514, .mem_freq_mhz =3D 1211 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0x3f000, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 7, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 356, .mem_freq_mhz =3D 315 }, + { .cpu_freq_mhz =3D 1018, .mem_freq_mhz =3D 479 }, + { .cpu_freq_mhz =3D 1536, .mem_freq_mhz =3D 545 }, + { .cpu_freq_mhz =3D 1748, .mem_freq_mhz =3D 725 }, + { .cpu_freq_mhz =3D 2496, .mem_freq_mhz =3D 840 }, + { .cpu_freq_mhz =3D 2900, .mem_freq_mhz =3D 959 }, + { .cpu_freq_mhz =3D 3514, .mem_freq_mhz =3D 1211 }, + } + }, + }, + }, + { + .memory_type =3D MEMLAT_HW_DDR_QOS_COMPUTE, + .name =3D "ddr-qos", + .monitor_cnt =3D 3, + .mem_table =3D glymur_ddr_qos_table, + .num_opps =3D ARRAY_SIZE(glymur_ddr_qos_table), + .grp_ev =3D glymur_ddr_qos_grp_ev, + .memory_range =3D { .min_freq_khz =3D 0, .max_freq_khz =3D 1 }, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0x3f, + .ipm_ceil =3D 80000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 2362, .mem_freq_mhz =3D 0 }, + { .cpu_freq_mhz =3D 2938, .mem_freq_mhz =3D 1 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xfc0, + .ipm_ceil =3D 80000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 2496, .mem_freq_mhz =3D 0 }, + { .cpu_freq_mhz =3D 3514, .mem_freq_mhz =3D 1 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0x3f000, + .ipm_ceil =3D 80000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 2496, .mem_freq_mhz =3D 0 }, + { .cpu_freq_mhz =3D 3514, .mem_freq_mhz =3D 1 }, + } + }, + }, + }, +}; + +static const struct scmi_qcom_memory_cfg hamoa_memory_cfg[] =3D { + { + .memory_type =3D MEMLAT_HW_DDR, + .name =3D "ddr", + .mem_table =3D hamoa_ddr_table, + .num_opps =3D ARRAY_SIZE(hamoa_ddr_table), + .grp_ev =3D hamoa_ddr_grp_ev, + .monitor_cnt =3D 4, + .memory_range =3D { .min_freq_khz =3D 200000, .max_freq_khz =3D 4224000 = }, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0xf, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 999, .mem_freq_mhz =3D 547 }, + { .cpu_freq_mhz =3D 1440, .mem_freq_mhz =3D 768 }, + { .cpu_freq_mhz =3D 1671, .mem_freq_mhz =3D 1555 }, + { .cpu_freq_mhz =3D 2189, .mem_freq_mhz =3D 2092 }, + { .cpu_freq_mhz =3D 2516, .mem_freq_mhz =3D 3187 }, + { .cpu_freq_mhz =3D 3860, .mem_freq_mhz =3D 4224 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xf0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 999, .mem_freq_mhz =3D 547 }, + { .cpu_freq_mhz =3D 1440, .mem_freq_mhz =3D 768 }, + { .cpu_freq_mhz =3D 1671, .mem_freq_mhz =3D 1555 }, + { .cpu_freq_mhz =3D 2189, .mem_freq_mhz =3D 2092 }, + { .cpu_freq_mhz =3D 2516, .mem_freq_mhz =3D 3187 }, + { .cpu_freq_mhz =3D 3860, .mem_freq_mhz =3D 4224 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0xf00, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 999, .mem_freq_mhz =3D 547 }, + { .cpu_freq_mhz =3D 1440, .mem_freq_mhz =3D 768 }, + { .cpu_freq_mhz =3D 1671, .mem_freq_mhz =3D 1555 }, + { .cpu_freq_mhz =3D 2189, .mem_freq_mhz =3D 2092 }, + { .cpu_freq_mhz =3D 2516, .mem_freq_mhz =3D 3187 }, + { .cpu_freq_mhz =3D 3860, .mem_freq_mhz =3D 4224 }, + } + }, + { + .name =3D "mon_3", + .cpu_mask =3D 0xfff, + .table_len =3D 4, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 1440, .mem_freq_mhz =3D 547 }, + { .cpu_freq_mhz =3D 2189, .mem_freq_mhz =3D 768 }, + { .cpu_freq_mhz =3D 2516, .mem_freq_mhz =3D 1555 }, + { .cpu_freq_mhz =3D 3860, .mem_freq_mhz =3D 2092 }, + } + }, + }, + }, + { + .memory_type =3D MEMLAT_HW_LLCC, + .name =3D "llcc", + .mem_table =3D hamoa_llcc_table, + .num_opps =3D ARRAY_SIZE(hamoa_llcc_table), + .grp_ev =3D hamoa_llcc_grp_ev, + .monitor_cnt =3D 3, + .memory_range =3D { .min_freq_khz =3D 300000, .max_freq_khz =3D 1066000 = }, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0xf, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 999, .mem_freq_mhz =3D 300 }, + { .cpu_freq_mhz =3D 1440, .mem_freq_mhz =3D 466 }, + { .cpu_freq_mhz =3D 1671, .mem_freq_mhz =3D 600 }, + { .cpu_freq_mhz =3D 2189, .mem_freq_mhz =3D 806 }, + { .cpu_freq_mhz =3D 2516, .mem_freq_mhz =3D 933 }, + { .cpu_freq_mhz =3D 3860, .mem_freq_mhz =3D 1066 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xf0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 999, .mem_freq_mhz =3D 300 }, + { .cpu_freq_mhz =3D 1440, .mem_freq_mhz =3D 466 }, + { .cpu_freq_mhz =3D 1671, .mem_freq_mhz =3D 600 }, + { .cpu_freq_mhz =3D 2189, .mem_freq_mhz =3D 806 }, + { .cpu_freq_mhz =3D 2516, .mem_freq_mhz =3D 933 }, + { .cpu_freq_mhz =3D 3860, .mem_freq_mhz =3D 1066 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0xf00, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 999, .mem_freq_mhz =3D 300 }, + { .cpu_freq_mhz =3D 1440, .mem_freq_mhz =3D 466 }, + { .cpu_freq_mhz =3D 1671, .mem_freq_mhz =3D 600 }, + { .cpu_freq_mhz =3D 2189, .mem_freq_mhz =3D 806 }, + { .cpu_freq_mhz =3D 2516, .mem_freq_mhz =3D 933 }, + { .cpu_freq_mhz =3D 3860, .mem_freq_mhz =3D 1066 }, + } + }, + }, + }, + { + .memory_type =3D MEMLAT_HW_DDR_QOS_COMPUTE, + .name =3D "ddr-qos", + .monitor_cnt =3D 3, + .mem_table =3D glymur_ddr_qos_table, + .num_opps =3D ARRAY_SIZE(glymur_ddr_qos_table), + .grp_ev =3D hamoa_ddr_qos_grp_ev, + .memory_range =3D { .min_freq_khz =3D 0, .max_freq_khz =3D 1 }, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0xf, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 2189, .mem_freq_mhz =3D 0 }, + { .cpu_freq_mhz =3D 3860, .mem_freq_mhz =3D 1 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xf0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 2189, .mem_freq_mhz =3D 0 }, + { .cpu_freq_mhz =3D 3860, .mem_freq_mhz =3D 1 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0xf00, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 2189, .mem_freq_mhz =3D 0 }, + { .cpu_freq_mhz =3D 3860, .mem_freq_mhz =3D 1 }, + } + }, + }, + }, +}; + +static const struct scmi_qcom_memory_cfg kaanapali_memory_cfg[] =3D { + { + .memory_type =3D MEMLAT_HW_DDR, + .name =3D "ddr", + .mem_table =3D kaanapali_ddr_table, + .num_opps =3D ARRAY_SIZE(kaanapali_ddr_table), + .grp_ev =3D kaanapali_ddr_grp_ev, + .monitor_cnt =3D 4, + .memory_range =3D { .min_freq_khz =3D 547000, .max_freq_khz =3D 5333000 = }, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0x3f, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 787, .mem_freq_mhz =3D 547 }, + { .cpu_freq_mhz =3D 960, .mem_freq_mhz =3D 1353 }, + { .cpu_freq_mhz =3D 1200, .mem_freq_mhz =3D 1555 }, + { .cpu_freq_mhz =3D 1536, .mem_freq_mhz =3D 2092 }, + { .cpu_freq_mhz =3D 2534, .mem_freq_mhz =3D 3187 }, + { .cpu_freq_mhz =3D 3552, .mem_freq_mhz =3D 3686 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xc0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 8, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 614, .mem_freq_mhz =3D 547 }, + { .cpu_freq_mhz =3D 864, .mem_freq_mhz =3D 1353 }, + { .cpu_freq_mhz =3D 1382, .mem_freq_mhz =3D 2092 }, + { .cpu_freq_mhz =3D 2131, .mem_freq_mhz =3D 3187 }, + { .cpu_freq_mhz =3D 2726, .mem_freq_mhz =3D 3686 }, + { .cpu_freq_mhz =3D 3513, .mem_freq_mhz =3D 4224 }, + { .cpu_freq_mhz =3D 3916, .mem_freq_mhz =3D 4780 }, + { .cpu_freq_mhz =3D 4185, .mem_freq_mhz =3D 5333 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0xff, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 2035, .mem_freq_mhz =3D 547 }, + { .cpu_freq_mhz =3D 4185, .mem_freq_mhz =3D 2092 }, + } + }, + { + .name =3D "mon_3", + .cpu_mask =3D 0xc0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 2726, .mem_freq_mhz =3D 547 }, + { .cpu_freq_mhz =3D 4185, .mem_freq_mhz =3D 4224 }, + } + }, + }, + }, + { + .memory_type =3D MEMLAT_HW_LLCC, + .name =3D "llcc", + .mem_table =3D kaanapali_llcc_table, + .num_opps =3D ARRAY_SIZE(kaanapali_llcc_table), + .grp_ev =3D kaanapali_llcc_grp_ev, + .monitor_cnt =3D 3, + .memory_range =3D { .min_freq_khz =3D 282000, .max_freq_khz =3D 1350000 = }, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0x3f, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 5, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 787, .mem_freq_mhz =3D 282 }, + { .cpu_freq_mhz =3D 960, .mem_freq_mhz =3D 350 }, + { .cpu_freq_mhz =3D 1536, .mem_freq_mhz =3D 533 }, + { .cpu_freq_mhz =3D 2534, .mem_freq_mhz =3D 806 }, + { .cpu_freq_mhz =3D 3552, .mem_freq_mhz =3D 933 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xc0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 8, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 614, .mem_freq_mhz =3D 282 }, + { .cpu_freq_mhz =3D 864, .mem_freq_mhz =3D 350 }, + { .cpu_freq_mhz =3D 1382, .mem_freq_mhz =3D 533 }, + { .cpu_freq_mhz =3D 2131, .mem_freq_mhz =3D 806 }, + { .cpu_freq_mhz =3D 2726, .mem_freq_mhz =3D 933 }, + { .cpu_freq_mhz =3D 3513, .mem_freq_mhz =3D 1066 }, + { .cpu_freq_mhz =3D 3916, .mem_freq_mhz =3D 1211 }, + { .cpu_freq_mhz =3D 4185, .mem_freq_mhz =3D 1350 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0xff, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 2035, .mem_freq_mhz =3D 282 }, + { .cpu_freq_mhz =3D 4185, .mem_freq_mhz =3D 533 }, + } + }, + }, + }, + { + .memory_type =3D MEMLAT_HW_DDR_QOS_MOBILE, + .name =3D "ddr-qos", + .monitor_cnt =3D 4, + .mem_table =3D glymur_ddr_qos_table, + .num_opps =3D ARRAY_SIZE(glymur_ddr_qos_table), + .grp_ev =3D kaanapali_ddr_qos_grp_ev, + .memory_range =3D { .min_freq_khz =3D 0, .max_freq_khz =3D 1 }, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0xff, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 2035, .mem_freq_mhz =3D 0 }, + { .cpu_freq_mhz =3D 4185, .mem_freq_mhz =3D 1 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xc0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 1574, .mem_freq_mhz =3D 0 }, + { .cpu_freq_mhz =3D 4185, .mem_freq_mhz =3D 1 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0xc0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 2131, .mem_freq_mhz =3D 0 }, + { .cpu_freq_mhz =3D 4185, .mem_freq_mhz =3D 1 }, + } + }, + { + .name =3D "mon_3", + .cpu_mask =3D 0xc0, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq_mhz =3D 3513, .mem_freq_mhz =3D 0 }, + { .cpu_freq_mhz =3D 4185, .mem_freq_mhz =3D 1 }, + } + }, + }, + }, +}; + +static const struct scmi_qcom_memlat_cfg_data glymur_memlat_data =3D { + .memory_cfg =3D glymur_memory_cfg, + .common_ev =3D glymur_common_ev, + .cpucp_legacy_freq_method =3D true, + .cpucp_sample_ms =3D 4, + .memory_cnt =3D ARRAY_SIZE(glymur_memory_cfg), +}; + +static const struct scmi_qcom_memlat_cfg_data hamoa_memlat_data =3D { + .memory_cfg =3D hamoa_memory_cfg, + .common_ev =3D hamoa_common_ev, + .cpucp_legacy_freq_method =3D true, + .cpucp_sample_ms =3D 4, + .memory_cnt =3D ARRAY_SIZE(hamoa_memory_cfg), +}; + +static const struct scmi_qcom_memlat_cfg_data kaanapali_memlat_data =3D { + .memory_cfg =3D kaanapali_memory_cfg, + .common_ev =3D kaanapali_common_ev, + .cpucp_legacy_freq_method =3D true, + .cpucp_sample_ms =3D 4, + .memory_cnt =3D ARRAY_SIZE(kaanapali_memory_cfg), +}; + +static const struct of_device_id scmi_qcom_memlat_configs[] =3D { + { .compatible =3D "qcom,glymur", .data =3D &glymur_memlat_data }, + { .compatible =3D "qcom,mahua", .data =3D &glymur_memlat_data }, + { .compatible =3D "qcom,x1e80100", .data =3D &hamoa_memlat_data }, + { .compatible =3D "qcom,x1p42100", .data =3D &hamoa_memlat_data }, + { .compatible =3D "qcom,kaanapali", .data =3D &kaanapali_memlat_data }, + { } +}; + +static int memlat_set_param(struct scmi_qcom_memlat_info *info, void *msg, + size_t size, u32 param_id) +{ + return info->ops->set_param(info->ph, msg, size, MEMLAT_ALGO_STR, param_i= d); +} + +static int configure_cpucp_common_events(struct scmi_qcom_memlat_info *inf= o) +{ + struct ev_map_msg ev =3D {}; + int i; + + ev.num_evs =3D cpu_to_le32(NUM_COMMON_EVS); + ev.hw_type =3D cpu_to_le32(MEMLAT_HW_TYPE_ALL); + for (i =3D 0; i < NUM_COMMON_EVS; i++) + ev.cid[i] =3D cpu_to_le32(info->cfg_data->common_ev[i]); + + return memlat_set_param(info, &ev, sizeof(ev), MEMLAT_SET_COMMON_EV_MAP); +} + +static int configure_cpucp_grp(struct device *dev, struct scmi_qcom_memlat= _info *info, + int memory_index) +{ + const struct scmi_qcom_memory_cfg *cfg =3D &info->cfg_data->memory_cfg[me= mory_index]; + struct ev_map_msg ev =3D {}; + struct node_msg node =3D {}; + int ret, i; + + node.cpumask =3D cpu_to_le32(*cpumask_bits(cpu_possible_mask)); + node.hw_type =3D cpu_to_le32(cfg->memory_type); + + /* mon_type/mon_idx are don't-care for SET_MEM_GROUP; leave them zero. */ + ret =3D memlat_set_param(info, &node, sizeof(node), MEMLAT_SET_MEM_GROUP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure mem type %d\n", + cfg->memory_type); + + ev.num_evs =3D cpu_to_le32(NUM_GRP_EVS); + ev.hw_type =3D cpu_to_le32(cfg->memory_type); + for (i =3D 0; i < NUM_GRP_EVS; i++) + ev.cid[i] =3D cpu_to_le32(cfg->grp_ev[i]); + + ret =3D memlat_set_param(info, &ev, sizeof(ev), MEMLAT_SET_GRP_EV_MAP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure event map for mem ty= pe %d\n", + cfg->memory_type); + + return 0; +} + +static int configure_cpucp_mon(struct device *dev, struct scmi_qcom_memlat= _info *info, + int memory_index, int monitor_index) +{ + const struct scmi_qcom_memory_cfg *cfg =3D &info->cfg_data->memory_cfg[me= mory_index]; + const struct scmi_qcom_monitor_cfg *mon =3D &cfg->monitor_cfg[monitor_ind= ex]; + struct scalar_param_msg scalar =3D {}; + struct map_param_msg map =3D {}; + struct node_msg node =3D {}; + int ret, i; + + if (mon->table_len > MEMLAT_MAX_MAP_ENTRIES) + return -EINVAL; + + node.cpumask =3D cpu_to_le32(mon->cpu_mask); + node.hw_type =3D cpu_to_le32(cfg->memory_type); + + /* The compute monitor passively scales with cpufreq irrespective of IPM = ratio. */ + node.mon_type =3D cpu_to_le32(!mon->ipm_ceil); + node.mon_idx =3D cpu_to_le32(monitor_index); + strscpy(node.mon_name, mon->name, sizeof(node.mon_name)); + ret =3D memlat_set_param(info, &node, sizeof(node), MEMLAT_SET_MONITOR); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure monitor %s\n", mon->= name); + + scalar.hw_type =3D cpu_to_le32(cfg->memory_type); + scalar.mon_idx =3D cpu_to_le32(monitor_index); + scalar.val =3D cpu_to_le32(mon->ipm_ceil); + ret =3D memlat_set_param(info, &scalar, sizeof(scalar), MEMLAT_IPM_CEIL); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set ipm ceil for %s\n", mon->n= ame); + + scalar.val =3D cpu_to_le32(mon->be_stall_floor); + ret =3D memlat_set_param(info, &scalar, sizeof(scalar), MEMLAT_BE_STALL_F= LOOR); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set be_stall_floor for %s\n", = mon->name); + + map.hw_type =3D cpu_to_le32(cfg->memory_type); + map.mon_idx =3D cpu_to_le32(monitor_index); + map.nr_rows =3D cpu_to_le32(mon->table_len); + for (i =3D 0; i < mon->table_len; i++) { + map.tbl[i].cpu_freq_mhz =3D cpu_to_le16(mon->table[i].cpu_freq_mhz); + map.tbl[i].mem_freq_mhz =3D cpu_to_le16(mon->table[i].mem_freq_mhz); + } + ret =3D memlat_set_param(info, &map, sizeof(map), MEMLAT_MON_FREQ_MAP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure freq_map for %s\n", = mon->name); + + scalar.val =3D cpu_to_le32(cfg->memory_range.min_freq_khz); + ret =3D memlat_set_param(info, &scalar, sizeof(scalar), MEMLAT_SET_MIN_FR= EQ); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set min_freq for %s\n", mon->n= ame); + + scalar.val =3D cpu_to_le32(cfg->memory_range.max_freq_khz); + ret =3D memlat_set_param(info, &scalar, sizeof(scalar), MEMLAT_SET_MAX_FR= EQ); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set max_freq for %s\n", mon->n= ame); + + return 0; +} + +static int scmi_qcom_devfreq_get_cur_freq(struct device *dev, unsigned lon= g *freq) +{ + struct scmi_qcom_memory_info *memory =3D dev_get_drvdata(dev); + const struct qcom_generic_ext_ops *ops =3D memory->ops; + const struct scmi_qcom_memory_cfg *cfg =3D memory->cfg; + u32 max_freq_khz =3D 0; + int ret, i; + + /* The bus's voted frequency is the max reported across all its monitors.= */ + for (i =3D 0; i < cfg->monitor_cnt; i++) { + union cur_freq_msg msg =3D {}; + + msg.req.hw_type =3D cpu_to_le32(cfg->memory_type); + msg.req.mon_idx =3D cpu_to_le32(i); + + ret =3D ops->get_param(memory->ph, &msg, sizeof(msg.req), MEMLAT_ALGO_ST= R, + MEMLAT_GET_CUR_FREQ, sizeof(msg.resp)); + if (ret < 0) { + /* One monitor failing shouldn't abort the whole read-back. */ + dev_warn_once(dev, "failed to get current frequency for %s\n", + cfg->monitor_cfg[i].name); + continue; + } + + max_freq_khz =3D max(max_freq_khz, le32_to_cpu(msg.resp)); + } + + /* + * DDR/LLCC report a frequency in kHz (converted to Hz for the OPP + * table); DDR_QOS reports a 0/1 level mapped to its synthetic OPP keys. + */ + if (cfg->memory_range.max_freq_khz > 1) + *freq =3D (unsigned long)((u64)max_freq_khz * HZ_PER_KHZ); + else + *freq =3D max_freq_khz ? 100 : 1; + + return 0; +} + +static void scmi_qcom_memlat_teardown(struct scmi_qcom_memlat_info *info) +{ + for (int i =3D 0; i < info->memory_cnt; i++) { + struct scmi_qcom_memory_info *memory =3D info->memory[i]; + + if (!memory || !memory->fdev) + continue; + + if (memory->devfreq) + devfreq_remove_device(memory->devfreq); + dev_pm_opp_remove_all_dynamic(&memory->fdev->dev); + faux_device_destroy(memory->fdev); + } +} + +static int scmi_qcom_memlat_configure_events(struct scmi_device *sdev, + struct scmi_qcom_memlat_info *info) +{ + const struct qcom_generic_ext_ops *ops =3D info->ops; + struct scmi_protocol_handle *ph =3D info->ph; + __le32 sample_ms, freq_method; + int i, j, ret; + + ret =3D configure_cpucp_common_events(info); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, "failed to configure common events= \n"); + + for (i =3D 0; i < info->memory_cnt; i++) { + ret =3D configure_cpucp_grp(&sdev->dev, info, i); + if (ret < 0) + return ret; + + for (j =3D 0; j < info->memory[i]->cfg->monitor_cnt; j++) { + ret =3D configure_cpucp_mon(&sdev->dev, info, i, j); + if (ret < 0) + return ret; + } + } + + sample_ms =3D cpu_to_le32(info->cfg_data->cpucp_sample_ms); + ret =3D memlat_set_param(info, &sample_ms, sizeof(sample_ms), MEMLAT_SAMP= LE_MS); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, "failed to set sample_ms\n"); + + freq_method =3D cpu_to_le32(info->cfg_data->cpucp_legacy_freq_method); + ret =3D memlat_set_param(info, &freq_method, sizeof(freq_method), + MEMLAT_SET_EFFECTIVE_FREQ_METHOD); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, + "failed to set effective frequency calc method\n"); + + /* Start sampling and voting timer */ + ret =3D ops->start_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_START_TI= MER); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, "failed to start memory group time= r\n"); + + for (i =3D 0; i < info->memory_cnt; i++) { + struct scmi_qcom_memory_info *memory =3D info->memory[i]; + const struct scmi_qcom_memory_range *range =3D &memory->cfg->memory_rang= e; + struct devfreq_dev_profile *profile =3D &memory->profile; + + /* + * CPUCP re-evaluates and re-votes at most once per cpucp_sample_ms, + * so a new operating point can appear only that often. Polling at half + * that period guarantees each distinct vote is observed in trans_stat + * before it can change again. + */ + profile->polling_ms =3D max(1U, info->cfg_data->cpucp_sample_ms / 2); + profile->get_cur_freq =3D scmi_qcom_devfreq_get_cur_freq; + profile->initial_freq =3D range->max_freq_khz > 1 ? + (unsigned long)((u64)range->min_freq_khz * HZ_PER_KHZ) : + range->min_freq_khz; + + faux_device_set_drvdata(memory->fdev, memory); + + memory->devfreq =3D devfreq_add_device(&memory->fdev->dev, profile, + DEVFREQ_GOV_REMOTE, NULL); + if (IS_ERR(memory->devfreq)) { + ret =3D PTR_ERR(memory->devfreq); + memory->devfreq =3D NULL; + ops->stop_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_STOP_TIMER); + return dev_err_probe(&sdev->dev, ret, "failed to add devfreq device\n"); + } + } + + return 0; +} + +static int scmi_qcom_memlat_setup(struct scmi_device *sdev, struct scmi_qc= om_memlat_info *info) +{ + const struct scmi_qcom_memlat_cfg_data *cfg_data; + int ret, i, j; + + cfg_data =3D of_machine_get_match_data(scmi_qcom_memlat_configs); + if (!cfg_data) { + dev_dbg(&sdev->dev, "no memlat config data for this platform\n"); + return -ENODEV; + } + + info->cfg_data =3D cfg_data; + info->memory =3D devm_kcalloc(&sdev->dev, cfg_data->memory_cnt, + sizeof(*info->memory), GFP_KERNEL); + if (!info->memory) + return -ENOMEM; + + for (i =3D 0; i < cfg_data->memory_cnt; i++) { + const struct scmi_qcom_memory_cfg *memory_cfg =3D &cfg_data->memory_cfg[= i]; + struct scmi_qcom_memory_info *memory; + + memory =3D devm_kzalloc(&sdev->dev, sizeof(*memory), GFP_KERNEL); + if (!memory) { + ret =3D -ENOMEM; + goto err_teardown; + } + + memory->cfg =3D memory_cfg; + memory->ops =3D info->ops; + memory->ph =3D info->ph; + info->memory[i] =3D memory; + + memory->fdev =3D faux_device_create(memory_cfg->name, &sdev->dev, NULL); + if (!memory->fdev) { + ret =3D dev_err_probe(&sdev->dev, -ENODEV, + "failed to create faux device\n"); + goto err_teardown; + } + info->memory_cnt =3D i + 1; + + for (j =3D 0; j < memory_cfg->num_opps; j++) { + struct dev_pm_opp_data data =3D { + .freq =3D memory_cfg->mem_table[j].freq, + }; + + ret =3D dev_pm_opp_add_dynamic(&memory->fdev->dev, &data); + if (ret) { + dev_err_probe(&sdev->dev, ret, "failed to add OPP\n"); + goto err_teardown; + } + } + } + + return 0; + +err_teardown: + scmi_qcom_memlat_teardown(info); + return ret; +} + +static int scmi_qcom_devfreq_memlat_probe(struct scmi_device *sdev) +{ + const struct scmi_handle *handle =3D sdev->handle; + const struct qcom_generic_ext_ops *ops; + struct scmi_qcom_memlat_info *info; + struct scmi_protocol_handle *ph; + int ret; + + if (!handle) + return -ENODEV; + + info =3D devm_kzalloc(&sdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + ops =3D handle->devm_protocol_get(sdev, SCMI_PROTOCOL_QCOM_GENERIC, &ph); + if (IS_ERR(ops)) + return PTR_ERR(ops); + + info->ops =3D ops; + info->ph =3D ph; + + ret =3D scmi_qcom_memlat_setup(sdev, info); + if (ret) + return ret; + + ret =3D scmi_qcom_memlat_configure_events(sdev, info); + if (ret) { + scmi_qcom_memlat_teardown(info); + return ret; + } + + dev_set_drvdata(&sdev->dev, info); + + return 0; +} + +static void scmi_qcom_devfreq_memlat_remove(struct scmi_device *sdev) +{ + struct scmi_qcom_memlat_info *info =3D dev_get_drvdata(&sdev->dev); + int ret; + + ret =3D info->ops->stop_activity(info->ph, NULL, 0, MEMLAT_ALGO_STR, MEML= AT_STOP_TIMER); + if (ret < 0) + dev_err(&sdev->dev, "failed to stop memory group timer\n"); + + scmi_qcom_memlat_teardown(info); +} + +static const struct scmi_device_id scmi_id_table[] =3D { + { SCMI_PROTOCOL_QCOM_GENERIC, "qcom-generic-ext" }, + { }, +}; +MODULE_DEVICE_TABLE(scmi, scmi_id_table); + +static struct scmi_driver scmi_qcom_devfreq_memlat_driver =3D { + .name =3D "scmi-qcom-devfreq-memlat", + .probe =3D scmi_qcom_devfreq_memlat_probe, + .remove =3D scmi_qcom_devfreq_memlat_remove, + .id_table =3D scmi_id_table, +}; +module_scmi_driver(scmi_qcom_devfreq_memlat_driver); + +MODULE_AUTHOR("Pragnesh Papaniya "); +MODULE_AUTHOR("Sibi Sankar "); +MODULE_DESCRIPTION("Qualcomm SCMI memlat devfreq driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Jul 24 21:54:50 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4B993A901F for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf8efe3afbsm45993805ad.33.2026.07.24.00.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 00:19:39 -0700 (PDT) From: Pragnesh Papaniya Date: Fri, 24 Jul 2026 12:48:13 +0530 Subject: [PATCH RFC 08/10] arm64: dts: qcom: glymur: Enable LLCC/DDR/DDR_QOS DVFS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-rfc_v8_scmi_memlat-v1-8-cb732bcff1f4@oss.qualcomm.com> References: <20260724-rfc_v8_scmi_memlat-v1-0-cb732bcff1f4@oss.qualcomm.com> In-Reply-To: <20260724-rfc_v8_scmi_memlat-v1-0-cb732bcff1f4@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784877514; l=2333; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=aJgvkeU1hYS46AIZM4QP3B9a00RqrtIO/xjx76HW+fg=; b=hyNDpepWQq8DZW50Hf0XKBhuQW9YP8x4gP2ntWFWx1ni2fW0+zMs1ZDdZWb3Acb5szBESdj+M y7/hPXttUVHB9YFZsF5+60PtQo990FpWQysl1rMZga50QkgkPksdsW+ X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDA2NSBTYWx0ZWRfXwpSNfrd8Zav2 wDdzpE/y4quCT2+bMbZz9JAHnhBmxmXm9KCyzgPBsQ1twkKG1U29zkXeTbqVHJwj/2j1mWF/PqO JghUN69oQi/hv30nHAzM+uO3TDe2bCSeMXIJ0OpJGDrCaH5ne1qvEDcd6up0Lfg/K9oHuidfVXi VHU78fN6KizC+JJlArUTr+XNl+UMlR5R8h9iU9u2JcKNaONC55C7Pp9cFhOsGt4tDDWdf7xbZrZ LxjdTFbg2axlRkWgV4AONuIboUkv1UjliS02jv5uDwK5l6QFQiFmmRzzrGlOjNUpmesaJNutTDk sNuS6IkgBpqsqU1ssZ4Bd3Qt52V3rkHy7RLQasPoii1nJZ7FIsiThe3lEq9y+WXxk/O44VywJc7 E2QiArOQHrKT90PDKbomavxMyHVFSECYD9rig1Svle8ojsscjWTBsPulX2vnE9MTAn2Q6mm6HqS 8wN/RU2w97ZnB3rf1CQ== X-Proofpoint-GUID: qr2yKJ6JDgHVVlBHJvzI1A57Yw2mNiS1 X-Authority-Analysis: v=2.4 cv=DfAnbPtW c=1 sm=1 tr=0 ts=6a63120d cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=-olaiSHPbsRiaquSn4UA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDA2NSBTYWx0ZWRfX8cwx3/qGlCrR RblOjk3z9qyRV3Efo7zz9NC98vcWkrw6AIq7S/EXK+hsCK9v108wecOiGhz+bB32qJm1ycDU5dR M4CmrfWz80hbtcyLJC4tF5MVjwEwM/M= X-Proofpoint-ORIG-GUID: qr2yKJ6JDgHVVlBHJvzI1A57Yw2mNiS1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_01,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 spamscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 adultscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240065 From: Sibi Sankar On Qualcomm Glymur SoCs, the memlat governor and the mechanism for controlling the LLCC and DDR/DDR_QOS frequencies run on the CPU Control Processor (CPUCP). Add the CPUCP mailbox and SCMI nodes required for the QCOM SCMI Generic Extension protocol to probe and get functional bus DVFS on Glymur/Mahua SoCs. Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya --- arch/arm64/boot/dts/qcom/glymur.dtsi | 41 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index f32af66a3f1c..32ac471e6727 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -420,6 +420,20 @@ scmi_perf: protocol@13 { #power-domain-cells =3D <1>; }; }; + + cpucp_scmi: scmi-1 { + compatible =3D "arm,scmi"; + mboxes =3D <&cpucp_mbox 0>, <&cpucp_mbox 2>; + mbox-names =3D "tx", "rx"; + shmem =3D <&cpucp_scp_lpri0>, <&cpucp_scp_lpri1>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_vendor: protocol@80 { + reg =3D <0x80>; + }; + }; }; =20 clk_virt: interconnect-0 { @@ -7658,6 +7672,13 @@ pdp0_mbox: mailbox@17610000 { #mbox-cells =3D <1>; }; =20 + cpucp_mbox: mailbox@17620000 { + compatible =3D "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg =3D <0x0 0x17620000 0 0x8000>, <0 0x18830000 0 0x8000>; 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Add the SCMI vendor protocol node required for the QCOM SCMI Generic Extension protocol to probe and get functional bus DVFS on Hamoa/Purwa SoCs. Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom= /hamoa.dtsi index 09527dcf9576..e9e75c4c4da6 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -340,6 +340,10 @@ scmi_dvfs: protocol@13 { reg =3D <0x13>; #power-domain-cells =3D <1>; }; + + scmi_vendor: protocol@80 { + reg =3D <0x80>; + }; }; }; =20 --=20 2.34.1 From nobody Fri Jul 24 21:54:50 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32ADE3AA517 for ; Fri, 24 Jul 2026 07:20:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf8efe3afbsm45993805ad.33.2026.07.24.00.19.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 00:19:54 -0700 (PDT) From: Pragnesh Papaniya Date: Fri, 24 Jul 2026 12:48:15 +0530 Subject: [PATCH RFC 10/10] arm64: dts: qcom: kaanapali: Enable LLCC/DDR/DDR_QOS DVFS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-rfc_v8_scmi_memlat-v1-10-cb732bcff1f4@oss.qualcomm.com> References: <20260724-rfc_v8_scmi_memlat-v1-0-cb732bcff1f4@oss.qualcomm.com> In-Reply-To: <20260724-rfc_v8_scmi_memlat-v1-0-cb732bcff1f4@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, Jia Yang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784877514; l=2511; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=RRRnlY8bGZF+Ix/OI25BJOg4/PDL2F0fBt3FTJPUD4w=; b=Ot/2FakveQieb9FjNIaC8Eh8UzyqnPZIl04ZXlXEwPmL4WwfHv5BdmPf/4u/1sE4diECf+Fzi z+UeTkQi74gBMDWhyksq21XsTERa3lzeFSsIje9jS5gJrlPZEsxfqRp X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDA2NSBTYWx0ZWRfX3gilDuQ9pGLn 2gXuNGAv20pC4Xhjvjaho2eMjcfjyMPwkvnkmuDyt6oWDOKCLhKLpStBRlOP91b0U8GSx1iIQL8 34MfnaLXFTXLb70oOLCLdc/DPcB1hC0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDA2NSBTYWx0ZWRfXxMYu6KdVRfRL E62onUEGsw8WLmInS2AB+rT3mFpzj++f9KF7P7soeYbQ92HsnJVVNcFHIykSdK3VwmXzYQwyyqa tTkzP+ojbOHSOecKeNughaiMaXMgoofMeOnM9+UGPcuJeRimlp0Ekqt/gOVdyK25thzDsUUDl9t AU+hqDSBDVYYkFO7q0r7aCetDMmIEOtU6jv2t4XKRe6ztFFnk00uZrWM/Cm6LiNXCdM78RnPgR6 D1SE2huDSOodONIznpNxBBZxUmgsYCRSnv38dk3DbvVKeAsFMrgqUtZeURDFPNkPINt3c/hlCNc IJzufEJgSp92M8U6ox46Kei+GfEBR+mWEsU/WjuaxKfMEe9GVnXTs9L5d2GBu9y2UzP+MAxB7FL pY6r3d2fPcmCbR8zQ/oG6rVWjxrPm0iUBC30fCwGOxu0M0De6RuR4AHK6oBsaL+T+OoTVlIldBB 32dxhs3oK9XChIjT5Ig== X-Authority-Analysis: v=2.4 cv=Z9Dc2nRA c=1 sm=1 tr=0 ts=6a63121f cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=-olaiSHPbsRiaquSn4UA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: UgQxYJ8R2Q-N_DQDuCfhHZPfC2XdllW0 X-Proofpoint-ORIG-GUID: UgQxYJ8R2Q-N_DQDuCfhHZPfC2XdllW0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_01,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240065 From: Jia Yang On Qualcomm Kaanapali SoCs, the memlat governor and the mechanism for controlling the LLCC and DDR/DDR_QOS frequencies run on the CPU Control Processor (CPUCP) and are exposed via the QCOM SCMI Generic Extension protocol. Add the CPUCP mailbox, the SCMI shared-memory regions and the CPUCP SCMI instance (scmi-1) with the Qualcomm vendor protocol@80 required for the QCOM SCMI Generic Extension protocol to probe and get functional bus DVFS on Kaanapali. Signed-off-by: Jia Yang Signed-off-by: Pragnesh Papaniya --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 41 +++++++++++++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/= qcom/kaanapali.dtsi index 74699bc3eadb..594fac6d27bc 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -240,6 +240,20 @@ scmi_perf: protocol@13 { #power-domain-cells =3D <1>; }; }; + + cpucp_scmi: scmi-1 { + compatible =3D "arm,scmi"; + mboxes =3D <&cpucp_mbox 0>, <&cpucp_mbox 2>; + mbox-names =3D "tx", "rx"; + shmem =3D <&cpucp_scp_lpri0>, <&cpucp_scp_lpri1>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_vendor: protocol@80 { + reg =3D <0x80>; + }; + }; }; =20 clk_virt: interconnect-0 { @@ -5756,6 +5770,13 @@ pdp0_mbox: mailbox@17610000 { #mbox-cells =3D <1>; }; =20 + cpucp_mbox: mailbox@17620000 { + compatible =3D "qcom,kaanapali-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg =3D <0x0 0x17620000 0x0 0x8000>, <0x0 0x18830000 0x0 0x8000>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; + timer@17810000 { compatible =3D "arm,armv7-timer-mem"; reg =3D <0x0 0x17810000 0x0 0x1000>; @@ -5965,6 +5986,26 @@ rpmhpd_opp_super_turbo_no_cpr: opp-480 { }; }; =20 + cpucp_sram: sram@1d838000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x1d838000 0x0 0x400>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + ranges =3D <0x0 0x0 0x1d838000 0x400>; + + cpucp_scp_lpri0: scp-sram-section@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x200>; + }; + + cpucp_scp_lpri1: scp-sram-section@200 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x200 0x200>; + }; + }; + nsp_noc: interconnect@260c0000 { compatible =3D "qcom,kaanapali-nsp-noc"; reg =3D <0x0 0x260c0000 0x0 0x21280>; --=20 2.34.1