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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-314bc593b57sm621809eec.25.2026.07.24.08.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:00:26 -0700 (PDT) From: Luo Jie Date: Fri, 24 Jul 2026 08:00:23 -0700 Subject: [PATCH 01/12] clk: qcom: ipq-cmn-pll: Use devm_clk_hw_register_fixed_rate_parent_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-qcom_ipq5210_cmnpll-v1-1-a8b8679d215f@oss.qualcomm.com> References: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> In-Reply-To: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Luo Jie X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1784905224; l=2855; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=DqJuOV/GfzjgmUgcYK2yXmABHWZdkEen47SlyOIyCNs=; b=CszzAwQHyV2LxSb+MI94lZAbB6BzV5kYZovqbPvnzvbfQJILWHX8TUww4jdO4egkurl12hCqh diGdeDFvY21D7+uwcMrca5hXrzPnYP0AIMgZ+rELhF5LKcSUvKnxBox X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Authority-Analysis: v=2.4 cv=GJE41ONK c=1 sm=1 tr=0 ts=6a637e0d cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=abD0O5-mJzoiGkpUKuEA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX8XOjxp1UvU4S acV8yrWRx0Bxl82YBMjGxF7qgYNx9zX7VlaABCD00MAliZhiDo2EScioB0Xz2MbcHYyBj4mCxBt 0ieioSiqlma14NyxfF34XFUmUsZkMSQeQyBFqKHPleznUeUoaaUHH4YtOGnR5d16f23o1Z6Ds1/ g19oEyUTfFeDk7+X+wPIj26ccayw89Bkm3oGz2hwNJWSp5aNs+bI/ghKvNDJskO/j8ukSyLQgNg sphJB2ulG09+QJr9ZljkPv0Pw5Whe1gSfv89T2Ncvz0pFBVBzd9t2EUV2m8oE0wklNZqSNxEpFn ObUKZmbnhFazp76SK1vcHOK/zsNkBx8jbwOYwuWncLvnbgK7TFqNJ0eYtvMBJMrg6cck+EDin02 +KlrBV78aRQ20FESzcBttyd+b7HPFWtLLgjngIlmF+eFNaF3QzJ11IsdD5v6+g1/zR4eGBkqO0K M4hbzaoaVf5kD2VdMNw== X-Proofpoint-ORIG-GUID: ub5YuEEh1QJhXFAxDX-MEwHDLGr8O8fr X-Proofpoint-GUID: ub5YuEEh1QJhXFAxDX-MEwHDLGr8O8fr X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX4mg9NOOlisAM RWn3LvokhLAvq/RKphPjuxm2Ll1+zuaMnfOwwmeN5ILn4u+EfwUUAUTZmdQK2n9zSbTEcNk3fUA G6vqApy8N2s5upWRnLr3Ykb0z4xlFHs= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240135 Replace clk_hw_register_fixed_rate_parent_hw() with the managed devm_clk_hw_register_fixed_rate_parent_data() so the fixed-rate output clocks are automatically unregistered when the device is unbound. Since all clocks in the driver are now registered via devm_ variants, the remove callback 'ipq_cmn_pll_clk_remove()' and the manual 'unregister_fixed_clk' error-path loop are no longer needed and are removed. Signed-off-by: Luo Jie Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/ipq-cmn-pll.c | 39 +++++++++------------------------------ 1 file changed, 9 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index dafe8c1738df..4fdf78f6829e 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -390,13 +390,14 @@ static int ipq_cmn_pll_register_clks(struct platform_= device *pdev) =20 /* Register the fixed rate output clocks. */ for (i =3D 0; i < num_clks; i++) { - hw =3D clk_hw_register_fixed_rate_parent_hw(dev, fixed_clk[i].name, - cmn_pll_hw, 0, - fixed_clk[i].rate); - if (IS_ERR(hw)) { - ret =3D PTR_ERR(hw); - goto unregister_fixed_clk; - } + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + + hw =3D devm_clk_hw_register_fixed_rate_parent_data(dev, + fixed_clk[i].name, + &pdata, 0, + fixed_clk[i].rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); =20 hw_data->hws[fixed_clk[i].id] =3D hw; } @@ -410,17 +411,11 @@ static int ipq_cmn_pll_register_clks(struct platform_= device *pdev) =20 ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data); if (ret) - goto unregister_fixed_clk; + return ret; =20 platform_set_drvdata(pdev, hw_data); =20 return 0; - -unregister_fixed_clk: - while (i > 0) - clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]); - - return ret; } =20 static int ipq_cmn_pll_clk_probe(struct platform_device *pdev) @@ -462,21 +457,6 @@ static int ipq_cmn_pll_clk_probe(struct platform_devic= e *pdev) return 0; } =20 -static void ipq_cmn_pll_clk_remove(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *hw_data =3D platform_get_drvdata(pdev); - int i; - - /* - * The clock with index CMN_PLL_CLK is unregistered by - * device management. - */ - for (i =3D 0; i < hw_data->num; i++) { - if (i !=3D CMN_PLL_CLK) - clk_hw_unregister(hw_data->hws[i]); - } -} - static const struct dev_pm_ops ipq_cmn_pll_pm_ops =3D { SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) }; @@ -494,7 +474,6 @@ MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids); =20 static struct platform_driver ipq_cmn_pll_clk_driver =3D { .probe =3D ipq_cmn_pll_clk_probe, - .remove =3D ipq_cmn_pll_clk_remove, .driver =3D { .name =3D "ipq_cmn_pll", .of_match_table =3D ipq_cmn_pll_clk_ids, --=20 2.43.0 From nobody Fri Jul 24 21:30:56 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5526F33D6FA for ; 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The IPQ5210 CMN PLL supplies configurable clocks to the NSS (network subsystem), PPE (packet process engine), and PON (passive optical network) hardware blocks. It also supplies a raw EPHY output clock for the integrated Ethernet PHY and several gated fixed-rate outputs to Ethernet PHY and switch devices. Signed-off-by: Luo Jie --- .../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 + include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h | 30 ++++++++++++++++++= ++++ 2 files changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.y= aml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml index a4f9af8fa187..91e17f126a9b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -25,6 +25,7 @@ properties: compatible: enum: - qcom,ipq5018-cmn-pll + - qcom,ipq5210-cmn-pll - qcom,ipq5332-cmn-pll - qcom,ipq5424-cmn-pll - qcom,ipq6018-cmn-pll diff --git a/include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h b/include/dt-= bindings/clock/qcom,ipq5210-cmn-pll.h new file mode 100644 index 000000000000..191589fd5311 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5210-cmn-pll.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5210_CMN_PLL_H +#define _DT_BINDINGS_CLK_QCOM_IPQ5210_CMN_PLL_H + +/* Parent clock */ +#define IPQ5210_CMN_PLL_CLK 0 + +/* Fixed-rate clocks */ +#define IPQ5210_XO_24MHZ_CLK 1 +#define IPQ5210_SLEEP_32KHZ_CLK 2 + +/* Configurable divider clocks */ +#define IPQ5210_NSS_CLK 3 +#define IPQ5210_PPE_CLK 4 +#define IPQ5210_PON_REFCLK 5 +#define IPQ5210_EPHY_RAW_CLK 6 + +/* Gate clocks */ +#define IPQ5210_PCS_31P25MHZ_CLK 7 +#define IPQ5210_ETH0_50MHZ_CLK 8 +#define IPQ5210_ETH1_50MHZ_CLK 9 +#define IPQ5210_ETH2_50MHZ_CLK 10 +#define IPQ5210_EPHY_50MHZ_CLK 11 +#define IPQ5210_ETH_25MHZ_CLK 12 + +#endif --=20 2.43.0 From nobody Fri Jul 24 21:30:56 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82691345CA1 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-314bc593b57sm621809eec.25.2026.07.24.08.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:00:27 -0700 (PDT) From: Luo Jie Date: Fri, 24 Jul 2026 08:00:25 -0700 Subject: [PATCH 03/12] clk: qcom: ipq-cmn-pll: Add analog soft-reset helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-qcom_ipq5210_cmnpll-v1-3-a8b8679d215f@oss.qualcomm.com> References: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> In-Reply-To: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Luo Jie X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1784905224; l=2559; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=sZaF10vBisSJ9QFSuDzkeFZ3FkrTFu5V6pURX6pp+do=; b=TKcQF2uKOlWteKqmyb9MPLLReArucJ9Mzz9/wZauk2reHky8k0gk9Z6uznGR9Oipw4E8vZt1l 60gwRkaqmLTDPQuajElAxEwLMSS1fICbA3RIzResKS2dgZlRZuwjAf4 X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-ORIG-GUID: sq7rzoTO2j0_SbAoYOTNW4MrK06Wor7h X-Proofpoint-GUID: sq7rzoTO2j0_SbAoYOTNW4MrK06Wor7h X-Authority-Analysis: v=2.4 cv=e/k2j6p/ c=1 sm=1 tr=0 ts=6a637e11 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=8SFKHiaDcLpzCnYd0_0A:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX47RUuQb6vHC8 yKeIqrCYdsfAKS+3ICsossQiq3VvjVtCJZbqvnamMFH+IFyX+aqLYKkU+3F0sjjsaxFYirYVTSz R6fL1LsZp4U+LJsBASmtZbobtS6eWsUlz92/6HB09VaSbYItER1mjvXGuoUUS2KFm87BunyV6R6 OeFeOkw8o8WsSXwrTZ8GZHENFHx02nYm2qZcPU47565t+lLhF/QnU/zc4zI7rYnCRHJ7WAyZN9e 9XdKg+Y/ZLaKkkrLBsqJ429gxWMvvGqttEY/KtGTy1I/6HNISzEZ3K0E2ijAGoBz2NfpcCbzPf1 fqUP+78xYdsX0qAcaCjcTCPwejZJR/pOW8ij98LJ3sGiLHXbGCYg3WA44vDUGBilwOCBSsdHqsm 6qjf08lFOsJvz7MJrtObDEuANhKBofe+ZBji2YLRNQYk2VEml8I/LQgap1ImNBSjbFEUKsAqULE oIlq0q01CX4LDHHW6Kg== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX4ubIMQU1hdo/ R60Kb4a/kR4v2ktjGZFdUUKRPgFoiGynf8OmekzxGzmDI8ppOxJtOT1GF+lDidLYyYNcBiUsDpI SPhfjqFgP5TNTWKneh3Bct+r0kDfm9w= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240135 Add clk_cmn_pll_ana_soft_reset(), which toggles the CMN_ANA_EN_SW_RSTN bit in CMN_PLL_POWER_ON_AND_RESET to perform an analog soft reset of the PLL, then polls CMN_PLL_LOCKED until the output clocks are stable. This helper will also be used by the NSS, PPE, and PON reference clock set_rate handlers added in subsequent patches. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 4fdf78f6829e..aa319d577871 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -210,6 +210,28 @@ static int ipq_cmn_pll_find_freq_index(unsigned long p= arent_rate) return index; } =20 +static int clk_cmn_pll_ana_soft_reset(struct regmap *regmap) +{ + int ret; + u32 val; + + ret =3D regmap_clear_bits(regmap, CMN_PLL_POWER_ON_AND_RESET, + CMN_ANA_EN_SW_RSTN); + if (ret) + return ret; + + usleep_range(1000, 1200); + ret =3D regmap_set_bits(regmap, CMN_PLL_POWER_ON_AND_RESET, + CMN_ANA_EN_SW_RSTN); + if (ret) + return ret; + + /* Stability check of CMN PLL output clocks. */ + return regmap_read_poll_timeout(regmap, CMN_PLL_LOCKED, val, + (val & CMN_PLL_CLKS_LOCKED), + 100, 100 * USEC_PER_MSEC); +} + static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -253,7 +275,6 @@ static int clk_cmn_pll_set_rate(struct clk_hw *hw, unsi= gned long rate, { struct clk_cmn_pll *cmn_pll =3D to_clk_cmn_pll(hw); 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Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 119 +++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 114 insertions(+), 5 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index aa319d577871..3df326c22fba 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -66,6 +66,11 @@ #define CMN_PLL_LOCKED 0x64 #define CMN_PLL_CLKS_LOCKED BIT(8) =20 +#define CMN_PLL_NSS_PPE_FREQ_CTRL 0x98 +#define CMN_PLL_NSS_CLK_SEL GENMASK(13, 8) +#define CMN_PLL_NSS_PPE_DIV_MIN 8 +#define CMN_PLL_NSS_PPE_DIV_MAX 63 + #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) =20 @@ -364,11 +369,105 @@ static struct clk_hw *ipq_cmn_pll_clk_hw_register(st= ruct platform_device *pdev) return &cmn_pll->hw; } =20 +/* + * NSS (Network Subsystem) clock operations. + * The NSS clock is derived from CMN PLL rate / 2, then divided by + * a configurable 6-bit divider (8-63). + */ +static unsigned long clk_nss_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_cmn_pll *nss_clk =3D to_clk_cmn_pll(hw); + u32 val, div; + + regmap_read(nss_clk->regmap, CMN_PLL_NSS_PPE_FREQ_CTRL, &val); + div =3D FIELD_GET(CMN_PLL_NSS_CLK_SEL, val); + if (WARN_ON_ONCE(!div)) + return 0; + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, 2ULL * div); +} + +static int clk_nss_ppe_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long div; + + if (WARN_ON_ONCE(!req->rate)) + return 0; + + div =3D DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate, 2ULL * req->rat= e); + div =3D clamp_t(unsigned long, div, CMN_PLL_NSS_PPE_DIV_MIN, + CMN_PLL_NSS_PPE_DIV_MAX); + + req->rate =3D DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate, 2ULL * di= v); + return 0; +} + +static int clk_nss_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_cmn_pll *nss_clk =3D to_clk_cmn_pll(hw); + unsigned long div; + int ret; + + if (rate =3D=3D 0) + return -EINVAL; + + div =3D DIV_ROUND_CLOSEST_ULL((u64)parent_rate, 2ULL * rate); + if (div < CMN_PLL_NSS_PPE_DIV_MIN || div > CMN_PLL_NSS_PPE_DIV_MAX) + return -EINVAL; + + ret =3D regmap_update_bits(nss_clk->regmap, CMN_PLL_NSS_PPE_FREQ_CTRL, + CMN_PLL_NSS_CLK_SEL, + FIELD_PREP(CMN_PLL_NSS_CLK_SEL, div)); + if (ret) + return ret; + + return clk_cmn_pll_ana_soft_reset(nss_clk->regmap); +} + +static const struct clk_ops clk_nss_ops =3D { + .recalc_rate =3D clk_nss_recalc_rate, + .determine_rate =3D clk_nss_ppe_determine_rate, + .set_rate =3D clk_nss_set_rate, +}; + +static struct clk_hw *ipq_cmn_pll_nss_register(struct platform_device *pde= v, + struct regmap *regmap, + struct clk_hw *cmn_pll_hw) +{ + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + struct device *dev =3D &pdev->dev; + struct clk_init_data init =3D {}; + struct clk_cmn_pll *nss_clk; + int ret; + + nss_clk =3D devm_kzalloc(dev, sizeof(*nss_clk), GFP_KERNEL); + if (!nss_clk) + return ERR_PTR(-ENOMEM); + + init.name =3D "nss-clk"; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_nss_ops; + + nss_clk->hw.init =3D &init; + nss_clk->regmap =3D regmap; + + ret =3D devm_clk_hw_register(dev, &nss_clk->hw); + if (ret) + return ERR_PTR(ret); + + return &nss_clk->hw; +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; struct clk_hw_onecell_data *hw_data; struct device *dev =3D &pdev->dev; + struct clk_cmn_pll *cmn_pll; struct clk_hw *cmn_pll_hw; unsigned int num_clks; struct clk_hw *hw; @@ -395,14 +494,24 @@ static int ipq_cmn_pll_register_clks(struct platform_= device *pdev) if (IS_ERR(cmn_pll_hw)) return PTR_ERR(cmn_pll_hw); =20 + cmn_pll =3D to_clk_cmn_pll(cmn_pll_hw); + /* Register the fixed rate output clocks. */ for (i =3D 0; i < num_clks; i++) { - struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + if (fixed_clk[i].rate) { + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + + hw =3D devm_clk_hw_register_fixed_rate_parent_data(dev, + fixed_clk[i].name, + &pdata, 0, + fixed_clk[i].rate); + } else if (!strcmp(fixed_clk[i].name, "nss")) { + hw =3D ipq_cmn_pll_nss_register(pdev, cmn_pll->regmap, + cmn_pll_hw); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-314bc593b57sm621809eec.25.2026.07.24.08.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:00:29 -0700 (PDT) From: Luo Jie Date: Fri, 24 Jul 2026 08:00:27 -0700 Subject: [PATCH 05/12] clk: qcom: ipq-cmn-pll: Add PPE clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-qcom_ipq5210_cmnpll-v1-5-a8b8679d215f@oss.qualcomm.com> References: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> In-Reply-To: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Luo Jie X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1784905224; l=3810; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=xuqTt5GjoAea9Mwg2P5H1PkIm/qIz8M0zitNWpkIwRE=; b=JevYk7GFcGwCVoa9WHymi/IM/SlxDVKAmgvKVfrGYswravJoGvfvRcAT9YQBYhX3WBvT+5PME ov6OXf0oEgCBNbLpNCWpdVKq10sryDeNAICgukGmMTNHi/RPaNpM1Tl X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-ORIG-GUID: O11TNioTy0xNrsRiqzt18GdDHkDtkFpS X-Proofpoint-GUID: O11TNioTy0xNrsRiqzt18GdDHkDtkFpS X-Authority-Analysis: v=2.4 cv=e/k2j6p/ c=1 sm=1 tr=0 ts=6a637e10 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=a0Q9v1deZHfQL7jRbVkA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX+j9KbnQZP0RL tRtSXqlv/XqKsyzjBwo6Eg3C/VyYuYV3FUm/HWSqlXBUhkyAFPPkJX9TKon6ANmeA1d+7qZjklY u8veSSpqLBdL+/zluIjZmGUkxkPQ1mHMTIEQ6uiGJO8qFtgLAJsJPdenh/STwjjn/0x1tiQx3xJ qyuTry88ntvUqhXoS/UD3LSg9sNJP8neYnCt1fXuK8hBg8dKkEivbmgDi6H0P52E1KgI4zSdlWF qV1GkA0sxFNjmboRV3fdJDNqXg8yiFhhFhOufmCtLF7UEaiWVsdvmXi8Ppe61puT4VBMikyi1u+ l2ONcutb7i5Be2NUsUyQepp00IxRLFdCURZbqqQOC2gfZJvXI9zXvUdR/y8q3ohbGZ5VXDCcrog h+6lpqKPp7h/HYX//psilkk4+FGEDk9tEs0mCbfk9ZsE9IG2Xyze9EHidqxLIAvp8tMBcOsTpJS dHxY9inlJYa2U8l6zKg== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfXwtrYlbgXNqNJ qcBcKHOWeiVQBT+/3XfXOU8beHWG5o1f1q3mie+oVLbCK5WW2I3grF3W98AMCEBbq1Le5OeaEJS +uv4tvnC14UfsB/5tjs4AmrOEGpX3Rw= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240135 The PPE (packet process engine) clock is derived from the CMN PLL output divided by 2 and then further divided by a configurable 6-bit divider with a valid range of 8-63. It shares the CMN_PLL_NSS_PPE_FREQ_CTRL register with the NSS clock but uses a different field (bits [5:0]). The determine_rate operation is shared with the NSS clock since the divider constraints and calculation are identical. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 81 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 81 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 3df326c22fba..020ad12ca1f2 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -68,6 +68,7 @@ =20 #define CMN_PLL_NSS_PPE_FREQ_CTRL 0x98 #define CMN_PLL_NSS_CLK_SEL GENMASK(13, 8) +#define CMN_PLL_PPE_CLK_SEL GENMASK(5, 0) #define CMN_PLL_NSS_PPE_DIV_MIN 8 #define CMN_PLL_NSS_PPE_DIV_MAX 63 =20 @@ -462,6 +463,83 @@ static struct clk_hw *ipq_cmn_pll_nss_register(struct = platform_device *pdev, return &nss_clk->hw; } =20 +/* + * PPE (Packet Process Engine) clock operations. + * The PPE clock is derived from CMN PLL rate / 2, then divided by + * a configurable 6-bit divider (8-63). + */ +static unsigned long clk_ppe_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_cmn_pll *ppe_clk =3D to_clk_cmn_pll(hw); + u32 val, div; + + regmap_read(ppe_clk->regmap, CMN_PLL_NSS_PPE_FREQ_CTRL, &val); + div =3D FIELD_GET(CMN_PLL_PPE_CLK_SEL, val); + if (WARN_ON_ONCE(!div)) + return 0; + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, 2ULL * div); +} + +static int clk_ppe_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_cmn_pll *ppe_clk =3D to_clk_cmn_pll(hw); + unsigned long div; + int ret; + + if (rate =3D=3D 0) + return -EINVAL; + + div =3D DIV_ROUND_CLOSEST_ULL((u64)parent_rate, 2ULL * rate); + if (div < CMN_PLL_NSS_PPE_DIV_MIN || div > CMN_PLL_NSS_PPE_DIV_MAX) + return -EINVAL; + + ret =3D regmap_update_bits(ppe_clk->regmap, CMN_PLL_NSS_PPE_FREQ_CTRL, + CMN_PLL_PPE_CLK_SEL, + FIELD_PREP(CMN_PLL_PPE_CLK_SEL, div)); + if (ret) + return ret; + + return clk_cmn_pll_ana_soft_reset(ppe_clk->regmap); +} + +static const struct clk_ops clk_ppe_ops =3D { + .recalc_rate =3D clk_ppe_recalc_rate, + .determine_rate =3D clk_nss_ppe_determine_rate, + .set_rate =3D clk_ppe_set_rate, +}; + +static struct clk_hw *ipq_cmn_pll_ppe_register(struct platform_device *pde= v, + struct regmap *regmap, + struct clk_hw *cmn_pll_hw) +{ + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + struct device *dev =3D &pdev->dev; + struct clk_init_data init =3D {}; + struct clk_cmn_pll *ppe_clk; + int ret; + + ppe_clk =3D devm_kzalloc(dev, sizeof(*ppe_clk), GFP_KERNEL); + if (!ppe_clk) + return ERR_PTR(-ENOMEM); + + init.name =3D "ppe-clk"; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_ppe_ops; + + ppe_clk->hw.init =3D &init; + ppe_clk->regmap =3D regmap; + + ret =3D devm_clk_hw_register(dev, &ppe_clk->hw); + if (ret) + return ERR_PTR(ret); + + return &ppe_clk->hw; +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; @@ -508,6 +586,9 @@ static int ipq_cmn_pll_register_clks(struct platform_de= vice *pdev) } else if (!strcmp(fixed_clk[i].name, "nss")) { hw =3D ipq_cmn_pll_nss_register(pdev, cmn_pll->regmap, cmn_pll_hw); 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The clock supports two modes: - UNIPHY mode (CMN_PLL_PON_MODE_SEL =3D 0): fixed 31.25 MHz output - PON mode (CMN_PLL_PON_MODE_SEL =3D 1): pll_rate / (2 * divider) The clock output can be independently enabled and disabled via the CMN_PLL_PON_EN bit. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 158 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 158 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 020ad12ca1f2..1ae32052b563 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -72,6 +72,11 @@ #define CMN_PLL_NSS_PPE_DIV_MIN 8 #define CMN_PLL_NSS_PPE_DIV_MAX 63 =20 +#define CMN_PLL_PON_CONFIG 0x42c +#define CMN_PLL_PON_MODE_SEL BIT(9) +#define CMN_PLL_PON_EN BIT(8) +#define CMN_PLL_PON_DIV_CTRL GENMASK(7, 0) + #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) =20 @@ -540,6 +545,155 @@ static struct clk_hw *ipq_cmn_pll_ppe_register(struct= platform_device *pdev, return &ppe_clk->hw; } =20 +/* + * PON (Passive Optical Network) reference clock operations. + * The PON refclk is derived from CMN PLL rate / 2, then divided by + * a configurable 8-bit divider (1-255). + */ +static int clk_pon_refclk_enable(struct clk_hw *hw) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + + return regmap_set_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_EN); +} + +static void clk_pon_refclk_disable(struct clk_hw *hw) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + + regmap_clear_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_EN); +} + +static int clk_pon_refclk_is_enabled(struct clk_hw *hw) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + + return regmap_test_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_EN); +} + +static unsigned long clk_pon_refclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + u32 val, div; + + regmap_read(pon_clk->regmap, CMN_PLL_PON_CONFIG, &val); + + /* Check if in UNIPHY mode (bit 9 =3D 0) - fixed 31.25 MHz */ + if (!(val & CMN_PLL_PON_MODE_SEL)) + return 31250000UL; + + /* PON mode: calculate from divider */ + div =3D FIELD_GET(CMN_PLL_PON_DIV_CTRL, val); + if (WARN_ON_ONCE(!div)) + return 0; + + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, 2ULL * div); +} + +static int clk_pon_refclk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long div; + + if (WARN_ON_ONCE(!req->rate)) + return 0; + + /* UNIPHY fixed mode */ + if (req->rate =3D=3D 31250000UL) + return 0; + + div =3D DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate, 2ULL * req->rat= e); + + /* Clamp to valid range (1-255) */ + div =3D clamp_t(unsigned long, div, 1, 255); + + req->rate =3D DIV_ROUND_CLOSEST_ULL((u64)req->best_parent_rate, 2ULL * di= v); + return 0; +} + +static int clk_pon_refclk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_cmn_pll *pon_clk =3D to_clk_cmn_pll(hw); + unsigned long div; + int ret; + + if (rate =3D=3D 0) + return -EINVAL; + + /* UNIPHY fixed mode (31.25 MHz) */ + if (rate =3D=3D 31250000UL) + return regmap_clear_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_MODE_SEL); + + div =3D DIV_ROUND_CLOSEST_ULL((u64)parent_rate, 2ULL * rate); + if (div =3D=3D 0 || div > 255) + return -EINVAL; + + /* Switch to PON mode */ + ret =3D regmap_set_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_MODE_SEL); + if (ret) + return ret; + + ret =3D regmap_update_bits(pon_clk->regmap, CMN_PLL_PON_CONFIG, + CMN_PLL_PON_DIV_CTRL, + FIELD_PREP(CMN_PLL_PON_DIV_CTRL, div)); + if (ret) + return ret; + + return clk_cmn_pll_ana_soft_reset(pon_clk->regmap); +} + +static const struct clk_ops clk_pon_refclk_ops =3D { + .enable =3D clk_pon_refclk_enable, + .disable =3D clk_pon_refclk_disable, + .is_enabled =3D clk_pon_refclk_is_enabled, + .recalc_rate =3D clk_pon_refclk_recalc_rate, + .determine_rate =3D clk_pon_refclk_determine_rate, + .set_rate =3D clk_pon_refclk_set_rate, +}; + +static struct clk_hw *ipq_cmn_pll_pon_refclk_register(struct platform_devi= ce *pdev, + struct regmap *regmap, + struct clk_hw *cmn_pll_hw) +{ + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + struct device *dev =3D &pdev->dev; + struct clk_init_data init =3D {}; + struct clk_cmn_pll *pon_clk; + int ret; + + pon_clk =3D devm_kzalloc(dev, sizeof(*pon_clk), GFP_KERNEL); + if (!pon_clk) + return ERR_PTR(-ENOMEM); + + init.name =3D "pon-clk"; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_pon_refclk_ops; + /* + * The PON reference clock may already be enabled by bootloader + * or consumed by hardware without an in-kernel client driver. + * Add CLK_IGNORE_UNUSED so the clock framework does not disable + * it when no consumer has claimed it. + */ + init.flags =3D CLK_IGNORE_UNUSED; + + pon_clk->hw.init =3D &init; + pon_clk->regmap =3D regmap; + + ret =3D devm_clk_hw_register(dev, &pon_clk->hw); + if (ret) + return ERR_PTR(ret); + + return &pon_clk->hw; +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; @@ -589,6 +743,10 @@ static int ipq_cmn_pll_register_clks(struct platform_d= evice *pdev) } else if (!strcmp(fixed_clk[i].name, "ppe")) { hw =3D ipq_cmn_pll_ppe_register(pdev, cmn_pll->regmap, cmn_pll_hw); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-314bc593b57sm621809eec.25.2026.07.24.08.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:00:31 -0700 (PDT) From: Luo Jie Date: Fri, 24 Jul 2026 08:00:29 -0700 Subject: [PATCH 07/12] clk: qcom: ipq-cmn-pll: Add EPHY-RAW clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-qcom_ipq5210_cmnpll-v1-7-a8b8679d215f@oss.qualcomm.com> References: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> In-Reply-To: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Luo Jie X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1784905224; l=3920; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=NpVN/Ozm8sANlDiqYWyTDjFt5f+smSHr7EMwKBYl4HQ=; b=jCZmtv0UvQjj2YoLx7Aya9S/E6GoSdbTGRjZldYrJXeKN/KCBgKTA9Ds5Zxtxp54N0yetlsC+ szcEt/ney9rDkmhXjLmGIP+vtg6W07LVN42ZINNJ54Ad6BnRTERxT++ X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-ORIG-GUID: d1xRcqFi95Hl53IVbSqG6I5awQt5YoHP X-Proofpoint-GUID: d1xRcqFi95Hl53IVbSqG6I5awQt5YoHP X-Authority-Analysis: v=2.4 cv=e/k2j6p/ c=1 sm=1 tr=0 ts=6a637e11 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=5v7W0TGBik0vBbtMqvUA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfXzF9f4LiJ0l0F zzxsFjzbRCGW7x/BUQaeUcKZUIji5ejui/DcIUzRMtEcl+P+5GQt5djAPSk2y81UJ7fZwQeSRp6 6g8ep530/pSWLxfLVobRD25lYeWKxfL096Fad1cPRCSU55IBczsxU+QzaAvsHe330rlCuvyGiGl XZOF/OaLChwLPT7wii545prH8fviToEuW1QxZbAjKUqO6vpYl742s1jUhhAAemYj7Rt8Tbj/zer WqnVBx2AbVWN6QvC14rstNFo9u0n8wXMtwAC1Yu8BZ5PBSvsylMfJm6mrc6OOiUSLT2VjJiH1+2 Z3kou4Buw3e6OFhULHvywBhlJgESfzCDyH8R2VPP1IKR6FsJYPRS0acMG0V0yUNY+OwAQusJkt/ QRR/NY68Jymt8Uom8bb4+zJdw2EzTHfbwoTjab3rLZFQNLTJyiHS1sZFNQC94QamI5XgGJDi/3O LyN+OOrpFjpmEY7mODA== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX2WEUUxzhasqa Cn+oDI5XHoKEfuuqWeQMEhU0uazult4Rs0U95bsdeG33OjdYqx0h9km3aj7wfFTx2VnmztEMzlG 9rIOoQtzMdjRYZC3WsjirGrp5w1Y3OY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240135 The EPHY-RAW clock is an IPQ5210-specific output from the CMN PLL that provides the raw reference clock to the SoC-integrated Ethernet PHY (EPHY), which supports up to 2.5G link speed. The output frequency is selected via bit 10 (CMN_PLL_GEPHY_312P5M_125M_SEL) of the CMN_PLL_PON_CONFIG register: - 0: 125 MHz - for 1G/100M/10M link speed - 1: 312.5 MHz - for 2.5G link speed Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 86 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 86 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 1ae32052b563..dfc28c12468b 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -76,6 +76,7 @@ #define CMN_PLL_PON_MODE_SEL BIT(9) #define CMN_PLL_PON_EN BIT(8) #define CMN_PLL_PON_DIV_CTRL GENMASK(7, 0) +#define CMN_PLL_GEPHY_312P5M_125M_SEL BIT(10) =20 #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) @@ -694,6 +695,87 @@ static struct clk_hw *ipq_cmn_pll_pon_refclk_register(= struct platform_device *pd return &pon_clk->hw; } =20 +/* + * EPHY-RAW clock operations for IPQ5210. + * The output clock rate is selected via bit 10 of CMN_PLL_PON_CONFIG: + * 0: 125 MHz (for 1G link speed) + * 1: 312.5 MHz (for 2.5G link speed) + */ +static unsigned long clk_ephy_raw_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_cmn_pll *ephy_raw_clk =3D to_clk_cmn_pll(hw); + u32 val; + + regmap_read(ephy_raw_clk->regmap, CMN_PLL_PON_CONFIG, &val); + + if (val & CMN_PLL_GEPHY_312P5M_125M_SEL) + return 312500000UL; + + return 125000000UL; +} + +static int clk_ephy_raw_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + if (req->rate <=3D 125000000UL) + req->rate =3D 125000000UL; + else + req->rate =3D 312500000UL; + + return 0; +} + +static int clk_ephy_raw_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_cmn_pll *ephy_raw_clk =3D to_clk_cmn_pll(hw); + + if (rate =3D=3D 125000000UL) + return regmap_clear_bits(ephy_raw_clk->regmap, + CMN_PLL_PON_CONFIG, + CMN_PLL_GEPHY_312P5M_125M_SEL); + + return regmap_set_bits(ephy_raw_clk->regmap, + CMN_PLL_PON_CONFIG, + CMN_PLL_GEPHY_312P5M_125M_SEL); +} + +static const struct clk_ops clk_ephy_raw_ops =3D { + .recalc_rate =3D clk_ephy_raw_recalc_rate, + .determine_rate =3D clk_ephy_raw_determine_rate, + .set_rate =3D clk_ephy_raw_set_rate, +}; + +static struct clk_hw *ipq_cmn_pll_ephy_raw_register(struct platform_device= *pdev, + struct regmap *regmap, + struct clk_hw *cmn_pll_hw) +{ + struct clk_parent_data pdata =3D { .hw =3D cmn_pll_hw }; + struct clk_cmn_pll *ephy_raw_clk; + struct device *dev =3D &pdev->dev; + struct clk_init_data init =3D {}; + int ret; + + ephy_raw_clk =3D devm_kzalloc(dev, sizeof(*ephy_raw_clk), GFP_KERNEL); + if (!ephy_raw_clk) + return ERR_PTR(-ENOMEM); + + init.name =3D "ephy-raw"; + init.parent_data =3D &pdata; + init.num_parents =3D 1; + init.ops =3D &clk_ephy_raw_ops; + + ephy_raw_clk->hw.init =3D &init; + ephy_raw_clk->regmap =3D regmap; + + ret =3D devm_clk_hw_register(dev, &ephy_raw_clk->hw); + if (ret) + return ERR_PTR(ret); + + return &ephy_raw_clk->hw; +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; @@ -747,6 +829,10 @@ static int ipq_cmn_pll_register_clks(struct platform_d= evice *pdev) hw =3D ipq_cmn_pll_pon_refclk_register(pdev, cmn_pll->regmap, cmn_pll_hw); + } else if (!strcmp(fixed_clk[i].name, "ephy-raw")) { + hw =3D ipq_cmn_pll_ephy_raw_register(pdev, + cmn_pll->regmap, + cmn_pll_hw); } else { continue; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-314bc593b57sm621809eec.25.2026.07.24.08.00.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:00:32 -0700 (PDT) From: Luo Jie Date: Fri, 24 Jul 2026 08:00:30 -0700 Subject: [PATCH 08/12] clk: composite: Export devm_clk_hw_register_composite_pdata Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-qcom_ipq5210_cmnpll-v1-8-a8b8679d215f@oss.qualcomm.com> References: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> In-Reply-To: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Luo Jie X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1784905224; l=749; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=KJR+wN2GxxX47mMq0L5v9qiUYbR7CJ2cgzDyV7M/EXA=; b=DRoCiALCPxHYfgApbZY8XM2JEu7UnvsJshHqGT5Wzcb0/ZfKVMybazdkOpoktKJK3sfTwIBlt mczsdlNRSK5AAwf6i0VJOS+7oLLv7ES55kGeFe8h4FmX0gyrKoKu10u X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX87my07dqpIYj Trbog1HJ93ZDdbOC8X3dJVM1IWAGyGGEhAea5+94vk43je88BH7Mcvv7vI2My2zQdDP10seGzba 9RmevEsHFExMjeSStGtmi9NR8kPBzdA= X-Authority-Analysis: v=2.4 cv=TvrWQjXh c=1 sm=1 tr=0 ts=6a637e14 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=Lly5wiSg1jk5MYLGpuEA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: jRoDyMXK7x0050olR8kF7UMfXXgjjU6Y X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX0zAoUM+KTLwg 7f4fRDn7JrxBd+6NsCey/DLmenW2qW/C/T0hgOdPp5wVfl2pz/9Rf2WHKW/w9fojQ9T+7zDlsoN NKC+W79X22O/khVZnQdEfr36BmhHKZ6z0Xh9wBaUO0gt2tZO6gdCXvA9le4KkB5bbItYdjpWJL2 IiR+67ymDA0VroLAVINEwkHc8qxE/qXDAZ0U+DD8qsvexdFezUc/efVyh1XM8IXR6nd8A57Ac7J A3AFyhsbI0mYJY5Be/GfCVluLgEfy0v4orM5YhOE3TxkVuH2VkgEawhVXD+oBWelkJXrKONsBdT oPizYgU75TiUiiDVmQpYFSWsv/rOZnDJk5fqdL396ceM1lfdJLnW88Yse4g0VpxRS/zs9Lfs0Zt 86D3SY7bwn3Nyi/f0t5VxJXDQrpy3frMEfPtQ+k87sBukKh1GWCJxS/F5USKnIJOig+Dhr+9QgP +cFNKx6LFH3dbhkwnPw== X-Proofpoint-ORIG-GUID: jRoDyMXK7x0050olR8kF7UMfXXgjjU6Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240135 devm_clk_hw_register_composite_pdata() is defined but not exported, preventing its use from loadable modules. Add EXPORT_SYMBOL_GPL() so that out-of-tree and built-as-module clock drivers can call it. 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-314bc593b57sm621809eec.25.2026.07.24.08.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:00:33 -0700 (PDT) From: Luo Jie Date: Fri, 24 Jul 2026 08:00:31 -0700 Subject: [PATCH 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-qcom_ipq5210_cmnpll-v1-9-a8b8679d215f@oss.qualcomm.com> References: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> In-Reply-To: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Luo Jie X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1784905224; l=5971; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=DLI8h6G0/NqwUS+zVGJ1siWTzN3VJ8p851OawG3o6CA=; b=mwC4Wq7Tq5UuKlPatOvvI0Da0Jmj3yyyj5EZBNcdk2c0PQvrKoVRF8CJRP5/Pl5nb38UDl1fr TSEHnMo38Y6CDBbzgM7DCBTa2/oCnrwi+RxMrGULj8AGnyeYJiUkhA1 X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-ORIG-GUID: 91XZ7djQGlORmzHjcmWO02TSlFNKjSU2 X-Proofpoint-GUID: 91XZ7djQGlORmzHjcmWO02TSlFNKjSU2 X-Authority-Analysis: v=2.4 cv=e/k2j6p/ c=1 sm=1 tr=0 ts=6a637e14 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=zP2XRvvY85Lzq-CNeuYA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX5zHVw6b4j8Yt f8ubQGRoeVcHjHhDECy+iyWBCjtBpIXNy7VSLuGe701hDtQqbSN9hO7i6rvNWipsbuIc6fYkEPW N8DLKCQKRi2pE+JAqIq6XBM4Gj5uGoXPFsF0YnQ1jrgTcsPFLY8v5bpUOohCeG8/ZevfFN3/8OQ y7zyO4KWYXODAH1zxQTGhExntkxWzy2bsxxcVdd3YhpCIKlkWHpYx3PBMC6xumFxuz7lO1xZ2K+ 2YE2JELvZq4YY1G1t/ijLXtUrkf4n4EL8CT0wfIQJw7mbxCalt50uh2B2x6jWmbylWICZ0Wcqke 8zm2kOMUJ4Vq3MBY0bi23qEQCqwhGwCW1WvKZr3OhWU3Ntt76mAr3fT/vKcWRNN+pDhSmSXW2Dv Nd9nUBF8QSiXt8lJSB3ovGgIsxMwbeuc7/HB8DQC+YuEhqL2BwqOgrN1QxDvIYunM6Ug/Q8J78G 9UEu0fOTejhvbyanWMg== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX59Hf1IMKOUDk pv9GMCtKlxXuxqHVJVX7cHKLwcUOiD0cORsDR9BHy46y5cDgAmADSC0SMKTmE1CPX0cTHgRsqmw oHgSXLMKw3Hw+BpiHbV8Y4UPa9MLh8Q= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240135 Some CMN PLL output clocks require a hardware gate in addition to a fixed rate. The gate control bits reside in the register CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered as a composite clock combining a clk_fixed_rate provider with a clk_gate. The enable_bit field is added to struct cmn_pll_fixed_output_clk (set to -1 for non-gated clocks). The CLK_PLL_OUTPUT_RAW() and CLK_PLL_GATE() helper macros are introduced alongside the existing CLK_PLL_OUTPUT(). The base MMIO address is added to struct clk_cmn_pll to allow gate clock registration to locate the output control register. Since CMN_PLL_OUTPUT_RELATED_1 is shared by all of these gate clocks, protect it with a single spinlock stored in struct clk_cmn_pll, so that concurrent enable and disable calls on different gate clocks correctly serialize their read-modify-write access to the shared register. Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 86 ++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 84 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index dfc28c12468b..00e243282b31 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -92,34 +92,62 @@ #define CMN_PLL_DIVIDER_CTRL 0x794 #define CMN_PLL_DIVIDER_CTRL_FACTOR GENMASK(9, 0) =20 +/* Clock gate enable bits. */ +#define CMN_PLL_OUTPUT_RELATED_1 0x79c +#define CLK25M_EN_BIT 15 +#define CLK50M_EN_BIT3_BIT 14 +#define CLK250M_EN_BIT 13 +#define CLK31P25M_EN_BIT 12 +#define CLK50M_EN_BIT 11 +#define CLK50M_EN_BIT2_BIT 10 + /** * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information * @id: Clock specifier to be supplied * @name: Clock name to be registered * @rate: Clock rate + * @enable_bit: Enable bit in CMN_PLL_OUTPUT_RELATED_1 for gate clock, + * -1 for non-gated clocks. */ struct cmn_pll_fixed_output_clk { unsigned int id; const char *name; unsigned long rate; + int enable_bit; }; =20 /** * struct clk_cmn_pll - CMN PLL hardware specific data * @regmap: hardware regmap. + * @base: register base address for gate clock registration + * @gate_lock: protects read-modify-write access to CMN_PLL_OUTPUT_RELATED= _1, + * which is shared by multiple gate clocks * @hw: handle between common and hardware-specific interfaces + * + * This structure is used for all CMN PLL-derived clocks including + * the main PLL, NSS clock, PPE clock, PON reference clock, and + * EPHY-RAW clock. */ struct clk_cmn_pll { struct regmap *regmap; + void __iomem *base; + spinlock_t gate_lock; struct clk_hw hw; }; =20 -#define CLK_PLL_OUTPUT(_id, _name, _rate) { \ +#define CLK_PLL_OUTPUT_RAW(_id, _name, _rate, _bit) { \ .id =3D _id, \ .name =3D _name, \ .rate =3D _rate, \ + .enable_bit =3D _bit, \ } =20 +#define CLK_PLL_OUTPUT(_id, _name, _rate) \ + CLK_PLL_OUTPUT_RAW(_id, _name, _rate, -1) + +#define CLK_PLL_GATE(_id, _name, _rate, _bit) \ + CLK_PLL_OUTPUT_RAW(_id, _name, _rate, _bit) + #define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw) =20 static const struct regmap_config ipq_cmn_pll_regmap_config =3D { @@ -368,6 +396,8 @@ static struct clk_hw *ipq_cmn_pll_clk_hw_register(struc= t platform_device *pdev) =20 cmn_pll->hw.init =3D &init; cmn_pll->regmap =3D regmap; + cmn_pll->base =3D base; + spin_lock_init(&cmn_pll->gate_lock); =20 ret =3D devm_clk_hw_register(dev, &cmn_pll->hw); if (ret) @@ -776,6 +806,50 @@ static struct clk_hw *ipq_cmn_pll_ephy_raw_register(st= ruct platform_device *pdev return &ephy_raw_clk->hw; } =20 +/* + * Register a composite clock that combines a fixed-rate clock with a gate. + * The gate control bit lives in CMN_PLL_OUTPUT_RELATED_1, which is shared + * across multiple gate clocks, so all of them must use the same lock. + */ +static struct clk_hw *ipq_cmn_pll_register_fixed_gate(struct device *dev, + const char *name, + struct clk_hw *parent_hw, + unsigned long rate, + void __iomem *base, + spinlock_t *lock, + u8 enable_bit) +{ + struct clk_parent_data pdata =3D { .hw =3D parent_hw }; + struct clk_fixed_rate *fixed; + struct clk_gate *gate; + + gate =3D devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + fixed =3D devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL); + if (!fixed) + return ERR_PTR(-ENOMEM); + + gate->reg =3D base + CMN_PLL_OUTPUT_RELATED_1; + gate->bit_idx =3D enable_bit; + gate->lock =3D lock; + + fixed->fixed_rate =3D rate; + + /* + * These gated clocks may be relied on by external hardware or + * bootloader-enabled paths without an in-kernel client driver. + * Add CLK_IGNORE_UNUSED so the clock framework does not disable + * them when no consumer has claimed them. + */ + return devm_clk_hw_register_composite_pdata(dev, name, &pdata, 1, + NULL, NULL, + &fixed->hw, &clk_fixed_rate_ops, + &gate->hw, &clk_gate_ops, + CLK_IGNORE_UNUSED); +} + static int ipq_cmn_pll_register_clks(struct platform_device *pdev) { const struct cmn_pll_fixed_output_clk *p, *fixed_clk; @@ -812,7 +886,15 @@ static int ipq_cmn_pll_register_clks(struct platform_d= evice *pdev) =20 /* Register the fixed rate output clocks. */ for (i =3D 0; i < num_clks; i++) { - if (fixed_clk[i].rate) { + if (fixed_clk[i].enable_bit !=3D -1) { + hw =3D ipq_cmn_pll_register_fixed_gate(dev, + fixed_clk[i].name, + cmn_pll_hw, + fixed_clk[i].rate, + cmn_pll->base, + &cmn_pll->gate_lock, + fixed_clk[i].enable_bit); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-314bc593b57sm621809eec.25.2026.07.24.08.00.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:00:35 -0700 (PDT) From: Luo Jie Date: Fri, 24 Jul 2026 08:00:32 -0700 Subject: [PATCH 10/12] clk: qcom: ipq-cmn-pll: Add all output clocks for IPQ5210 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-qcom_ipq5210_cmnpll-v1-10-a8b8679d215f@oss.qualcomm.com> References: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> In-Reply-To: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Luo Jie X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1784905224; l=2989; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=zD85P6LNvs+Wzn31QuiidOpUYjqw0x5J1/H7IesxRLc=; b=Q2q2ptGYFI+xtBfmNOhlqW3mJWAQCUQiuOtAQZIRbmS4WW4fQKPik+Fd4ApKXTikHou/S4VdU X+vnBENuFivDxqmGWBclAmQwafjAtdmi/cb6UpSfeHRc1q4ba6KphS8 X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfXycj5KkZfZyzK PzUyX1602xd0RS/h/hByvLlTfOnrlL/3q5Tf+hF4D9Q7Kqgq/F3wMAqi444jtof4tPgO1Sgf0p1 h1Cz0sO9d0THxKoOMhdO9l5G9awFUt0= X-Proofpoint-GUID: zlK3lvU_F6460QpMovMaBBLlaZLfFzgF X-Proofpoint-ORIG-GUID: zlK3lvU_F6460QpMovMaBBLlaZLfFzgF X-Authority-Analysis: v=2.4 cv=er/vCIpX c=1 sm=1 tr=0 ts=6a637e15 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=EC4oSUd80wHeU967I9AA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX5H1G5sD+lxdZ oZRbOAi3QfPyimfpIxJM2IeKiuyhNoMxbBCYGmJS3wwEC7MexAwbludze/8AsGb8BIYJ52beuzq 3jFFZ2s/TVqh+nGv+m4XupYK2nEPnHIAZKaEIGHue9do4sCXboETc2nsRGwizvFZa8dGoxmBEoh HSPqEuPfMCMSuBUxo2fFhE/5ImLEwsWD3hPTovmQFRMMFihmuA47N4/9GPOBC8M3nzqKTyX8fbQ NNS1H5tBaGwG++vtcE7uKZN5Cwf7ZWlfcTYxDAp+Fz20aA73s6I+dr+3jqccR2eYruHk4N8ZMGR q7m5cgBc5uDNCTdjgmgiyzrllw4sFDziJMiOz0I74i7/27dN4Xzw7r8jXJqW7FiJSV3NGjB4etX os7BmWOXbL8iD3GS3zinjAWD1JgQ6bw2hH3cBWm6boPs+xQL0l9n60WPyg8dWA9Ph+8YE1L35Yr 7MiguqkJSZsDmZ4pLlg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 clxscore=1015 bulkscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240135 Add the IPQ5210 output clock array and the device match table entry, wiring together all the infrastructure added in the previous patches. The IPQ5210 CMN PLL supplies 12 output clocks: Fixed-rate: XO 24 MHz, sleep 32 kHz Gated fixed-rate: PCS 31.25 MHz, ETH0/1/2 50 MHz, EPHY 50 MHz, ETH 25 MHz Configurable divider: NSS, PPE PON reference: PON (enable/disable + 8-bit divider) EPHY-RAW: 125/312.5 MHz select Signed-off-by: Luo Jie --- drivers/clk/qcom/ipq-cmn-pll.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c index 00e243282b31..902a222e4533 100644 --- a/drivers/clk/qcom/ipq-cmn-pll.c +++ b/drivers/clk/qcom/ipq-cmn-pll.c @@ -55,6 +55,7 @@ =20 #include #include +#include #include #include #include @@ -164,6 +165,22 @@ static const struct cmn_pll_fixed_output_clk ipq5018_o= utput_clks[] =3D { { /* Sentinel */ } }; =20 +static const struct cmn_pll_fixed_output_clk ipq5210_output_clks[] =3D { + CLK_PLL_OUTPUT(IPQ5210_XO_24MHZ_CLK, "xo-24mhz", 24000000UL), + CLK_PLL_OUTPUT(IPQ5210_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL), + CLK_PLL_GATE(IPQ5210_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL, CLK31P= 25M_EN_BIT), + CLK_PLL_GATE(IPQ5210_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL, CLK50M_EN_= BIT), + CLK_PLL_GATE(IPQ5210_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL, CLK50M_EN_= BIT2_BIT), + CLK_PLL_GATE(IPQ5210_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL, CLK50M_EN_= BIT3_BIT), + CLK_PLL_GATE(IPQ5210_EPHY_50MHZ_CLK, "ephy-50mhz", 50000000UL, CLK250M_EN= _BIT), + CLK_PLL_GATE(IPQ5210_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL, CLK25M_EN_BI= T), + CLK_PLL_OUTPUT(IPQ5210_NSS_CLK, "nss", 0), + CLK_PLL_OUTPUT(IPQ5210_PPE_CLK, "ppe", 0), + CLK_PLL_OUTPUT(IPQ5210_PON_REFCLK, "pon", 0), + CLK_PLL_OUTPUT(IPQ5210_EPHY_RAW_CLK, "ephy-raw", 0), + { /* Sentinel */ } +}; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-314bc593b57sm621809eec.25.2026.07.24.08.00.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:00:36 -0700 (PDT) From: Luo Jie Date: Fri, 24 Jul 2026 08:00:33 -0700 Subject: [PATCH 11/12] arm64: dts: qcom: ipq5210: Add CMN PLL device node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-qcom_ipq5210_cmnpll-v1-11-a8b8679d215f@oss.qualcomm.com> References: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> In-Reply-To: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Luo Jie X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1784905224; l=2855; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=NX5KasTfSKSbMXviS2FdTitdo/PZoLn00u5pTFfve+U=; b=gcQ7OhdE0DgGlhmsNp5bB83DWWLXlQAVb3RRgWRFGCxxWA1L+jSeziLbglT90osY6QuuO6AwQ S30eUzn984NDohmj1qfgNH239MNl04xUzEvSwIhOFMWQQPtTHNENHMw X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX/UMOAJeRTH1c mL/AL5MbgB7/8FGQv1zl3o4aqpLt2GODYbg8Bav1+O4kjauPI5m54EEOD6N62K6wU/EKroP1g6M WeOEtgqtfFJ+pESwUgxZJV3qqgwuKPdF2tZadHPqfla6dxwo2fmwTOxrXRBJQqn8F+Rr9IRxuu1 6b+MVt4M3Pc/FkhSIk96UZglENS43RnZcQ7TBfxHJgEBqlRNkQcD25vibbKCwCpMwuJHFMiPixU KC3Tio7mHxk9/RZhl76kSVne1u0RA9nzn5DO2k2nK30r9ydNCoLJFmLT2/72B+ktrVmNryCPE3K cbN5I0vzzDzk5nAxxZYD2do1rPotEU59yYLPa7JzOQTVTq6mQCtLbf4tZJDHTmX5FGLra4TUYxF HLINA4U85i3GCkpltGWZRLAGEJahC3i4vVk5XNEKoonUojDVDYBH8zleqef6zABBLXMNlMvtOId wH8xoniNFKK5kCNihgw== X-Proofpoint-GUID: pGzDXo3xdvS2pohuTlMxVFiywszvkmYT X-Proofpoint-ORIG-GUID: pGzDXo3xdvS2pohuTlMxVFiywszvkmYT X-Authority-Analysis: v=2.4 cv=F79nsKhN c=1 sm=1 tr=0 ts=6a637e17 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=ihdlGfXGyWBHLSVGZBMA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX7T3RiKLCOmmL QCpiaad5UzkJakQKFfepjwHcmgkuh0ZOFCo9zBANq0Y2PY7RHichH+o8gvdR06TlOTJ8JGUoRMb u4yTYvr5/cRLVKl11G392nAi4yLZIV8= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240135 Add CMN PLL node for enabling output clocks to the networking hardware blocks on IPQ5210 devices. The reference clock of CMN PLL is routed from XO to the CMN PLL through the WiFi block. XO (48 MHZ or 96 MHZ or 192 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 15 +++++++++++++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts index 941f866ecfe9..7410d092814e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -74,6 +74,21 @@ &uart1 { status =3D "okay"; }; =20 +/* + * The bootstrap pins for the board select the XO clock frequency that + * supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically + * enables the right dividers, to ensure the reference clock output + * from WiFi to the CMN PLL is 48 MHZ. + */ +&ref_48mhz_clk { + clock-div =3D <1>; + clock-mult =3D <1>; +}; + &xo_board { clock-frequency =3D <24000000>; }; + +&xo_clk { + clock-frequency =3D <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi index 2cdc10529c48..9bbd55cc1e75 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include =20 / { @@ -13,6 +14,12 @@ / { interrupt-parent =3D <&intc>; =20 clocks { + ref_48mhz_clk: ref-48mhz-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_clk>; + #clock-cells =3D <0>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -22,6 +29,11 @@ xo_board: xo-board-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; }; + + xo_clk: xo-clk { + compatible =3D "fixed-clock"; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-314bc593b57sm621809eec.25.2026.07.24.08.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 08:00:37 -0700 (PDT) From: Luo Jie Date: Fri, 24 Jul 2026 08:00:34 -0700 Subject: [PATCH 12/12] arm64: dts: qcom: Update IPQ5210 xo_board to use fixed factor clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-qcom_ipq5210_cmnpll-v1-12-a8b8679d215f@oss.qualcomm.com> References: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> In-Reply-To: <20260724-qcom_ipq5210_cmnpll-v1-0-a8b8679d215f@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, Luo Jie X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1784905224; l=1388; i=jie.luo@oss.qualcomm.com; s=20251128; h=from:subject:message-id; bh=wbagZecBaQaRTzpU5oWRY+OBJJnCD2znP6i38nr/QN4=; b=II2tJeI+QYrAlC0j4VnZRc0EEtf+s+4DoQ2s23PX28N451oypkU+KqQirS4y3dyrCa8XgagYz ENZHwYOcxEEACdz3lO8dJ2BdSOYHK+NC4EkY82URuCHEcJHcEQMvlXC X-Developer-Key: i=jie.luo@oss.qualcomm.com; a=ed25519; pk=gSsYMDakxtd6UDFYDdA9y9yjIs5Etp5GK/3DoXWPyS0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX5OK63V4TbUdc O/nJL6S8bUiZMBJuJPzY5PxjLP9JAD3B4GwdzwGyIMnGrBpMRq8q2MR/nhudfYprB2a3qZSzixX sejl15hih2UVO03nnUt8X5GuBgn5rZCJuEoP0EyK0zBTbvkk7NySSPeYdyVP+kKYATd88bAJ6qd YmwzYvjJ0MU4hkTnVDEZPh48bWgm/c/Udn6nd5vnmXwbp6hQW5rA2E5TJlma8yjXGN3B3QYErgf fjR4ZYGIljZckSNqcGGqbGtby4sbT9WCs/WZksBu5nMImfDhaXHBkvMAIetIJcc/EAGlVEFHIQx wi4PJRgx9jOWodVs+i5QQGH+3ijNeRuOEqfx9hNRnZc5qi98vk6n/Al5glrYY6BDEBOmwTQnTqW D4Sjrm2rgYr4RELlNL+EDAy2wp6A7e59pSyCrEYW8ZgyTkrSHdm3DnF6te5OhA2HQ6GIwUYmliP 0uSdw7z4xhIamADzntQ== X-Proofpoint-GUID: SSQH9ti8LuJb4BmrzuwySCHn6a4pv-4A X-Proofpoint-ORIG-GUID: SSQH9ti8LuJb4BmrzuwySCHn6a4pv-4A X-Authority-Analysis: v=2.4 cv=F79nsKhN c=1 sm=1 tr=0 ts=6a637e17 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=CPdYy-Otk887xBsD2wUA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDEzNSBTYWx0ZWRfX0HDhnIKNqjxj BaBjGGQZbEVJbxqZdV5vzJvRJiULMAqy8MJxzcyEYfzBbDuIOayqJRSy5AWKrYLBRBTX1175EI4 s3UpvFwLGRDFyp4yaZMyqs3G4TY/42Q= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_03,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240135 xo_board is fixed to 24 MHZ, which is routed from WiFi output clock 48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog block routing channel. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 7 ++++++- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts index 7410d092814e..fa537633d5f5 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -85,8 +85,13 @@ &ref_48mhz_clk { clock-mult =3D <1>; }; =20 +/* + * The frequency of xo_board is fixed to 24 MHZ, which is routed + * from WiFi output clock 48 MHZ divided by 2. + */ &xo_board { - clock-frequency =3D <24000000>; + clock-div =3D <2>; + clock-mult =3D <1>; }; =20 &xo_clk { diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi index 9bbd55cc1e75..45026f7835bf 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -26,7 +26,8 @@ sleep_clk: sleep-clk { }; =20 xo_board: xo-board-clk { - compatible =3D "fixed-clock"; + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_clk>; #clock-cells =3D <0>; }; =20 --=20 2.43.0