From nobody Fri Jul 24 21:53:26 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C330E3FADFA for ; Fri, 24 Jul 2026 09:54:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784886897; cv=none; b=Lrj9Q0zLcKQsiE1WD+mi7g90r3Wf8ZraX4wfm1iLDkGPaEMHy6f9CT0HO3oucgExuJS+n2PQuHpWrT5ZcTJtRlTXKByw6UB7gCzA47ZKJdlfIqFWQsEbDfjPIJKLGLviTpvORvqp0opyZEefEjtKRWQ1IdY6QIou50siB7U+hdo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784886897; c=relaxed/simple; bh=Xc4PXMaoYldFY9uHwsgJyrcRAuOBTYgT1lD6R3KdCfo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FKfErhxUbnnU8HeUsW6tn0Q5TahtQrTRmtqF62CoS5ZaYY4HOwuoY1hosOt83qfJTnmkmK8mKl/HeZli9IcPBuZCVYA21BsZeFWixkTNakmU7mqa94VTH6SzLMTu9+DnA5u9M0njw5pop3JZKXzvjnGx/GOW3NxjOpnhsC5JEME= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=FEwASyY8; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=AKnkkIfq; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="FEwASyY8"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="AKnkkIfq" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66O9T4863786092 for ; Fri, 24 Jul 2026 09:54:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= QH8MfES3pr72T5irLL292Vri+hNWh1CPgEIsdIlnYgE=; b=FEwASyY8gd+qSQIU 1LD7jzcdivCPSiWjI+wanlhVQB+fn8i1AgeaMMmw1ieKf0KOiJl4wnVDhKLnLiHf m/cJOl7R3SzM/ZQSaFLcp/UYqo7izlO/znWsvinivqmUg/1z8ubrzI/EJZkxhuVH x4QYbhQXZ5rupdnK1VByGD+6/TtpGqQYPJSbAnjUBQWtpxn4X1o4mwQUGPT33gV8 Ma5KEULWzSu0dMEEPKhllLoVDV/0Y8xFoETE4la25nlFbmjRCa8+M4LmfxvNz5db 5KM98NzxsO+AZjKc8d6/FygyucqeIWXwvLklL0CkK+d05loeOExwG4eRfQX3xqdv d2eeeg== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fm5f68348-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 24 Jul 2026 09:54:54 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-cbb467e56aaso281524a12.1 for ; Fri, 24 Jul 2026 02:54:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784886894; x=1785491694; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=QH8MfES3pr72T5irLL292Vri+hNWh1CPgEIsdIlnYgE=; b=AKnkkIfq2N292jDOwcYb3oAWtpIuWIt/1fWEKxYnZIrZF5OltiG5gLvx24M+hZGXWE jLWDjwlZX62haASx7EFWYg7eR70ChJnKPZMy5pJo50CMBodJvKCzrC619MBMlSyiMAqY 1EfEa2XqVHjCzVCEBh1/6KZtcebTq9x2/HZylkwsa1NZFIz6AK0M8wIRJofKhCrtl+Kd EaVltqupK6Yfsun+AhHuYf4YvH8N4L9WxyjlIa441thDIm26CHTYsyiAQwqBMKHI2a// qVOluh1MBZdv6jWJyep+tmnpMMGLh9011dRA8QL1IhtSCyhgWKc/8AceAPyhkQ0JVnmG sP1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784886894; x=1785491694; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=QH8MfES3pr72T5irLL292Vri+hNWh1CPgEIsdIlnYgE=; b=RICmKUw8Bs2g+fspy8zGq9eckwI4dOAJvLCtHa5IbKkE91qRvlw+Mclg1MZhs3EQRe c+kYdBLDJR0ypgutmN0ZpAoE4P24kTr2bnEKyFIahvvR6riZsU1qMQSHXac4zHgphxam WbC3QCRpKFA6CKcuTgHCpJcvADw7TL8/AA9ArCNiZBWz5eoEfdJYlELB+EWOFCgzdf4w zeFtJloEkT9iAgn7m5qX3+y2XJeKeCuyEuVAhvBM5+z0LbR6cTgdhOkqBA28iyTPvx+H BEZjm4Jn9l38U1EUuk3Qv4LyKqw4L9oAhWA7yM956DoLmGSkN7Hq+Ev2xTd/kST7ybcM 1ysA== X-Forwarded-Encrypted: i=1; AHgh+RovmsZHWWRNWodejbUT6TOcdx15SMi6Jh8AB7vxdfsX3a1YqHsp2pN3MyoqNV7vUIk3TtcpL5PTUzLsAsg=@vger.kernel.org X-Gm-Message-State: AOJu0Ywg+UDr/0OEF3SkEJ5cxwN2VToLrcHjkl4JTSXw43BPBmVfXy98 rm+nokpSnR2H7WOe9SUqsnStlcS3TCFQ25tuEtlpT8/qPhVB2RtBuTqDsMGzJFrK/k46DO9d/gf r31HNWja5OjwM7hXw4rLX3a+5/Y+RfhgfvdEz9b14kLts6r7R7z2W3dww0eNWK0JLrAo= X-Gm-Gg: AR+sD12tbfw4HWI2S2ClZ6A/HZBoqopRi/sLw9zt7w0HxtWgzIyxSrXUxor9SEHa5K4 3DLbuXCjuirmDioh6wOeRbMye69cItgQCcfX687LZDZyzBcYfFdOCehJK+DimYoSKw/YDXv6EEH R2OhGa5bidLhKzmhopg3Zl6IJfToaJ2dg4dqDRbjF+W9nBXymq2yWKbNZtWFYDYUOHA2iq+Esai DW77mmXtYz5/Kda+zcnwKH4Xeb9qHARsLiQaCDzrcpo1N+/pmJx+Tv+l0w1M5aznSmi13PGLyDX pVSs4wujhh/9aNYId9NDrbHPg2av1GiNC9LyIT3DiimWExDeAzME1wzLJPOfm1Y/P2guO8qBgsA zTSOVDgmDh/pbdKPOsCoe/5PtFUH5MjbuhCx/5PdqVC02Qi3HC4pjyPXhiODLhErD5M+RH3zdKH GrFrLNNgtgcHUNQVYCe4vWUboRFQr62g== X-Received: by 2002:a05:6a20:938c:b0:3bf:b6e3:fbe1 with SMTP id adf61e73a8af0-3c44b1fc81emr8556031637.55.1784886893974; Fri, 24 Jul 2026 02:54:53 -0700 (PDT) X-Received: by 2002:a05:6a20:938c:b0:3bf:b6e3:fbe1 with SMTP id adf61e73a8af0-3c44b1fc81emr8555998637.55.1784886893496; Fri, 24 Jul 2026 02:54:53 -0700 (PDT) Received: from hu-varada-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3147e1b6a45sm28975093eec.28.2026.07.24.02.54.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 02:54:53 -0700 (PDT) From: Varadarajan Narayanan Date: Fri, 24 Jul 2026 15:24:44 +0530 Subject: [PATCH v4 1/3] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-08-dts-v4-1-65e61a1061f0@oss.qualcomm.com> References: <20260724-08-dts-v4-0-65e61a1061f0@oss.qualcomm.com> In-Reply-To: <20260724-08-dts-v4-0-65e61a1061f0@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDA5MCBTYWx0ZWRfXysNUVqvgeMIQ CHRYP8oS7avZH/DdXf6UcnUnzQfOSTDNLbGCFmSP6Ea5ZrCLO97wg4L+agENUGQdeMXajT5lNk6 dIlwEjwpeXM6YIPtWVTygazFZVT0DsI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDA5MCBTYWx0ZWRfX+YqUrbPOCo+i 46lodLiP53ZRGlmEZZck8U9CZCZZG+lNvq3KZzDdoHNFwAaS5d/xuH679mCnxA0SOenlT12YrzT t1MLbkpxQ5TpyoTEzyetIN+joKQwz31usOSb0F1jljFA+2znjiMpz188p9VTh8RvVegjK0JKcqR Gyfx45X4fnu3RNqpxZa+Xm7bPyLm6Uy0MSyxp2wO/XOGaZeq9dYiQvbq9Nb2wcbWq4Uy0O7vOoU 6y8LN+VPKHiDFXgw7PCOqfm1ZVHRJlO79c6/xJudgi7LjOkKHh96/yrTW0atbuM0gsCTeNAUhrC 6gnDpPm24Z9giSJf9gyj8cODhGXP0nZi5XHYdicjTsWkiMm2k6NYuaEGggKaBaVx6VHgRhphHDC gRghjVlQT8c0PrJ4YgFUCAhwDv2ua32HmDLweOaoEKcz+Qd74kcLhU2q9rnd8TIjmTmx9mx8ayQ OEMeCwJvCVANCDsv4rA== X-Proofpoint-GUID: T8VgwdhtaEiUG6uqOFnVt6BhEoXZA8ea X-Authority-Analysis: v=2.4 cv=BNeDalQG c=1 sm=1 tr=0 ts=6a63366e cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=a-56kPbHyNSDQn79x5kA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-ORIG-GUID: T8VgwdhtaEiUG6uqOFnVt6BhEoXZA8ea X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_01,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 adultscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240090 Describe common IPQ5210 SoC peripherals in the base DTSI so board DTS files can enable the hardware they use. Add nodes for USB, PCIe, QPIC NAND/BAM, QFPROM, TSENS and thermal zones. Also describe the CPU OPP table and CPU cooling cells needed for CPU frequency scaling and thermal throttling. Signed-off-by: Varadarajan Narayanan --- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 605 ++++++++++++++++++++++++++++++= +++- 1 file changed, 599 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi index 20e8b240642c..161b5bb5a7f7 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -4,8 +4,11 @@ */ =20 #include +#include #include +#include #include +#include =20 / { #address-cells =3D <2>; @@ -28,36 +31,48 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 =3D <&cpu_opp_table>; }; =20 - cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 =3D <&cpu_opp_table>; }; =20 - cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x2>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 =3D <&cpu_opp_table>; }; =20 - cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x3>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 =3D <&cpu_opp_table>; }; =20 l2_0: l2-cache { @@ -84,6 +99,40 @@ memory@80000000 { reg =3D <0x0 0x80000000 0x0 0x0>; }; =20 + cpu_opp_table: opp-table-cpu { + compatible =3D "operating-points-v2-kryo-cpu"; + opp-shared; + nvmem-cells =3D <&cpu_speed_bin>; + + opp-816000000 { + opp-hz =3D /bits/ 64 <816000000>; + opp-supported-hw =3D <0x3>; + opp-microvolt =3D <850000>; + clock-latency-ns =3D <200000>; + }; + + opp-1008000000 { + opp-hz =3D /bits/ 64 <1008000000>; + opp-supported-hw =3D <0x3>; + opp-microvolt =3D <850000>; + clock-latency-ns =3D <200000>; + }; + + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-supported-hw =3D <0x3>; + opp-microvolt =3D <850000>; + clock-latency-ns =3D <200000>; + }; + + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-supported-hw =3D <0x1>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <200000>; + }; + }; + pmu { compatible =3D "arm,cortex-a53-pmu"; interrupts =3D ; @@ -130,6 +179,170 @@ soc@0 { dma-ranges =3D <0 0 0 0 0x10 0>; ranges =3D <0 0 0 0 0x10 0>; =20 + qusb_phy_0: phy@7b000 { + compatible =3D "qcom,ipq5210-qusb2-phy", "qcom,ipq6018-qusb2-phy"; + reg =3D <0x0 0x0007b000 0x0 0x180>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board>; + clock-names =3D "cfg_ahb", + "ref"; + + resets =3D <&gcc GCC_QUSB2_0_PHY_BCR>; + status =3D "disabled"; + }; + + ssphy_0: phy@7d000 { + compatible =3D "qcom,ipq5210-qmp-usb3-phy", "qcom,ipq9574-qmp-usb3-phy"; + reg =3D <0x0 0x0007d000 0x0 0xa00>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_USB0_AUX_CLK>, + <&xo_board>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets =3D <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names =3D "phy", + "phy_phy"; + + #clock-cells =3D <0>; + clock-output-names =3D "usb0_pipe_clk"; + + status =3D "disabled"; + }; + + pcie0_phy: phy@84000 { + compatible =3D "qcom,ipq5210-qmp-gen3x1-pcie-phy"; + reg =3D <0x0 0x00084000 0x0 0x1000>; + + clocks =3D <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names =3D "aux", "cfg_ahb", "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE0_AUX_CLK>; + assigned-clock-rates =3D <20000000>; + + resets =3D <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names =3D "phy", "common"; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie0_pipe_clk"; + + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + pcie1_phy: phy@f4000 { + compatible =3D "qcom,ipq5210-qmp-gen3x2-pcie-phy", + "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg =3D <0x0 0x000f4000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_PIPE_CLK>; + clock-names =3D "aux", "cfg_ahb", "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE1_AUX_CLK>; + assigned-clock-rates =3D <20000000>; + + resets =3D <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names =3D "phy", "common"; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie1_pipe_clk"; + + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + efuse@a4000 { + compatible =3D "qcom,ipq5210-qfprom", "qcom,qfprom"; + reg =3D <0x0 0x000a4000 0x0 0x741>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_speed_bin: cpu-speed-bin@28 { + reg =3D <0x28 0x1>; + bits =3D <0 8>; + }; + + tsens_sens11_off: s11@3dd { + reg =3D <0x3dd 0x1>; + bits =3D <4 4>; + }; + + tsens_sens12_off: s12@3de { + reg =3D <0x3de 0x1>; + bits =3D <0 4>; + }; + + tsens_sens13_off: s13@3de { + reg =3D <0x3de 0x1>; + bits =3D <4 4>; + }; + + tsens_sens14_off: s14@3e5 { + reg =3D <0x3e5 0x2>; + bits =3D <7 4>; + }; + + tsens_sens15_off: s15@3e6 { + reg =3D <0x3e6 0x1>; + bits =3D <3 4>; + }; + + tsens_mode: mode@419 { + reg =3D <0x419 0x1>; + bits =3D <0 3>; + }; + + tsens_base0: base0@419 { + reg =3D <0x419 0x2>; + bits =3D <3 10>; + }; + + tsens_base1: base1@41a { + reg =3D <0x41a 0x2>; + bits =3D <5 10>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,ipq5210-tsens", "qcom,ipq5332-tsens"; + reg =3D <0x0 0x004a9000 0x0 0x1000>, + <0x0 0x004a8000 0x0 0x1000>; + nvmem-cells =3D <&tsens_mode>, + <&tsens_base0>, + <&tsens_base1>, + <&tsens_sens11_off>, + <&tsens_sens12_off>, + <&tsens_sens13_off>, + <&tsens_sens14_off>, + <&tsens_sens15_off>; + nvmem-cell-names =3D "mode", + "base0", + "base1", + "tsens_sens11_off", + "tsens_sens12_off", + "tsens_sens13_off", + "tsens_sens14_off", + "tsens_sens15_off"; + interrupts =3D ; + interrupt-names =3D "combined"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <5>; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5210-tlmm"; reg =3D <0x0 0x01000000 0x0 0x300000>; @@ -146,8 +359,8 @@ gcc: clock-controller@1800000 { reg =3D <0x0 0x01800000 0x0 0x40000>; clocks =3D <&xo_board>, <&sleep_clk>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>; #clock-cells =3D <1>; @@ -205,6 +418,87 @@ sdhc: mmc@7804000 { status =3D "disabled"; }; =20 + qpic_bam: dma-controller@7984000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x0 0x07984000 0x0 0x1c000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QPIC_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + status =3D "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible =3D "qcom,ipq5210-snand", "qcom,ipq9574-snand"; + reg =3D <0x0 0x079b0000 0x0 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names =3D "core", + "aon", + "iom"; + + dmas =3D <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names =3D "tx", + "rx", + "cmd"; + + status =3D "disabled"; + }; + + usb3: usb@8a00000 { + compatible =3D "qcom,ipq5210-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x08a00000 0x0 0x200000>; + + clocks =3D <&gcc GCC_CNOC_USB_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks =3D <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates =3D <200000000>, + <24000000>; + + interrupts-extended =3D <&intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "qusb2_phy", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + phys =3D <&qusb_phy_0>, + <&ssphy_0>; + phy-names =3D "usb2-phy", + "usb3-phy"; + + resets =3D <&gcc GCC_USB_BCR>; + + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + + status =3D "disabled"; + }; + intc: interrupt-controller@b000000 { compatible =3D "qcom,msm-qgic2"; interrupt-controller; @@ -244,6 +538,24 @@ watchdog@b017000 { clocks =3D <&sleep_clk>; }; =20 + apcs_glb: mailbox@b111000 { + compatible =3D "qcom,ipq5210-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg =3D <0x0 0x0b111000 0x0 0x1000>; + #clock-cells =3D <1>; + clocks =3D <&a53pll>, <&xo_board>, <&gcc GPLL0>; + clock-names =3D "pll", "xo", "gpll0"; + #mbox-cells =3D <1>; + }; + + a53pll: clock@b116000 { + compatible =3D "qcom,ipq5210-a53pll"; + reg =3D <0x0 0x0b116000 0x0 0x1000>; + #clock-cells =3D <0>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + timer@b120000 { compatible =3D "arm,armv7-timer-mem"; reg =3D <0x0 0x0b120000 0x0 0x1000>; @@ -307,6 +619,287 @@ frame@b128000 { status =3D "disabled"; }; }; + + pcie1: pcie@50000000 { + compatible =3D "qcom,pcie-ipq5210", "qcom,pcie-ipq9574"; + reg =3D <0x0 0x50000000 0x0 0xf1c>, + <0x0 0x50000f20 0x0 0xa8>, + <0x0 0x50001000 0x0 0x1000>, + <0x0 0x000f0000 0x0 0x3000>, + <0x0 0x50100000 0x0 0x1000>, + <0x0 0x000f6000 0x0 0x1000>; + reg-names =3D "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + bus-range =3D <0x00 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x0 0x0 0x50200000 0x0 0x00100000>, + <0x02000000 0x0 0x0 0x0 0x50300000 0x0 0x0fd00000>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks =3D <&gcc GCC_PCIE1_AXI_M_CLK>, + <&gcc GCC_PCIE1_AXI_S_CLK>, + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE1_RCHNG_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>; + clock-names =3D "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets =3D <&gcc GCC_PCIE1_PIPE_ARES>, + <&gcc GCC_PCIE1_CORE_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_ARES>, + <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_M_ARES>, + <&gcc GCC_PCIE1_AUX_ARES>, + <&gcc GCC_PCIE1_AHB_ARES>; + reset-names =3D "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects =3D <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>, + <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + status =3D "disabled"; + + pcie1_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie1_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie0: pcie@70000000 { + compatible =3D "qcom,pcie-ipq5210", "qcom,pcie-ipq9574"; + reg =3D <0x0 0x70000000 0x0 0xf1c>, + <0x0 0x70000f20 0x0 0xa8>, + <0x0 0x70001000 0x0 0x1000>, + <0x0 0x00080000 0x0 0x3000>, + <0x0 0x70100000 0x0 0x1000>, + <0x0 0x00086000 0x0 0x1000>; + reg-names =3D "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + bus-range =3D <0x00 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x0 0x0 0x70200000 0x0 0x00100000>, + <0x02000000 0x0 0x0 0x0 0x70300000 0x0 0x0fd00000>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks =3D <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>; + clock-names =3D "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets =3D <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_ARES>, + <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_M_ARES>, + <&gcc GCC_PCIE0_AUX_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>; + reset-names =3D "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects =3D <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>, + <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + status =3D "disabled"; + + pcie0_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie0_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + }; + + thermal_zones: thermal-zones { + ethphy-thermal { + thermal-sensors =3D <&tsens 11>; + + trips { + ethphy-critical { + temperature =3D <125000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + }; + }; + + pon-uniphy-thermal { + thermal-sensors =3D <&tsens 12>; + + trips { + pon-uniphy-critical { + temperature =3D <125000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + }; + }; + + nss-top-thermal { + thermal-sensors =3D <&tsens 13>; + + trips { + nss-top-critical { + temperature =3D <125000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + }; + }; + + cpu0-thermal { + thermal-sensors =3D <&tsens 14>; + + trips { + cpu-critical { + temperature =3D <120000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + + cpu0_thermal_alert: cpu-passive { + temperature =3D <110000>; + hysteresis =3D <9000>; + type =3D "passive"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu0_thermal_alert>; + /* Set maximum frequency as 816 MHz */ + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + thermal-sensors =3D <&tsens 15>; + + trips { + cpu-critical { + temperature =3D <120000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + + cpu-passive { + temperature =3D <110000>; + hysteresis =3D <9000>; + type =3D "passive"; + }; + }; + }; }; =20 timer { --=20 2.34.1 From nobody Fri Jul 24 21:53:26 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5B7E41D624 for ; Fri, 24 Jul 2026 09:54:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784886902; cv=none; b=mJB8C57FE8LdSiT/qDSQDRto691GoNeCO5qeGEUcLJSzp0ES+0M1TTfF8Un2tTUX4KGHoOOefwpeFWCoz3zWDUltgnt4YXb+ms9feAM1v0KqZ/2moy1Fp2WCQQlNl2hpsUhKA4OZ7Pj9MGxkWXlP+hMVGibUjkfK5dCTXlXHsGU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784886902; c=relaxed/simple; bh=qcVLJczhLVF77VjvKP3+H0o12u0hwIN/GBWxg/eWzGo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cTFDBaaHuzHXcjLIKAFC39Iw5hhNpegPd+LPvYnyD5fktguY7grS4vTki2B1JCC79YjwOs50kwaoITsXvPORuvK92uhkgRju74UvyaBp1K8jKCZEXeRmE+o6tnVHsvg7IVwYKPeQ8m7P8JSxBWyrk028DQm45fahmE0ZQEIrNyY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ZxFIYv3q; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=QFlkdjUE; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ZxFIYv3q"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="QFlkdjUE" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66O9MENn2754960 for ; Fri, 24 Jul 2026 09:54:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= QJ+XG8fKARImpjXxnXkd7ors2tn1d27g2wgp4VBamlo=; b=ZxFIYv3qVWW6oXEs adkORp+bL4RY51VpA/lXOTtn/j/7GnXHSycD0uaplDA8S8lz2TLUetVGc0SqoWQW qP5NEnY9BEBQh4PvRj459KKqlLvci36vOrGoVj07MR8FX8XRaW1dakIgKSXZTJ8A kcKdFMJ9rO4ZHAeWFRzVlYSVlkKIzitzq3dpFVboPvCXFLXmGFz5BoTmaPPZw1S+ nRDAOlTMEjERq8m8p10xHZGnAQlXMv1QIoykVbxb3bWJgeZFHSOx5YocwGEfjkbe RY1gpAmRCVNJbt6Egd0AHiKMbzc0XcReZdy/uo8jLuhZ2Z22Wr+f7ATCthMhrls0 C0Gxww== Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fm5byr3y0-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 24 Jul 2026 09:54:58 +0000 (GMT) Received: by mail-pg1-f197.google.com with SMTP id 41be03b00d2f7-cbb467e56aaso281556a12.1 for ; Fri, 24 Jul 2026 02:54:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784886898; x=1785491698; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=QJ+XG8fKARImpjXxnXkd7ors2tn1d27g2wgp4VBamlo=; b=QFlkdjUEJ7XYywRAi5zPqMf107bP2op5i8mJ0x7qR3//NGs1mSj2babG9rbzsrBqiK mqD/6FFpZASy3YOoQ9c0/14LzWvq2JESZRN4xdKeQGSuL0rUNoppFh4+anwtlaGWnsYT fNF9bvtAgzP9l7Qc78LRWsktN0PpqnvSsPym/t+jxRtWsMUgPH3akoJ2zD66gYyv32eb N6YgQENFIGRSdRM5PG2f+8IFxU/LRTiLDbCSkX+N2Vv2hyOniQbbonFd2S13+MvEeeoz q6XBoZIcQqIVqE91pzGTPXRwLInHtNU7kDbB0SJpJhF+ZahmC2SvWtl5J7wBWSyxn5JX LAoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784886898; x=1785491698; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=QJ+XG8fKARImpjXxnXkd7ors2tn1d27g2wgp4VBamlo=; b=RTwIodtuw0vQyDqVcllc3yce+fRbCbMwdpqCxInnDUPsa3qqOw+CE9+Fn3i05nKL/C N10fN5jGk7LxtiiuGih4yop/f39y8Hn+INqr0P8Y7NZULo83JgqOCK1DHOQJ7Uzt8YBI KEoUUflvWJ98qYWNZu6b+MrnIFAwgDrl1RM13mLJACKYLmPSytsX4CkgKwzjwvp5XPIr sQ/byHWjgCi4oC2V2PLChDLwCpcLK5uOJW06QjggMctLdmsJLD7D+2M6YV7HDXKDJwLx gTOIfIwpFNMXRHl3QBpt4P6EIVnWHvy2uz3DQiqByRBt7lBhGoca3aKp7zRbzloFKCPd UElg== X-Forwarded-Encrypted: i=1; AHgh+Ro/iFDuaOHxQwesMzp8ZMhpmXlEnOq/rli2OzIi0yxCUEnbjNznFjzVVMtLaHM/XGS+cOrUp0LEbEqyTmo=@vger.kernel.org X-Gm-Message-State: AOJu0YzZj91IEICIDVYHUoZk0sqciBYD0qDrmVeXq6AdstQKhv92bfPt gEsxJ95QDNwcwYk+1tFay1Unoq/uT7HlXpVkpNekotdjvFDugFiAluhX6Q7e6gxMmfZL9muck68 NFPvfyuIZympBWinaRmbrVTNiXjXctDoWwuo2AaAqMyXd2cq6iFIXHzvou0izaLGbcsA= X-Gm-Gg: AR+sD12HfABpUK5wovFXlrur0zmm+/WjPyyhIVAQqH/YglJusj+npQ6WA1w+xj7aQ7/ aMVkEJL7wKDouSlZ1yv/07TX7hy9fhJVKShfnCW5D13TiTMJ75SMlf3CMCAYaKBQ1Ri5YbDZW8K 78PzUVVuuBCJ9ZPoSsepWDNABJKAoYe+pckZTkDGo1JBW7KnHGm25X+6wMODZ5X2nEtrxeYtHAy kURe19a97OzhkXyCmi46LyQRxWUvU4OBqh7Y3cYlUXo7v1fivVUInYOqhmf/pcdUeMVGaJWuqV3 s58QezCI+tzMYQwgKkC+Mt2BqNpdRwY/Bm8q5gqMbBfVrDaY/ntn9W3/L7sfz2bM6D/Gr2h2DuO NrlM2Yekot2jljq1bwHVjJd9RPneYtATqjR2Mznyv8FulUgQY16NDj8LTIbHwouLkqZgglFwSHl bX06h5eQvgkz6bbOEVAvRnMVDr7xTFMw== X-Received: by 2002:a05:6a21:e8b:b0:3bf:6011:53b with SMTP id adf61e73a8af0-3c44b18c993mr7612955637.38.1784886897587; Fri, 24 Jul 2026 02:54:57 -0700 (PDT) X-Received: by 2002:a05:6a21:e8b:b0:3bf:6011:53b with SMTP id adf61e73a8af0-3c44b18c993mr7612929637.38.1784886897132; Fri, 24 Jul 2026 02:54:57 -0700 (PDT) Received: from hu-varada-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3147e1b6a45sm28975093eec.28.2026.07.24.02.54.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 02:54:56 -0700 (PDT) From: Varadarajan Narayanan Date: Fri, 24 Jul 2026 15:24:45 +0530 Subject: [PATCH v4 2/3] arm64: dts: qcom: ipq5210: Introduce RDP504 common DT file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-08-dts-v4-2-65e61a1061f0@oss.qualcomm.com> References: <20260724-08-dts-v4-0-65e61a1061f0@oss.qualcomm.com> In-Reply-To: <20260724-08-dts-v4-0-65e61a1061f0@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: XMFyecpxRIpf1dz4qsOWcyITxg1K93lU X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDA5MCBTYWx0ZWRfX2KOvjhVl5+46 G50S9HX7bZ0NVuQp87PsElR6YZAVAYqG4JC/P6+a8zZ+kMtbmONBRIdrGq1Bj0vg9G2byMBshoe qf5HLxcDnWOiSUsFm9bDXRi+kkEPJQ4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDA5MCBTYWx0ZWRfX20GmXMi+odPz apdMsDc/ijz9ZxLnEKXdZLS2YcBkXWaO453IdfHqitI6gw01L6j2iUnIgmydQNt3YA7y6XUZ3kY TzJZoginAaCKDIWWk/mdJn9PaEC947LU4J7Bgyxm9W2U4Avr/jD/J+R8DerjuXrOrOm3D4WIF3+ /sUWyqq3E4GUYZZ5fmvvNh6DL4A6H/h2Q80Jah1pTQ5omRsNtsbvWOgP795Q268Mj5pkWTv+QVf 3yzFC1hsnfN88wNimebCgQOCTefes2GjiRW9ylp13ciMbn8B5IyJqT6tQGNFMRDrE10aFUMu29d Ucg27P5vvVa37aPwlnpV/qd3E3T3Ey3DfESFwVHBPl3PCuXKgRNMBIUtNGHHCNAGLHddwgx5qJA dnccGm3Wnw1ve4o+n9wcugphsX7hXS1WyZP5uw+jvaelJVRDTMJ2f19BnbR/CWqpA3G9FCyzAQX 2pgBXcK7++w4QqQzzWw== X-Proofpoint-GUID: XMFyecpxRIpf1dz4qsOWcyITxg1K93lU X-Authority-Analysis: v=2.4 cv=GMA41ONK c=1 sm=1 tr=0 ts=6a633672 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=sBhH8NEu279NYU_71NoA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_01,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240090 RDP504 has USB, PCIe and SPI NAND devices populated. EMMC and NAND share the GPIOs. The board has to be reworked to change from EMMC to NAND variant. Rename ipq5210-rdp504.dts as ipq5210-rdp504-common.dtsi and include it in variant specific DTS file. Describe the fixed USB regulators, PCIe reset GPIOs, QPIC SPI NAND flash and required pinctrl states. Enable QPIC BAM, USB and PCIe for the board. Remove ipq5210-rdp504.dtb from Makefile to avoid build break. Signed-off-by: Varadarajan Narayanan --- arch/arm64/boot/dts/qcom/Makefile | 1 - .../arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi | 209 +++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 79 -------- 3 files changed, 209 insertions(+), 80 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index e05414290d8e..88c898d8ac3b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -25,7 +25,6 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D hamoa-iot-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D hamoa-lenovo-ideacentre-mini-01q8x10.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-tplink-archer-ax55-v1.dtb -dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5210-rdp504.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp468.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm= 64/boot/dts/qcom/ipq5210-rdp504-common.dtsi new file mode 100644 index 000000000000..30c8560822b5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include "ipq5210.dtsi" + +/ { + aliases { + serial0 =3D &uart1; + }; + + chosen { + stdout-path =3D "serial0"; + }; + + vreg_misc_3p3: regulator-usb-3p3 { + compatible =3D "regulator-fixed"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-name =3D "usb_hs_vdda_3p3"; + }; + + vreg_misc_1p8: regulator-usb-1p8 { + compatible =3D "regulator-fixed"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-name =3D "vdda_1p8_usb"; + }; + + vreg_misc_0p925: regulator-usb-0p925 { + compatible =3D "regulator-fixed"; + regulator-min-microvolt =3D <925000>; + regulator-max-microvolt =3D <925000>; + regulator-boot-on; + regulator-always-on; + regulator-name =3D "vdd_core_usb"; + }; +}; + +&pcie0 { + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie0_phy { + status =3D "okay"; +}; + +&pcie0_port0 { + reset-gpios =3D <&tlmm 32 GPIO_ACTIVE_LOW>; +}; + +&pcie1 { + pinctrl-0 =3D <&pcie1_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie1_phy { + status =3D "okay"; +}; + +&pcie1_port0 { + reset-gpios =3D <&tlmm 29 GPIO_ACTIVE_LOW>; +}; + +&qpic_bam { + status =3D "okay"; +}; + +&qpic_nand { + pinctrl-0 =3D <&qpic_snand_default_state>; + pinctrl-names =3D "default"; + + flash@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nand-ecc-engine =3D <&qpic_nand>; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + }; +}; + +&qusb_phy_0 { + vdd-supply =3D <&vreg_misc_0p925>; + vdda-pll-supply =3D <&vreg_misc_1p8>; + vdda-phy-dpdm-supply =3D <&vreg_misc_3p3>; + + status =3D "okay"; +}; + +&sdhc { + max-frequency =3D <192000000>; + bus-width =3D <4>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-0 =3D <&sdhc_default_state>; + pinctrl-names =3D "default"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&ssphy_0 { + vdda-pll-supply =3D <&vreg_misc_1p8>; + vdda-phy-supply =3D <&vreg_misc_0p925>; + + status =3D "okay"; +}; + +&tlmm { + pcie1_default_state: pcie1-default-state { + pins =3D "gpio29"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-down; + }; + + pcie0_default_state: pcie0-default-state { + pins =3D "gpio32"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-down; + }; + + qpic_snand_default_state: qpic-snand-default-state { + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "qspi_data"; + drive-strength =3D <8>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio4"; + function =3D "qspi_cs_n"; + drive-strength =3D <8>; + bias-disable; + }; + + clock-pins { + pins =3D "gpio5"; + function =3D "qspi_clk"; + drive-strength =3D <8>; + bias-disable; + }; + }; + + qup_uart1_default_state: qup-uart1-default-state { + pins =3D "gpio38", "gpio39"; + function =3D "qup_se1"; + drive-strength =3D <6>; + bias-pull-down; + }; + + sdhc_default_state: sdhc-default-state { + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "sdc_data"; + drive-strength =3D <8>; + bias-pull-up; + }; + + cmd-pins { + pins =3D "gpio4"; + function =3D "sdc_cmd"; + drive-strength =3D <8>; + bias-pull-up; + }; + + clk-pins { + pins =3D "gpio5"; + function =3D "sdc_clk"; + drive-strength =3D <8>; + bias-disable; + }; + }; +}; + +&uart1 { + pinctrl-0 =3D <&qup_uart1_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&usb3 { + dr_mode =3D "host"; + + status =3D "okay"; +}; + +&xo_board { + clock-frequency =3D <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts deleted file mode 100644 index 941f866ecfe9..000000000000 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; - -#include "ipq5210.dtsi" - -/ { - model =3D "Qualcomm Technologies, Inc. IPQ5210 RDP504"; - compatible =3D "qcom,ipq5210-rdp504", "qcom,ipq5210"; - - aliases { - serial0 =3D &uart1; - }; - - chosen { - stdout-path =3D "serial0"; - }; -}; - -&sdhc { - max-frequency =3D <192000000>; - bus-width =3D <4>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - pinctrl-0 =3D <&sdhc_default_state>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&sleep_clk { - clock-frequency =3D <32000>; -}; - -&tlmm { - qup_uart1_default_state: qup-uart1-default-state { - pins =3D "gpio38", "gpio39"; - function =3D "qup_se1"; - drive-strength =3D <6>; - bias-pull-down; - }; - - sdhc_default_state: sdhc-default-state { - clk-pins { - pins =3D "gpio5"; - function =3D "sdc_clk"; - drive-strength =3D <8>; - bias-disable; - }; - - cmd-pins { - pins =3D "gpio4"; - function =3D "sdc_cmd"; - drive-strength =3D <8>; - bias-pull-up; - }; - - data-pins { - pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; - function =3D "sdc_data"; - drive-strength =3D <8>; - bias-pull-up; - }; - }; -}; - -&uart1 { - pinctrl-0 =3D <&qup_uart1_default_state>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - -&xo_board { - clock-frequency =3D <24000000>; -}; --=20 2.34.1 From nobody Fri Jul 24 21:53:26 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4767282F1D for ; Fri, 24 Jul 2026 09:55:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784886908; cv=none; b=FHDM02wK5wHcOBwZTLd38Zr82jTVl4Fxx3fSUv/eHi4mm5OqLPaj+6u16wxcfPLUMY2fEsY4WoRwE8y5BcrzV67G/7p3zUcp9UHEG/rd2xwAgGHIiVOcR7S7rEZyZLhalG4/pHoXBUNphVpRC+ShBParbxjzgD0rRoCckQbru34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784886908; c=relaxed/simple; bh=A2YLyH7JcJgoRXIQ3ZAsTHakvd0VJnhjFDGiS2WuYJg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=R6NH6727aEFjY6ebXKcJwyYrJEB49Xex7644E6u/pT3/+vZqScXP+gDtNTlNq3aklSGhuec202sfmh3Y+21OwZn5+8Ca1eb+lB4n0RtIN+HaOcSWLtl7mOQW084drOPdpK6o6RHtAoO61UrbDfSCSOfK5viUkQfXRM+ygjhE50U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=KSs48/XO; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=bTbCII32; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="KSs48/XO"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="bTbCII32" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66O4lLYo2276405 for ; Fri, 24 Jul 2026 09:55:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= RK2KUPhk9iEKyipUm2ztkbbRY+972Yp7NvKxoamx8iY=; b=KSs48/XOup/fnNjR FHwa6CpQf0PA3kxm8me/1qA+dVitU+2bI9OwI1QG9ZA9HHQXwl5tcyCJy7p9lsMw ZGPb2SlLLFI2kniDhSgQT2kIV9fCSKA3Y4lDhR1QSkvUWGja2VLyQ0cTwgj9vNRx 5mdkvoE4H4TNFsVoUktVFbruFGV1XbdSKXNFH3iQSNdJTl7kcLyYVNN4VE/FWGZu ZZdIazQApgRvdv1MVm1oMjMIIw3THfHHghq00fFb3Cx6XfMaj8M9WqNMAEwy2kxV avAjyBVgGTqO6HaTD+B241ynY73hfRPABnv9s0y8s0TAvi/mIbIB/aKsQC9lDoq1 sTuA8g== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fkqa0b680-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 24 Jul 2026 09:55:01 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-cb74d5db64eso313776a12.2 for ; Fri, 24 Jul 2026 02:55:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784886901; x=1785491701; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=RK2KUPhk9iEKyipUm2ztkbbRY+972Yp7NvKxoamx8iY=; b=bTbCII32SBijEQ30EALLO3WTeIU+inkRWTwjZ+3zWHxYMk59PZt2oa1TBUoFpFo7Hy f2sDCbnmeGiUr+w/f/gkZId/Cc0/Dh8OmWoper/6G6jPRLGgT9IJQFDXku+EvJtcIeYp C14K080yqCsCg9UjbrngGYxOD1MdK1k5dgKDC8VY9v/ebNakVb1Lhs3dO/61h6bthqE8 J4PFntkjWHS/9t1pV0nwKdrhmicOcab94xzoBKWCmW36RY0QI+ked2p91R+HbRNUGqN0 nkmpVxR+9Vg0p1t3E5UVLfFWTZQF5syDPMte26YsFJLfSnB1C1kFJ1i2tFqDO5vCwP/E 5eNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784886901; x=1785491701; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=RK2KUPhk9iEKyipUm2ztkbbRY+972Yp7NvKxoamx8iY=; b=MavuLNs/rhbLMMQZvk7ofz7FYguMHwBnvaanqDGqzcA2xDROFtiDCa61uvT+etnhUz gfpS2lLxyMnX6lmlmW+DscLHslvd5Fucy1FnyRm+JWxXWPpHwes5vb98nyvx+o+zsLXe sEalHtCI3H+Ua7UTfE4lqYNL2D9VqTNaxfUiIMLTwuRa5DP9HcfN6yiCUneMfuVajeUy qK3TPAf17E9uJ1LsDXxP34BGsGNb7GEwFXsIdu/noMbSz5aAtHMdWl8NxLZTmaZz0+Dn hllYG+ymiVEwqchRRReQ7TDI6RBGrQ/UmNOk69FJ3cdXAlLpc2qaIU+VQ4yWpZEwi4m1 1ZoQ== X-Forwarded-Encrypted: i=1; AHgh+RqNOKoiMFlma/R64yIrKj3IzvmCN5CjhsQCyN0u6DEztZ+OW9iBLEicfRYPQbQnGM+suJikELosoM2IOLQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yz6ZiUuJl42EVHKJrtIbsavlEyPbVNHuo/rNp4SPgBQK1u9EHoY 1iCpLu0c0KpNn+reY6kOzky1t9CdczY/UgnCnHAu4aRx14OGeu4tqNpD4NKA5olB6evaB5N/GQ1 P7swOGQUvPAxMg+thKr6a6vWLG+mtrJPpmPyU1TvqK9MuRJoI3xLacgPYRFXIoYeS9JM= X-Gm-Gg: AR+sD11rN1sQz+Qk3Q37EUvOjuyQIO4NBAr9+0aDlzmNyZjTEaqbPbsg+NCv+zX8s5C hz+D9d66bxE/gHf2N3bfNsBp1nMN6gLZ6SZWgW6WnNtqgX5AgFgJehMqBoVtWVBjQA79EXL2PH2 D5R5R7zszBEO9jKasGnw9jMCg6Xf0eh1GniAjweWeSAxK+92yFHuI94RTT6kwsOtH+ps4Kuv1QN 0dMJzgENaN+/w5oqVi/Jb3vX+1AueAQ/Zfq2JzaaCb6sRUylM2jYfBHrt4S48LY5LDHrI61kJ/w WHlJEo4K8Y/B4dZsTNwEFGGqLTlVCs3gutEkZghKhSbN7ozNePk6+HdnOq5YQJzlMrMge/gpQYB rkR/61hYPCwBMTgG4I2gzlf27Sv+37aFWQgL6gwhpTjo7lI3abqcMuMoJcb5Xq4Qx5Dmaul2WFO OruaLdU1JnLDKPSrx050EZvfPMVhpgkw== X-Received: by 2002:a05:6a21:a89:b0:3c0:b766:74f4 with SMTP id adf61e73a8af0-3c44b04cc2dmr8005818637.31.1784886901234; Fri, 24 Jul 2026 02:55:01 -0700 (PDT) X-Received: by 2002:a05:6a21:a89:b0:3c0:b766:74f4 with SMTP id adf61e73a8af0-3c44b04cc2dmr8005793637.31.1784886900824; Fri, 24 Jul 2026 02:55:00 -0700 (PDT) Received: from hu-varada-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3147e1b6a45sm28975093eec.28.2026.07.24.02.54.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Jul 2026 02:55:00 -0700 (PDT) From: Varadarajan Narayanan Date: Fri, 24 Jul 2026 15:24:46 +0530 Subject: [PATCH v4 3/3] arm64: dts: qcom: ipq5210: Introduce RDP504 variant specific DT file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260724-08-dts-v4-3-65e61a1061f0@oss.qualcomm.com> References: <20260724-08-dts-v4-0-65e61a1061f0@oss.qualcomm.com> In-Reply-To: <20260724-08-dts-v4-0-65e61a1061f0@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: iLOBKH07IvqoiQRyZoSfDbfKc6gp2rK8 X-Proofpoint-GUID: iLOBKH07IvqoiQRyZoSfDbfKc6gp2rK8 X-Authority-Analysis: v=2.4 cv=e/k2j6p/ c=1 sm=1 tr=0 ts=6a633675 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=OPStAwdTocQlwmF8_qcA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI0MDA5MCBTYWx0ZWRfXwnpD/fAkj9y+ fIyHjmxoeLKeXP4/Rz+vPKYZJtMMi/lh+oLLFFywSS0l6wujLPwmNG3mmeAbE/SyiT12obxF56T Uf0JV3HFVibXyzL7s/UF/z9qHXopvKWHZvhuyNs8QgeVG2e45h3UVVEfDc6xcqE+Z/6Yb9uFWhL 5yHO04X1gjqvXJ+AvC/gL+Do+Kq1gYProxqI3sZe0N88+w+ptaK09cZb2xzoXPnPHtg4B4JHcjm /JjMT2Vdp9RoZmuRiizW9CQXBzWUHbVx59tsyn61Xwbc+avSV+lWEgTUaz6XVurmYZvYtYgcI5I 1YMoVEvtI4xrTbvTA6XUxDCyo2KvG3+LTSUGsotkMcT/2mnKJCV0F/qOML/qoaR327gAamMvMT/ USbaye7zLjKdEtAkVtBd0/mU7I7fW9SW4u/x22z7wsmj6qwcJOiaaNh26RT78maaotQw3WcPpxv 2yNZ1kfMpuannjfp2eg== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI0MDA5MCBTYWx0ZWRfX/h5mzM4kFGNt eRURXCv3xrn5RsLZOUVs5xCFUp/zVMLIrEt4L1VCZT9MH7XqDSy4grZPAGJUG2CVxceYgi113Cz soJYO7PMpV+jyXt3P1k0dZPqm4mKVDI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-24_01,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607240090 Add two DT files, one for the default eMMC variant and one for the NAND variant. Add ipq5210-rdp504.dtb and ipq5210-rdp504-nand.dtb to Makefile Signed-off-by: Varadarajan Narayanan --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 17 +++++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 88c898d8ac3b..6d1773761496 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D hamoa-iot-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D hamoa-lenovo-ideacentre-mini-01q8x10.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5018-tplink-archer-ax55-v1.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5210-rdp504.dtb ipq5210-rdp504-nand.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq5332-rdp468.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts b/arch/arm64/= boot/dts/qcom/ipq5210-rdp504-nand.dts new file mode 100644 index 000000000000..1145fcf0a302 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-nand.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq5210-rdp504-common.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. IPQ5210 RDP504 (NAND)"; + compatible =3D "qcom,ipq5210-rdp504", "qcom,ipq5210"; +}; + +&qpic_nand { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts new file mode 100644 index 000000000000..e5f2f9217f3b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq5210-rdp504-common.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. IPQ5210 RDP504 (eMMC)"; + compatible =3D "qcom,ipq5210-rdp504", "qcom,ipq5210"; +}; + +&sdhc { + status =3D "okay"; +}; --=20 2.34.1