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Thu, 23 Jul 2026 10:12:13 -0700 (PDT) Received: from kernel ([45.251.35.26]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13d130f42bbsm19016480c88.14.2026.07.23.10.12.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 10:12:12 -0700 (PDT) From: Mohamad Raizudeen To: bhelgaas@google.com Cc: alex@shazbot.org, skhan@linuxfoundation.org, jkoolstra@xs4all.nl, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Mohamad Raizudeen Subject: [PATCH v2] PCI: Fix 32-bit config write in Intel RP MPC ACS quirk Date: Thu, 23 Jul 2026 22:42:03 +0530 Message-ID: <20260723171203.4892-1-raizudeen.kerneldev@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The pci_quirk_enable_intel_rp_mpc_acs() reads a 32 bit DWORD from the MPC register, sets bit 26 (INTEL_MPC_REG_IRBNCE), but it writes it back using pci_write_config_word(). Because bit 26 resides in the upper 16 bits of the 32 bit register, a 16 bit write to offset 0xd8 completely drops the newly set bit. The quirk logs that it is enabling IRBNCE, but the hardware never actually receives the command. Fix this by using pci_write_config_dword() to ensure the full 32 bit value is written back to the hardware. Fixes: d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root por= ts") Signed-off-by: Mohamad Raizudeen --- Changes in v2: - Added "Fixes:" tag and CC'd Alex Williamson as requested by Bjorn Helgaas. Link to v1: https://lore.kernel.org/linux-pci/20260723160641.GC836122@bhelg= aas/T/#t drivers/pci/quirks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index b09f27f7846f..0d0cf6f86173 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5361,7 +5361,7 @@ static void pci_quirk_enable_intel_rp_mpc_acs(struct = pci_dev *dev) if (!(mpc & INTEL_MPC_REG_IRBNCE)) { pci_info(dev, "Enabling MPC IRBNCE\n"); mpc |=3D INTEL_MPC_REG_IRBNCE; - pci_write_config_word(dev, INTEL_MPC_REG, mpc); + pci_write_config_dword(dev, INTEL_MPC_REG, mpc); } } =20 --=20 2.53.0