From nobody Fri Jul 24 05:21:41 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 23E1544E65D; Thu, 23 Jul 2026 15:55:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822107; cv=none; b=Bu1LuU55moJCwhNYDUNUsPkLhl44AyO/SIxzsUCdgDMyzC7yEF7phqorHNzILAkpmo8OmG7fma7RSHij2S7i7K94eyZSAPnxfZdNh3NMdj37MR+t6jOOGJ+atLOUtD50mqAW3/d8j1skBo+8E9jp4ogHhnDxuu0W4LBKuomIhWE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822107; c=relaxed/simple; bh=Y6WEnBs2cgXZZd8Q1Tuvn8J1rTb9pkh2ckXfdKexDis=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ELBZgATehiejptJLvJjSIS/AgfehbkL/G5w0pXrnxRffPyS2XY4rNVK/CJ/NgHZrdluMMoTwdTekyakMJF0ydTvpn4toX3A8Ujeoz7qa3mmSikuWLPr20JKEK1IehK/sqOwPkkNuropSmJqy9y2D3m3RWrsXm77dV9PtXeRfhHk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=WJSZO5Cr; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="WJSZO5Cr" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F37231595; Thu, 23 Jul 2026 08:54:59 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 97E483F66F; Thu, 23 Jul 2026 08:55:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784822104; bh=Y6WEnBs2cgXZZd8Q1Tuvn8J1rTb9pkh2ckXfdKexDis=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WJSZO5CrrqwKbP0H3BEPg9hs7S+3DKTMjNwHfSHhnblIC3Ja5KRywffWmYXkmnXdn 5iIoXcD0nIivUywHueJlQZXNRz7SD41gBJIBv5z0fkSacP/KmX2SIwimbiC8F9vcuj GLqpMUeXU2oDTWB8b9rNXkf9cmH2N6X8BomDDNIc= From: Andre Przywara To: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 01/10] arm_mpam: let low level MSC accessors return an error Date: Thu, 23 Jul 2026 17:54:45 +0200 Message-ID: <20260723155454.1760823-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723155454.1760823-1-andre.przywara@arm.com> References: <20260723155454.1760823-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The upcoming MPAM-Fb support does not use MMIO primitives to access an MSC, but employs a shared-memory/doorbell based firmware protocol. Its complexity means that is must be able to handle errors, whereas we always assume an MMIO based MSC access succeeds today. Change the __mpam_read_reg() low level accessor function to return the requested data through a pointer, and return an error code instead. Also change the __mpam_write_reg() accessor function to return an error code. At the moment this is always 0, but this will change with alternative MSC access methods. Change all direct users of those MSC wrappers to comply with the new prototypes, though the errors are not propagated all the way up yet. Signed-off-by: Andre Przywara --- drivers/resctrl/mpam_devices.c | 204 +++++++++++++++++++++------------ 1 file changed, 130 insertions(+), 74 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index b69f99488111..912c21ce7f9f 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -177,59 +177,68 @@ static void mpam_assert_partid_sizes_fixed(void) WARN_ON_ONCE(!partid_max_published); } =20 -static u32 __mpam_read_reg(struct mpam_msc *msc, u16 reg) +static int __mpam_read_reg(struct mpam_msc *msc, u16 reg, u32 *res) { WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); =20 - return readl_relaxed(msc->mapped_hwpage + reg); + *res =3D readl_relaxed(msc->mapped_hwpage + reg); + + return 0; } =20 -static inline u32 _mpam_read_partsel_reg(struct mpam_msc *msc, u16 reg) +static inline int _mpam_read_partsel_reg(struct mpam_msc *msc, u16 reg, + u32 *res) { lockdep_assert_held_once(&msc->part_sel_lock); - return __mpam_read_reg(msc, reg); + return __mpam_read_reg(msc, reg, res); } =20 -#define mpam_read_partsel_reg(msc, reg) _mpam_read_partsel_reg(msc, MPAMF_= ##reg) +#define mpam_read_partsel_reg(msc, reg, res) _mpam_read_partsel_reg(msc, M= PAMF_##reg, res) =20 -static void __mpam_write_reg(struct mpam_msc *msc, u16 reg, u32 val) +static int __mpam_write_reg(struct mpam_msc *msc, u16 reg, u32 val) { WARN_ON_ONCE(reg + sizeof(u32) > msc->mapped_hwpage_sz); WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); =20 writel_relaxed(val, msc->mapped_hwpage + reg); + + return 0; } =20 -static inline void _mpam_write_partsel_reg(struct mpam_msc *msc, u16 reg, = u32 val) +static inline int _mpam_write_partsel_reg(struct mpam_msc *msc, u16 reg, u= 32 val) { lockdep_assert_held_once(&msc->part_sel_lock); - __mpam_write_reg(msc, reg, val); + return __mpam_write_reg(msc, reg, val); } =20 #define mpam_write_partsel_reg(msc, reg, val) _mpam_write_partsel_reg(msc= , MPAMCFG_##reg, val) =20 -static inline u32 _mpam_read_monsel_reg(struct mpam_msc *msc, u16 reg) +static inline int _mpam_read_monsel_reg(struct mpam_msc *msc, u16 reg, + u32 *res) { mpam_mon_sel_lock_held(msc); - return __mpam_read_reg(msc, reg); + return __mpam_read_reg(msc, reg, res); } =20 -#define mpam_read_monsel_reg(msc, reg) _mpam_read_monsel_reg(msc, MSMON_##= reg) +#define mpam_read_monsel_reg(msc, reg, res) _mpam_read_monsel_reg(msc, MSM= ON_##reg, res) =20 -static inline void _mpam_write_monsel_reg(struct mpam_msc *msc, u16 reg, u= 32 val) +static inline int _mpam_write_monsel_reg(struct mpam_msc *msc, u16 reg, u3= 2 val) { mpam_mon_sel_lock_held(msc); - __mpam_write_reg(msc, reg, val); + return __mpam_write_reg(msc, reg, val); } =20 #define mpam_write_monsel_reg(msc, reg, val) _mpam_write_monsel_reg(msc,= MSMON_##reg, val) =20 static bool mpam_msc_check_aidr(struct mpam_msc *msc) { - u32 aidr =3D __mpam_read_reg(msc, MPAMF_AIDR); - u32 major =3D FIELD_GET(MPAMF_AIDR_ARCH_MAJOR_REV, aidr); - u32 minor =3D FIELD_GET(MPAMF_AIDR_ARCH_MINOR_REV, aidr); + u32 aidr, major, minor; =20 + if (__mpam_read_reg(msc, MPAMF_AIDR, &aidr)) + return false; + + major =3D FIELD_GET(MPAMF_AIDR_ARCH_MAJOR_REV, aidr); + minor =3D FIELD_GET(MPAMF_AIDR_ARCH_MINOR_REV, aidr); /* * v0.0 and >v2.x aren't supported, but anything else should be backward * compatible to v0.1 or v1.0. @@ -242,25 +251,39 @@ static bool mpam_msc_check_aidr(struct mpam_msc *msc) return true; } =20 -static u64 mpam_msc_read_idr(struct mpam_msc *msc) +static int mpam_msc_read_idr(struct mpam_msc *msc, u64 *res) { - u64 idr_high =3D 0, idr_low; + u32 idr_high =3D 0, idr_low; + int ret; =20 lockdep_assert_held(&msc->part_sel_lock); =20 - idr_low =3D mpam_read_partsel_reg(msc, IDR); - if (FIELD_GET(MPAMF_IDR_EXT, idr_low)) - idr_high =3D mpam_read_partsel_reg(msc, IDR + 4); + ret =3D mpam_read_partsel_reg(msc, IDR, &idr_low); + if (ret) + return ret; + + if (FIELD_GET(MPAMF_IDR_EXT, idr_low)) { + ret =3D mpam_read_partsel_reg(msc, IDR + 4, &idr_high); + if (ret) + return ret; + } =20 - return (idr_high << 32) | idr_low; + *res =3D ((u64)idr_high << 32) | idr_low; + + return 0; } =20 -static void mpam_msc_clear_esr(struct mpam_msc *msc) +static int mpam_msc_clear_esr(struct mpam_msc *msc) { - u64 esr_low =3D __mpam_read_reg(msc, MPAMF_ESR); + u32 esr_low; + int ret; + + ret =3D __mpam_read_reg(msc, MPAMF_ESR, &esr_low); + if (ret) + return ret; =20 if (!esr_low) - return; + return 0; =20 /* * Clearing the high/low bits of MPAMF_ESR can not be atomic. @@ -268,44 +291,57 @@ static void mpam_msc_clear_esr(struct mpam_msc *msc) * lower half prevent hardware from updating either half of the * register. */ - if (msc->has_extd_esr) - __mpam_write_reg(msc, MPAMF_ESR + 4, 0); - __mpam_write_reg(msc, MPAMF_ESR, 0); + if (msc->has_extd_esr) { + ret =3D __mpam_write_reg(msc, MPAMF_ESR + 4, 0); + if (ret) + return ret; + } + + return __mpam_write_reg(msc, MPAMF_ESR, 0); } =20 -static u64 mpam_msc_read_esr(struct mpam_msc *msc) +static int mpam_msc_read_esr(struct mpam_msc *msc, u64 *res) { - u64 esr_high =3D 0, esr_low; + u32 esr_high =3D 0, esr_low; + int ret; =20 - esr_low =3D __mpam_read_reg(msc, MPAMF_ESR); - if (msc->has_extd_esr) - esr_high =3D __mpam_read_reg(msc, MPAMF_ESR + 4); + ret =3D __mpam_read_reg(msc, MPAMF_ESR, &esr_low); + if (ret) + return ret; =20 - return (esr_high << 32) | esr_low; + if (msc->has_extd_esr) { + ret =3D __mpam_read_reg(msc, MPAMF_ESR + 4, &esr_high); + if (ret) + return ret; + } + + *res =3D ((u64)esr_high << 32) | esr_low; + + return 0; } =20 -static void __mpam_part_sel_raw(u32 partsel, struct mpam_msc *msc) +static int __mpam_part_sel_raw(u32 partsel, struct mpam_msc *msc) { lockdep_assert_held(&msc->part_sel_lock); =20 - mpam_write_partsel_reg(msc, PART_SEL, partsel); + return mpam_write_partsel_reg(msc, PART_SEL, partsel); } =20 -static void __mpam_part_sel(u8 ris_idx, u16 partid, struct mpam_msc *msc) +static int __mpam_part_sel(u8 ris_idx, u16 partid, struct mpam_msc *msc) { u32 partsel =3D FIELD_PREP(MPAMCFG_PART_SEL_RIS, ris_idx) | FIELD_PREP(MPAMCFG_PART_SEL_PARTID_SEL, partid); =20 - __mpam_part_sel_raw(partsel, msc); + return __mpam_part_sel_raw(partsel, msc); } =20 -static void __mpam_intpart_sel(u8 ris_idx, u16 intpartid, struct mpam_msc = *msc) +static int __mpam_intpart_sel(u8 ris_idx, u16 intpartid, struct mpam_msc *= msc) { u32 partsel =3D FIELD_PREP(MPAMCFG_PART_SEL_RIS, ris_idx) | FIELD_PREP(MPAMCFG_PART_SEL_PARTID_SEL, intpartid) | MPAMCFG_PART_SEL_INTERNAL; =20 - __mpam_part_sel_raw(partsel, msc); + return __mpam_part_sel_raw(partsel, msc); } =20 int mpam_register_requestor(u16 partid_max, u8 pmg_max) @@ -774,13 +810,13 @@ static bool mpam_ris_hw_probe_csu_nrdy(struct mpam_ms= c_ris *ris) mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val); =20 _mpam_write_monsel_reg(msc, MSMON_CSU, MSMON___NRDY); - now =3D _mpam_read_monsel_reg(msc, MSMON_CSU); + _mpam_read_monsel_reg(msc, MSMON_CSU, &now); can_set =3D now & MSMON___NRDY; =20 _mpam_write_monsel_reg(msc, MSMON_CSU, 0); /* Configuration change to try and coax hardware into setting nrdy */ mpam_write_monsel_reg(msc, CFG_CSU_FLT, 0x1); - now =3D _mpam_read_monsel_reg(msc, MSMON_CSU); + _mpam_read_monsel_reg(msc, MSMON_CSU, &now); can_clear =3D !(now & MSMON___NRDY); mpam_mon_sel_unlock(msc); =20 @@ -800,7 +836,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) =20 /* Cache Capacity Partitioning */ if (FIELD_GET(MPAMF_IDR_HAS_CCAP_PART, ris->idr)) { - u32 ccap_features =3D mpam_read_partsel_reg(msc, CCAP_IDR); + u32 ccap_features; + + mpam_read_partsel_reg(msc, CCAP_IDR, &ccap_features); =20 props->cmax_wd =3D FIELD_GET(MPAMF_CCAP_IDR_CMAX_WD, ccap_features); if (props->cmax_wd && @@ -823,7 +861,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) =20 /* Cache Portion partitioning */ if (FIELD_GET(MPAMF_IDR_HAS_CPOR_PART, ris->idr)) { - u32 cpor_features =3D mpam_read_partsel_reg(msc, CPOR_IDR); + u32 cpor_features; + + mpam_read_partsel_reg(msc, CPOR_IDR, &cpor_features); =20 props->cpbm_wd =3D FIELD_GET(MPAMF_CPOR_IDR_CPBM_WD, cpor_features); if (props->cpbm_wd) @@ -832,7 +872,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) =20 /* Memory bandwidth partitioning */ if (FIELD_GET(MPAMF_IDR_HAS_MBW_PART, ris->idr)) { - u32 mbw_features =3D mpam_read_partsel_reg(msc, MBW_IDR); + u32 mbw_features; + + mpam_read_partsel_reg(msc, MBW_IDR, &mbw_features); =20 /* portion bitmap resolution */ props->mbw_pbm_bits =3D FIELD_GET(MPAMF_MBW_IDR_BWPBM_WD, mbw_features); @@ -860,7 +902,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) =20 /* Priority partitioning */ if (FIELD_GET(MPAMF_IDR_HAS_PRI_PART, ris->idr)) { - u32 pri_features =3D mpam_read_partsel_reg(msc, PRI_IDR); + u32 pri_features; + + mpam_read_partsel_reg(msc, PRI_IDR, &pri_features); =20 props->intpri_wd =3D FIELD_GET(MPAMF_PRI_IDR_INTPRI_WD, pri_features); if (props->intpri_wd && FIELD_GET(MPAMF_PRI_IDR_HAS_INTPRI, pri_features= )) { @@ -879,7 +923,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) =20 /* Performance Monitoring */ if (FIELD_GET(MPAMF_IDR_HAS_MSMON, ris->idr)) { - u32 msmon_features =3D mpam_read_partsel_reg(msc, MSMON_IDR); + u32 msmon_features; + + mpam_read_partsel_reg(msc, MSMON_IDR, &msmon_features); =20 /* * If the firmware max-nrdy-us property is missing, the @@ -892,7 +938,8 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) if (FIELD_GET(MPAMF_MSMON_IDR_MSMON_CSU, msmon_features)) { u32 csumonidr; =20 - csumonidr =3D mpam_read_partsel_reg(msc, CSUMON_IDR); + mpam_read_partsel_reg(msc, CSUMON_IDR, &csumonidr); + props->num_csu_mon =3D FIELD_GET(MPAMF_CSUMON_IDR_NUM_MON, csumonidr); if (props->num_csu_mon) { bool hw_managed; @@ -915,7 +962,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) } if (FIELD_GET(MPAMF_MSMON_IDR_MSMON_MBWU, msmon_features)) { bool has_long; - u32 mbwumon_idr =3D mpam_read_partsel_reg(msc, MBWUMON_IDR); + u32 mbwumon_idr; + + mpam_read_partsel_reg(msc, MBWUMON_IDR, &mbwumon_idr); =20 props->num_mbwu_mon =3D FIELD_GET(MPAMF_MBWUMON_IDR_NUM_MON, mbwumon_id= r); if (props->num_mbwu_mon) { @@ -945,8 +994,11 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) */ if (FIELD_GET(MPAMF_IDR_HAS_PARTID_NRW, ris->idr) && class->type !=3D MPAM_CLASS_UNKNOWN) { - u32 nrwidr =3D mpam_read_partsel_reg(msc, PARTID_NRW_IDR); - u16 partid_max =3D FIELD_GET(MPAMF_PARTID_NRW_IDR_INTPARTID_MAX, nrwidr); + u16 partid_max; + u32 nrwidr; + + mpam_read_partsel_reg(msc, PARTID_NRW_IDR, &nrwidr); + partid_max =3D FIELD_GET(MPAMF_PARTID_NRW_IDR_INTPARTID_MAX, nrwidr); =20 mpam_set_feature(mpam_feat_partid_nrw, props); msc->partid_max =3D min(msc->partid_max, partid_max); @@ -970,8 +1022,9 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) =20 /* Grab an IDR value to find out how many RIS there are */ mutex_lock(&msc->part_sel_lock); - idr =3D mpam_msc_read_idr(msc); - msc->iidr =3D mpam_read_partsel_reg(msc, IIDR); + mpam_msc_read_idr(msc, &idr); + mpam_read_partsel_reg(msc, IIDR, &msc->iidr); + mutex_unlock(&msc->part_sel_lock); =20 mpam_enable_quirks(msc); @@ -985,7 +1038,7 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) for (ris_idx =3D 0; ris_idx <=3D msc->ris_max; ris_idx++) { mutex_lock(&msc->part_sel_lock); __mpam_part_sel(ris_idx, 0, msc); - idr =3D mpam_msc_read_idr(msc); + mpam_msc_read_idr(msc, &idr); mutex_unlock(&msc->part_sel_lock); =20 partid_max =3D FIELD_GET(MPAMF_IDR_PARTID_MAX, idr); @@ -1039,24 +1092,24 @@ static u64 mpam_msc_read_mbwu_l(struct mpam_msc *ms= c) { int retry =3D 3; u32 mbwu_l_low; - u64 mbwu_l_high1, mbwu_l_high2; + u32 mbwu_l_high1, mbwu_l_high2; =20 mpam_mon_sel_lock_held(msc); =20 WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz); WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); =20 - mbwu_l_high2 =3D __mpam_read_reg(msc, MSMON_MBWU_L + 4); + __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2); do { mbwu_l_high1 =3D mbwu_l_high2; - mbwu_l_low =3D __mpam_read_reg(msc, MSMON_MBWU_L); - mbwu_l_high2 =3D __mpam_read_reg(msc, MSMON_MBWU_L + 4); + __mpam_read_reg(msc, MSMON_MBWU_L, &mbwu_l_low); + __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2); =20 retry--; } while (mbwu_l_high1 !=3D mbwu_l_high2 && retry > 0); =20 if (mbwu_l_high1 =3D=3D mbwu_l_high2) - return (mbwu_l_high1 << 32) | mbwu_l_low; + return ((u64)mbwu_l_high1 << 32) | mbwu_l_low; =20 pr_warn("Failed to read a stable value\n"); return MSMON___L_NRDY; @@ -1120,14 +1173,14 @@ static void read_msmon_ctl_flt_vals(struct mon_read= *m, u32 *ctl_val, =20 switch (m->type) { case mpam_feat_msmon_csu: - *ctl_val =3D mpam_read_monsel_reg(msc, CFG_CSU_CTL); - *flt_val =3D mpam_read_monsel_reg(msc, CFG_CSU_FLT); + mpam_read_monsel_reg(msc, CFG_CSU_CTL, ctl_val); + mpam_read_monsel_reg(msc, CFG_CSU_FLT, flt_val); break; case mpam_feat_msmon_mbwu_31counter: case mpam_feat_msmon_mbwu_44counter: case mpam_feat_msmon_mbwu_63counter: - *ctl_val =3D mpam_read_monsel_reg(msc, CFG_MBWU_CTL); - *flt_val =3D mpam_read_monsel_reg(msc, CFG_MBWU_FLT); + mpam_read_monsel_reg(msc, CFG_MBWU_CTL, ctl_val); + mpam_read_monsel_reg(msc, CFG_MBWU_FLT, flt_val); break; default: pr_warn("Unexpected monitor type %d\n", m->type); @@ -1206,6 +1259,7 @@ static u64 mpam_msmon_overflow_val(enum mpam_device_f= eatures type, static void __ris_msmon_read(void *arg) { u64 now; + u32 now32; bool nrdy =3D false; bool config_mismatch; bool overflow =3D false; @@ -1268,9 +1322,9 @@ static void __ris_msmon_read(void *arg) =20 switch (m->type) { case mpam_feat_msmon_csu: - now =3D mpam_read_monsel_reg(msc, CSU); - nrdy =3D now & MSMON___NRDY; - now =3D FIELD_GET(MSMON___VALUE, now); + mpam_read_monsel_reg(msc, CSU, &now32); + nrdy =3D now32 & MSMON___NRDY; + now =3D FIELD_GET(MSMON___VALUE, now32); =20 if (mpam_has_quirk(IGNORE_CSU_NRDY, msc) && m->waited_timeout) nrdy =3D false; @@ -1288,9 +1342,9 @@ static void __ris_msmon_read(void *arg) else now =3D FIELD_GET(MSMON___L_VALUE, now); } else { - now =3D mpam_read_monsel_reg(msc, MBWU); - nrdy =3D now & MSMON___NRDY; - now =3D FIELD_GET(MSMON___VALUE, now); + mpam_read_monsel_reg(msc, MBWU, &now32); + nrdy =3D now32 & MSMON___NRDY; + now =3D FIELD_GET(MSMON___VALUE, now32); } =20 if (mpam_has_quirk(T241_MBW_COUNTER_SCALE_64, msc) && @@ -1685,16 +1739,18 @@ static int mpam_save_mbwu_state(void *arg) mon_sel =3D FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, i) | FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx); mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); - - cur_flt =3D mpam_read_monsel_reg(msc, CFG_MBWU_FLT); - cur_ctl =3D mpam_read_monsel_reg(msc, CFG_MBWU_CTL); + mpam_read_monsel_reg(msc, CFG_MBWU_FLT, &cur_flt); + mpam_read_monsel_reg(msc, CFG_MBWU_CTL, &cur_ctl); mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0); =20 if (mpam_ris_has_mbwu_long_counter(ris)) { val =3D mpam_msc_read_mbwu_l(msc); mpam_msc_zero_mbwu_l(msc); } else { - val =3D mpam_read_monsel_reg(msc, MBWU); + u32 val32; + + mpam_read_monsel_reg(msc, MBWU, &val32); + val =3D val32; mpam_write_monsel_reg(msc, MBWU, 0); } =20 @@ -2465,7 +2521,7 @@ static irqreturn_t __mpam_irq_handler(int irq, struct= mpam_msc *msc) &msc->accessibility))) return IRQ_NONE; =20 - reg =3D mpam_msc_read_esr(msc); + mpam_msc_read_esr(msc, ®); =20 errcode =3D FIELD_GET(MPAMF_ESR_ERRCODE, reg); if (!errcode) --=20 2.43.0 From nobody Fri Jul 24 05:21:41 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6193647D93F; Thu, 23 Jul 2026 15:55:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822112; cv=none; b=lA3B4NIqB0Wh5X6FQlZike5JoiLWrM7F9mFgVJ3jYBxwtWUd1rWxIBlmR07BhyL7DIvk/SQm1CmnCQ+oFVa8p/+Oporu/UrPagQRZ3n/t4Zu00KqNPZGMn/NxFhlM/CxSCsgkU3/p/b4tI4kqC64nN/m3NEhhDCx08acm3hcdVU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822112; c=relaxed/simple; bh=s63AvJmH/yDk+84LzQBoFp+Px3O8XOz1/Jdu0R3WFpw=; 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Thu, 23 Jul 2026 08:55:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784822107; bh=s63AvJmH/yDk+84LzQBoFp+Px3O8XOz1/Jdu0R3WFpw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oMgftY9wNxOOZAd+wlaOWj5JV6E5aUNpBnzPtDfM25o1wHUnAbrURdlc9neNasWWT 1ooxui0Y2I6PvZXku/3HIB1NxpRD1zc379AkydCnkG0YXVpeiNP/EXPwPpgYMViFeo cjBP+Xu8fM4JX+zLBdGxHxIWjYZEOGlTSyDzMIZw= From: Andre Przywara To: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 02/10] arm_mpam: propagate MSC access errors for hw_probe functions Date: Thu, 23 Jul 2026 17:54:46 +0200 Message-ID: <20260723155454.1760823-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723155454.1760823-1-andre.przywara@arm.com> References: <20260723155454.1760823-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow the functions probing for MSC hardware and features to return an error, and propagate read and write errors from the lower level up. This uses some "scoped cleanup" functions like scoped_guard() and ACQUIRE() to avoid the complexity of error handling when a lock has been taken. Since the mon_sel_lock is a bit special (even more so in an upcoming patch), we define a new GUARD type for it. Signed-off-by: Andre Przywara --- drivers/resctrl/mpam_devices.c | 127 +++++++++++++++++++++----------- drivers/resctrl/mpam_internal.h | 8 ++ 2 files changed, 91 insertions(+), 44 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 912c21ce7f9f..ecd45a585942 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -794,38 +794,46 @@ static bool mpam_ris_hw_probe_csu_nrdy(struct mpam_ms= c_ris *ris) bool can_set, can_clear; struct mpam_msc *msc =3D ris->vmsc->msc; =20 - if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) + ACQUIRE(mon_sel_lock, guard)(msc); + if (ACQUIRE_ERR(mon_sel_lock, &guard)) return false; =20 mon_sel =3D FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, 0) | FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx); - mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); + if (mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel)) + return false; =20 /* Hardware might ignore nrdy if it's not enabled */ ctl_val =3D MSMON_CFG_CSU_CTL_TYPE_CSU; ctl_val |=3D MSMON_CFG_x_CTL_MATCH_PARTID; ctl_val |=3D MSMON_CFG_x_CTL_MATCH_PMG; ctl_val |=3D MSMON_CFG_x_CTL_EN; - mpam_write_monsel_reg(msc, CFG_CSU_FLT, 0); - mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val); + if (mpam_write_monsel_reg(msc, CFG_CSU_FLT, 0)) + return false; + if (mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val)) + return false; =20 - _mpam_write_monsel_reg(msc, MSMON_CSU, MSMON___NRDY); - _mpam_read_monsel_reg(msc, MSMON_CSU, &now); + if (_mpam_write_monsel_reg(msc, MSMON_CSU, MSMON___NRDY)) + return false; + if (_mpam_read_monsel_reg(msc, MSMON_CSU, &now)) + return false; can_set =3D now & MSMON___NRDY; =20 - _mpam_write_monsel_reg(msc, MSMON_CSU, 0); + if (_mpam_write_monsel_reg(msc, MSMON_CSU, 0)) + return false; /* Configuration change to try and coax hardware into setting nrdy */ - mpam_write_monsel_reg(msc, CFG_CSU_FLT, 0x1); - _mpam_read_monsel_reg(msc, MSMON_CSU, &now); + if (mpam_write_monsel_reg(msc, CFG_CSU_FLT, 0x1)) + return false; + if (_mpam_read_monsel_reg(msc, MSMON_CSU, &now)) + return false; can_clear =3D !(now & MSMON___NRDY); - mpam_mon_sel_unlock(msc); =20 return (!can_set || !can_clear); } =20 -static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) +static int mpam_ris_hw_probe(struct mpam_msc_ris *ris) { - int err; + int fw_has_nrdy_err, err; struct mpam_msc *msc =3D ris->vmsc->msc; struct device *dev =3D &msc->pdev->dev; struct mpam_props *props =3D &ris->props; @@ -838,7 +846,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) if (FIELD_GET(MPAMF_IDR_HAS_CCAP_PART, ris->idr)) { u32 ccap_features; =20 - mpam_read_partsel_reg(msc, CCAP_IDR, &ccap_features); + err =3D mpam_read_partsel_reg(msc, CCAP_IDR, &ccap_features); + if (err) + return err; =20 props->cmax_wd =3D FIELD_GET(MPAMF_CCAP_IDR_CMAX_WD, ccap_features); if (props->cmax_wd && @@ -863,7 +873,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) if (FIELD_GET(MPAMF_IDR_HAS_CPOR_PART, ris->idr)) { u32 cpor_features; =20 - mpam_read_partsel_reg(msc, CPOR_IDR, &cpor_features); + err =3D mpam_read_partsel_reg(msc, CPOR_IDR, &cpor_features); + if (err) + return err; =20 props->cpbm_wd =3D FIELD_GET(MPAMF_CPOR_IDR_CPBM_WD, cpor_features); if (props->cpbm_wd) @@ -873,8 +885,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) /* Memory bandwidth partitioning */ if (FIELD_GET(MPAMF_IDR_HAS_MBW_PART, ris->idr)) { u32 mbw_features; - - mpam_read_partsel_reg(msc, MBW_IDR, &mbw_features); + err =3D mpam_read_partsel_reg(msc, MBW_IDR, &mbw_features); + if (err) + return err; =20 /* portion bitmap resolution */ props->mbw_pbm_bits =3D FIELD_GET(MPAMF_MBW_IDR_BWPBM_WD, mbw_features); @@ -903,8 +916,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) /* Priority partitioning */ if (FIELD_GET(MPAMF_IDR_HAS_PRI_PART, ris->idr)) { u32 pri_features; - - mpam_read_partsel_reg(msc, PRI_IDR, &pri_features); + err =3D mpam_read_partsel_reg(msc, PRI_IDR, &pri_features); + if (err) + return err; =20 props->intpri_wd =3D FIELD_GET(MPAMF_PRI_IDR_INTPRI_WD, pri_features); if (props->intpri_wd && FIELD_GET(MPAMF_PRI_IDR_HAS_INTPRI, pri_features= )) { @@ -925,20 +939,24 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ri= s) if (FIELD_GET(MPAMF_IDR_HAS_MSMON, ris->idr)) { u32 msmon_features; =20 - mpam_read_partsel_reg(msc, MSMON_IDR, &msmon_features); + err =3D mpam_read_partsel_reg(msc, MSMON_IDR, &msmon_features); + if (err) + return err; =20 /* * If the firmware max-nrdy-us property is missing, the * CSU counters can't be used. Should we wait forever? */ - err =3D device_property_read_u32(&msc->pdev->dev, - "arm,not-ready-us", - &msc->nrdy_usec); + fw_has_nrdy_err =3D device_property_read_u32(&msc->pdev->dev, + "arm,not-ready-us", + &msc->nrdy_usec); =20 if (FIELD_GET(MPAMF_MSMON_IDR_MSMON_CSU, msmon_features)) { u32 csumonidr; =20 - mpam_read_partsel_reg(msc, CSUMON_IDR, &csumonidr); + err =3D mpam_read_partsel_reg(msc, CSUMON_IDR, &csumonidr); + if (err) + return err; =20 props->num_csu_mon =3D FIELD_GET(MPAMF_CSUMON_IDR_NUM_MON, csumonidr); if (props->num_csu_mon) { @@ -956,7 +974,7 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) * Accept the missing firmware property if NRDY appears * un-implemented. */ - if (err && hw_managed) + if (fw_has_nrdy_err && hw_managed) dev_err_once(dev, "Counters are not usable because not-ready timeout = was not provided by firmware."); } } @@ -964,7 +982,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) bool has_long; u32 mbwumon_idr; =20 - mpam_read_partsel_reg(msc, MBWUMON_IDR, &mbwumon_idr); + err =3D mpam_read_partsel_reg(msc, MBWUMON_IDR, &mbwumon_idr); + if (err) + return err; =20 props->num_mbwu_mon =3D FIELD_GET(MPAMF_MBWUMON_IDR_NUM_MON, mbwumon_id= r); if (props->num_mbwu_mon) { @@ -997,16 +1017,22 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *r= is) u16 partid_max; u32 nrwidr; =20 - mpam_read_partsel_reg(msc, PARTID_NRW_IDR, &nrwidr); + err =3D mpam_read_partsel_reg(msc, PARTID_NRW_IDR, &nrwidr); + if (err) + return err; + partid_max =3D FIELD_GET(MPAMF_PARTID_NRW_IDR_INTPARTID_MAX, nrwidr); =20 mpam_set_feature(mpam_feat_partid_nrw, props); msc->partid_max =3D min(msc->partid_max, partid_max); } + + return 0; } =20 static int mpam_msc_hw_probe(struct mpam_msc *msc) { + int ret; u64 idr; u16 partid_max; u8 ris_idx, pmg_max; @@ -1021,11 +1047,14 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) } =20 /* Grab an IDR value to find out how many RIS there are */ - mutex_lock(&msc->part_sel_lock); - mpam_msc_read_idr(msc, &idr); - mpam_read_partsel_reg(msc, IIDR, &msc->iidr); - - mutex_unlock(&msc->part_sel_lock); + scoped_guard(mutex, &msc->part_sel_lock) { + ret =3D mpam_msc_read_idr(msc, &idr); + if (ret) + return ret; + ret =3D mpam_read_partsel_reg(msc, IIDR, &msc->iidr); + if (ret) + return ret; + } =20 mpam_enable_quirks(msc); =20 @@ -1036,10 +1065,15 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) msc->pmg_max =3D FIELD_GET(MPAMF_IDR_PMG_MAX, idr); =20 for (ris_idx =3D 0; ris_idx <=3D msc->ris_max; ris_idx++) { - mutex_lock(&msc->part_sel_lock); - __mpam_part_sel(ris_idx, 0, msc); - mpam_msc_read_idr(msc, &idr); - mutex_unlock(&msc->part_sel_lock); + scoped_guard(mutex, &msc->part_sel_lock) { + ret =3D __mpam_part_sel(ris_idx, 0, msc); + if (ret) + return ret; + + ret =3D mpam_msc_read_idr(msc, &idr); + if (ret) + return ret; + } =20 partid_max =3D FIELD_GET(MPAMF_IDR_PARTID_MAX, idr); pmg_max =3D FIELD_GET(MPAMF_IDR_PMG_MAX, idr); @@ -1047,17 +1081,22 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) msc->pmg_max =3D min(msc->pmg_max, pmg_max); msc->has_extd_esr =3D FIELD_GET(MPAMF_IDR_HAS_EXTD_ESR, idr); =20 - mutex_lock(&mpam_list_lock); - ris =3D mpam_get_or_create_ris(msc, ris_idx); - mutex_unlock(&mpam_list_lock); - if (IS_ERR(ris)) - return PTR_ERR(ris); + scoped_guard(mutex, &mpam_list_lock) { + ris =3D mpam_get_or_create_ris(msc, ris_idx); + if (IS_ERR(ris)) + return PTR_ERR(ris); + } ris->idr =3D idr; =20 - mutex_lock(&msc->part_sel_lock); - __mpam_part_sel(ris_idx, 0, msc); - mpam_ris_hw_probe(ris); - mutex_unlock(&msc->part_sel_lock); + scoped_guard(mutex, &msc->part_sel_lock) { + ret =3D __mpam_part_sel(ris_idx, 0, msc); + if (ret) + return ret; + + ret =3D mpam_ris_hw_probe(ris); + if (ret) + return ret; + } } =20 /* Clear any stale errors */ diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 04d1a59f02af..0c3f6a040b20 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -162,6 +162,14 @@ static inline void mpam_mon_sel_lock_init(struct mpam_= msc *msc) raw_spin_lock_init(&msc->_mon_sel_lock); } =20 +DEFINE_GUARD(mon_sel, + struct mpam_msc *, + mpam_mon_sel_lock(_T), + mpam_mon_sel_unlock(_T)); +DEFINE_GUARD_COND(mon_sel, _lock, + mpam_mon_sel_lock(_T), + _RET); + /* Bits for mpam features bitmaps */ enum mpam_device_features { mpam_feat_cpor_part, --=20 2.43.0 From nobody Fri Jul 24 05:21:41 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id ABB2344E679; Thu, 23 Jul 2026 15:55:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822115; cv=none; b=Lp/WhNzYZcoHsEAhQPMnUd3KuoURbgfzgjG84gU6+KqofPVjYlQPx3k6o44Kke9Ut3EcATE5XSZKFOvyaj/5VEPUQg5Li68AVH63jTVBzie7kr9B0IPI8Q7/lyUlY0FhOlc8gD/DeSmnWOGHf45DyIRcIlN2pq/JhRxXpkF7uVE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822115; c=relaxed/simple; bh=gRBsK2XXpdqJk9qjuat4AR6gYBmA1l94CmOgVQCns2M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Thu, 23 Jul 2026 08:55:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784822111; bh=gRBsK2XXpdqJk9qjuat4AR6gYBmA1l94CmOgVQCns2M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AU90jM55LVKYweB0a4JY116y7y/hpadHywkYyTXWvTxL7EhqKY42AezSJszkbX995 BxNMXITwtulwzyuyAdJ6TzouvJG71xz0LdBDY29C7W7HA9mSxmiocB3sLPZVHAeYub zvW68GuV/FOHi7BgdC0h5KiI5Zl8mDHVXVdEqvck= From: Andre Przywara To: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 03/10] arm_mpam: propagate MSC access errors for MBWU counters Date: Thu, 23 Jul 2026 17:54:47 +0200 Message-ID: <20260723155454.1760823-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723155454.1760823-1-andre.przywara@arm.com> References: <20260723155454.1760823-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow the mpam_msc_read_mbwu_l() function to return an error, and propagate errors from the lower level up. This also changes the users of this function. Signed-off-by: Andre Przywara --- drivers/resctrl/mpam_devices.c | 45 +++++++++++++++++++++++----------- 1 file changed, 31 insertions(+), 14 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index ecd45a585942..fce29fa9ef78 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1127,8 +1127,9 @@ static bool mpam_ris_has_mbwu_long_counter(struct mpa= m_msc_ris *ris) mpam_has_feature(mpam_feat_msmon_mbwu_44counter, &ris->props)); } =20 -static u64 mpam_msc_read_mbwu_l(struct mpam_msc *msc) +static int mpam_msc_read_mbwu_l(struct mpam_msc *msc, u64 *res) { + int ret; int retry =3D 3; u32 mbwu_l_low; u32 mbwu_l_high1, mbwu_l_high2; @@ -1138,20 +1139,30 @@ static u64 mpam_msc_read_mbwu_l(struct mpam_msc *ms= c) WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz); WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); =20 - __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2); + ret =3D __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2); + if (ret) + return ret; + do { mbwu_l_high1 =3D mbwu_l_high2; - __mpam_read_reg(msc, MSMON_MBWU_L, &mbwu_l_low); - __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2); + ret =3D __mpam_read_reg(msc, MSMON_MBWU_L, &mbwu_l_low); + if (ret) + return ret; + ret =3D __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2); + if (ret) + return ret; =20 retry--; } while (mbwu_l_high1 !=3D mbwu_l_high2 && retry > 0); =20 - if (mbwu_l_high1 =3D=3D mbwu_l_high2) - return ((u64)mbwu_l_high1 << 32) | mbwu_l_low; + if (mbwu_l_high1 =3D=3D mbwu_l_high2) { + *res =3D ((u64)mbwu_l_high1 << 32) | mbwu_l_low; + } else { + pr_warn("Failed to read a stable value\n"); + *res =3D MSMON___L_NRDY; + } =20 - pr_warn("Failed to read a stable value\n"); - return MSMON___L_NRDY; + return 0; } =20 static void mpam_msc_zero_mbwu_l(struct mpam_msc *msc) @@ -1310,10 +1321,12 @@ static void __ris_msmon_read(void *arg) struct mpam_msc *msc =3D m->ris->vmsc->msc; u32 mon_sel, ctl_val, flt_val, cur_ctl, cur_flt; =20 - if (!mpam_mon_sel_lock(msc)) { + ACQUIRE(mon_sel_lock, guard)(msc); + if (ACQUIRE_ERR(mon_sel_lock, &guard)) { m->err =3D -EIO; return; } + mon_sel =3D FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, ctx->mon) | FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx); mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); @@ -1373,7 +1386,9 @@ static void __ris_msmon_read(void *arg) case mpam_feat_msmon_mbwu_44counter: case mpam_feat_msmon_mbwu_63counter: if (m->type !=3D mpam_feat_msmon_mbwu_31counter) { - now =3D mpam_msc_read_mbwu_l(msc); + m->err =3D mpam_msc_read_mbwu_l(msc, &now); + if (m->err) + return; nrdy =3D now & MSMON___L_NRDY; =20 if (m->type =3D=3D mpam_feat_msmon_mbwu_63counter) @@ -1407,7 +1422,6 @@ static void __ris_msmon_read(void *arg) default: m->err =3D -EINVAL; } - mpam_mon_sel_unlock(msc); =20 if (nrdy) m->err =3D -EBUSY; @@ -1762,6 +1776,7 @@ static int mpam_save_mbwu_state(void *arg) { int i; u64 val; + int ret; struct mon_cfg *cfg; u32 cur_flt, cur_ctl, mon_sel; struct mpam_msc_ris *ris =3D arg; @@ -1772,7 +1787,8 @@ static int mpam_save_mbwu_state(void *arg) mbwu_state =3D &ris->mbwu_state[i]; cfg =3D &mbwu_state->cfg; =20 - if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) + ACQUIRE(mon_sel_lock, guard)(msc); + if (ACQUIRE_ERR(mon_sel_lock, &guard)) return -EIO; =20 mon_sel =3D FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, i) | @@ -1783,7 +1799,9 @@ static int mpam_save_mbwu_state(void *arg) mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0); =20 if (mpam_ris_has_mbwu_long_counter(ris)) { - val =3D mpam_msc_read_mbwu_l(msc); + ret =3D mpam_msc_read_mbwu_l(msc, &val); + if (ret) + return ret; mpam_msc_zero_mbwu_l(msc); } else { u32 val32; @@ -1799,7 +1817,6 @@ static int mpam_save_mbwu_state(void *arg) cfg->partid =3D FIELD_GET(MSMON_CFG_x_FLT_PARTID, cur_flt); mbwu_state->correction +=3D val; mbwu_state->enabled =3D FIELD_GET(MSMON_CFG_x_CTL_EN, cur_ctl); - mpam_mon_sel_unlock(msc); } =20 return 0; --=20 2.43.0 From nobody Fri Jul 24 05:21:41 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 07C8047CA84; Thu, 23 Jul 2026 15:55:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="l+WWQbjM" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3EE211595; Thu, 23 Jul 2026 08:55:11 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F0E083F66F; Thu, 23 Jul 2026 08:55:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784822115; bh=ouZ5S5YFYUS/PHknbH6+A2f7Dw6YkpC1gKY7l/k2aeU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l+WWQbjMVLtrIz4XBt509x1swhraB4t+WBl9Dwn7jowA7x4zBGu/r1XSkHZzH7+AC mlZgIFjzpisGCIMNKnOEK4rCz2LIf10iHZvIPXDllCdID4ZpbEH7gIny4b6qiLXZAC iqljenLsYEoCY1YbHuIXEnOB6BDDYfvZNVCKmcn8= From: Andre Przywara To: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 04/10] arm_mpam: propagate MSC access errors for msmon helpers Date: Thu, 23 Jul 2026 17:54:48 +0200 Message-ID: <20260723155454.1760823-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723155454.1760823-1-andre.przywara@arm.com> References: <20260723155454.1760823-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow the helper functions for msmon accesses to return an error, and propagate read and write errors from the lower level up. Signed-off-by: Andre Przywara --- drivers/resctrl/mpam_devices.c | 72 ++++++++++++++++++++++------------ 1 file changed, 47 insertions(+), 25 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index fce29fa9ef78..9ee4eb4db03f 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1165,15 +1165,20 @@ static int mpam_msc_read_mbwu_l(struct mpam_msc *ms= c, u64 *res) return 0; } =20 -static void mpam_msc_zero_mbwu_l(struct mpam_msc *msc) +static int mpam_msc_zero_mbwu_l(struct mpam_msc *msc) { + int ret; + mpam_mon_sel_lock_held(msc); =20 WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz); WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); =20 - __mpam_write_reg(msc, MSMON_MBWU_L, 0); - __mpam_write_reg(msc, MSMON_MBWU_L + 4, 0); + ret =3D __mpam_write_reg(msc, MSMON_MBWU_L, 0); + if (ret) + return ret; + + return __mpam_write_reg(msc, MSMON_MBWU_L + 4, 0); } =20 static void gen_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val, @@ -1216,24 +1221,28 @@ static void gen_msmon_ctl_flt_vals(struct mon_read = *m, u32 *ctl_val, } } =20 -static void read_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val, - u32 *flt_val) +static int read_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val, + u32 *flt_val) { struct mpam_msc *msc =3D m->ris->vmsc->msc; + int ret; =20 switch (m->type) { case mpam_feat_msmon_csu: - mpam_read_monsel_reg(msc, CFG_CSU_CTL, ctl_val); - mpam_read_monsel_reg(msc, CFG_CSU_FLT, flt_val); - break; + ret =3D mpam_read_monsel_reg(msc, CFG_CSU_CTL, ctl_val); + if (ret) + return ret; + return mpam_read_monsel_reg(msc, CFG_CSU_FLT, flt_val); case mpam_feat_msmon_mbwu_31counter: case mpam_feat_msmon_mbwu_44counter: case mpam_feat_msmon_mbwu_63counter: - mpam_read_monsel_reg(msc, CFG_MBWU_CTL, ctl_val); - mpam_read_monsel_reg(msc, CFG_MBWU_FLT, flt_val); - break; + ret =3D mpam_read_monsel_reg(msc, CFG_MBWU_CTL, ctl_val); + if (ret) + return ret; + return mpam_read_monsel_reg(msc, CFG_MBWU_FLT, flt_val); default: pr_warn("Unexpected monitor type %d\n", m->type); + return -EINVAL; } } =20 @@ -1246,10 +1255,11 @@ static inline void clean_msmon_ctl_val(u32 *cur_ctl) *cur_ctl &=3D ~MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L; } =20 -static void write_msmon_ctl_flt_vals(struct mon_read *m, u32 ctl_val, - u32 flt_val) +static int write_msmon_ctl_flt_vals(struct mon_read *m, u32 ctl_val, + u32 flt_val) { struct mpam_msc *msc =3D m->ris->vmsc->msc; + int ret; =20 /* * Write the ctl_val with the enable bit cleared, reset the counter, @@ -1257,25 +1267,37 @@ static void write_msmon_ctl_flt_vals(struct mon_rea= d *m, u32 ctl_val, */ switch (m->type) { case mpam_feat_msmon_csu: - mpam_write_monsel_reg(msc, CFG_CSU_FLT, flt_val); - mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val); - mpam_write_monsel_reg(msc, CSU, 0); - mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val | MSMON_CFG_x_CTL_EN); - break; + ret =3D mpam_write_monsel_reg(msc, CFG_CSU_FLT, flt_val); + if (ret) + return ret; + ret =3D mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val); + if (ret) + return ret; + ret =3D mpam_write_monsel_reg(msc, CSU, 0); + if (ret) + return ret; + return mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val | MSMON_CFG_x_CTL= _EN); case mpam_feat_msmon_mbwu_31counter: case mpam_feat_msmon_mbwu_44counter: case mpam_feat_msmon_mbwu_63counter: - mpam_write_monsel_reg(msc, CFG_MBWU_FLT, flt_val); - mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val); - mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val | MSMON_CFG_x_CTL_EN); + ret =3D mpam_write_monsel_reg(msc, CFG_MBWU_FLT, flt_val); + if (ret) + return ret; + ret =3D mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val); + if (ret) + return ret; + ret =3D mpam_write_monsel_reg(msc, CFG_MBWU_CTL, + ctl_val | MSMON_CFG_x_CTL_EN); + if (ret) + return ret; /* Counting monitors require NRDY to be reset by software */ if (m->type =3D=3D mpam_feat_msmon_mbwu_31counter) - mpam_write_monsel_reg(msc, MBWU, 0); - else - mpam_msc_zero_mbwu_l(m->ris->vmsc->msc); - break; + return mpam_write_monsel_reg(msc, MBWU, 0); + + return mpam_msc_zero_mbwu_l(m->ris->vmsc->msc); default: pr_warn("Unexpected monitor type %d\n", m->type); + return -EINVAL; } } =20 --=20 2.43.0 From nobody Fri Jul 24 05:21:41 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5626E44E679; Thu, 23 Jul 2026 15:55:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; 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spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="M0FVYxNT" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F227B1477; Thu, 23 Jul 2026 08:55:14 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BA3D83F66F; Thu, 23 Jul 2026 08:55:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784822119; bh=hroGaWGQMzWX3bDSX9pHLPOMEtJTFweY6FhbdiQJngY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M0FVYxNTQ6zvPNP2iS6lgpDwJQlpwqk6HLQNncB7ajmKpo8yfCZTogqNIpVdU4N8q nbTuHBvEZNlBKqPo3eEAUw4EkOra0ttWb0Ln3zKkJHMoh3FGmPDkNcMnfuoujXT1E1 25+sr69jnPvgM9cJW0nglaxKgOj8GsGmTXWLUKgk= From: Andre Przywara To: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 05/10] arm_mpam: propagate MSC access errors for __ris_msmon_read() Date: Thu, 23 Jul 2026 17:54:49 +0200 Message-ID: <20260723155454.1760823-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723155454.1760823-1-andre.przywara@arm.com> References: <20260723155454.1760823-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow the function for RIS accesses to return an error, and propagate read and write errors from the lower level up. This function is a bit special, since it can be called via an SMP helper, so the prototype must stay as void. So propagate any errors using the "err" field in the struct passed in as the sole argument to that function. Signed-off-by: Andre Przywara --- drivers/resctrl/mpam_devices.c | 36 +++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 9ee4eb4db03f..bcff53477133 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1328,6 +1328,10 @@ static u64 mpam_msmon_overflow_val(enum mpam_device_= features type, return overflow_val; } =20 +/* + * This function might be called via smp_call_function_any(), so propagate + * errors inside the arg struct. + */ static void __ris_msmon_read(void *arg) { u64 now; @@ -1351,7 +1355,9 @@ static void __ris_msmon_read(void *arg) =20 mon_sel =3D FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, ctx->mon) | FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx); - mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); + m->err =3D mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); + if (m->err) + return; =20 switch (m->type) { case mpam_feat_msmon_mbwu_31counter: @@ -1371,7 +1377,9 @@ static void __ris_msmon_read(void *arg) * Read the existing configuration to avoid re-writing the same values. * This saves waiting for 'nrdy' on subsequent reads. */ - read_msmon_ctl_flt_vals(m, &cur_ctl, &cur_flt); + m->err =3D read_msmon_ctl_flt_vals(m, &cur_ctl, &cur_flt); + if (m->err) + return; =20 if (mpam_feat_msmon_mbwu_31counter =3D=3D m->type) overflow =3D cur_ctl & MSMON_CFG_x_CTL_OFLOW_STATUS; @@ -1385,18 +1393,24 @@ static void __ris_msmon_read(void *arg) cur_ctl !=3D (ctl_val | MSMON_CFG_x_CTL_EN); =20 if (config_mismatch || reset_on_next_read) { - write_msmon_ctl_flt_vals(m, ctl_val, flt_val); + m->err =3D write_msmon_ctl_flt_vals(m, ctl_val, flt_val); + if (m->err) + return; overflow =3D false; } else if (overflow) { - mpam_write_monsel_reg(msc, CFG_MBWU_CTL, - cur_ctl & - ~(MSMON_CFG_x_CTL_OFLOW_STATUS | - MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L)); + m->err =3D mpam_write_monsel_reg(msc, CFG_MBWU_CTL, + cur_ctl & + ~(MSMON_CFG_x_CTL_OFLOW_STATUS | + MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L)); + if (m->err) + return; } =20 switch (m->type) { case mpam_feat_msmon_csu: - mpam_read_monsel_reg(msc, CSU, &now32); + m->err =3D mpam_read_monsel_reg(msc, CSU, &now32); + if (m->err) + return; nrdy =3D now32 & MSMON___NRDY; now =3D FIELD_GET(MSMON___VALUE, now32); =20 @@ -1418,7 +1432,9 @@ static void __ris_msmon_read(void *arg) else now =3D FIELD_GET(MSMON___L_VALUE, now); } else { - mpam_read_monsel_reg(msc, MBWU, &now32); + m->err =3D mpam_read_monsel_reg(msc, MBWU, &now32); + if (m->err) + return; nrdy =3D now32 & MSMON___NRDY; now =3D FIELD_GET(MSMON___VALUE, now32); } @@ -1787,6 +1803,8 @@ static int mpam_restore_mbwu_state(void *_ris) mwbu_arg.val =3D &val; =20 __ris_msmon_read(&mwbu_arg); + if (mwbu_arg.err) + return mwbu_arg.err; } } =20 --=20 2.43.0 From nobody Fri Jul 24 05:21:41 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 971234C77CA; Thu, 23 Jul 2026 15:55:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822125; cv=none; b=upFY1TBmPIWjmgXgIHET+b/gpQQ/sQ4XFHVIgCkOe/LHmiZJBa99ifUrjki1LX2bVJb8S+A04sDr2hH3QlSQDOGoIRI/ZSgvgk8mDKQhXTixLq8AaqPunnwMtfV4aZtfj79lojjJODz9eaxjBNUqNCPo7Rmby2R240ngVwMauyY= ARC-Message-Signature: i=1; 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Thu, 23 Jul 2026 08:55:18 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 78E4C3F66F; Thu, 23 Jul 2026 08:55:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784822122; bh=zuii4y3ZJEsm4812TF2ly2vpc/bQP8awGaQF3cHeW2A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B1p47kdnYLlMlEOvDF7EeUClQq+qwW1K8JHUITjYfSp2J5KEGVUdJyCaYpmJi2RnO uv6VYIUFQv/venwh0oXEZnUDhsItAt9WNczRsVwS11WhxcGHojakSThvpPMbf9vdCM RsV40R2bPaHKQZE2VavexMvvKxyPAFYH0hsswoQk= From: Andre Przywara To: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 06/10] arm_mpam: propagate MSC access errors for state saving function Date: Thu, 23 Jul 2026 17:54:50 +0200 Message-ID: <20260723155454.1760823-7-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723155454.1760823-1-andre.przywara@arm.com> References: <20260723155454.1760823-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow the mpam_save_mbwu_state() function to return an error, and propagate read and write errors from the lower level up. Signed-off-by: Andre Przywara --- drivers/resctrl/mpam_devices.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index bcff53477133..6329443c451f 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1833,22 +1833,37 @@ static int mpam_save_mbwu_state(void *arg) =20 mon_sel =3D FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, i) | FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx); - mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); - mpam_read_monsel_reg(msc, CFG_MBWU_FLT, &cur_flt); - mpam_read_monsel_reg(msc, CFG_MBWU_CTL, &cur_ctl); - mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0); + ret =3D mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); + if (ret) + return ret; + ret =3D mpam_read_monsel_reg(msc, CFG_MBWU_FLT, &cur_flt); + if (ret) + return ret; + ret =3D mpam_read_monsel_reg(msc, CFG_MBWU_CTL, &cur_ctl); + if (ret) + return ret; + ret =3D mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0); + if (ret) + return ret; =20 if (mpam_ris_has_mbwu_long_counter(ris)) { ret =3D mpam_msc_read_mbwu_l(msc, &val); if (ret) return ret; - mpam_msc_zero_mbwu_l(msc); + ret =3D mpam_msc_zero_mbwu_l(msc); + if (ret) + return ret; } else { u32 val32; =20 - mpam_read_monsel_reg(msc, MBWU, &val32); + ret =3D mpam_read_monsel_reg(msc, MBWU, &val32); + if (ret) + return ret; + val =3D val32; - mpam_write_monsel_reg(msc, MBWU, 0); + ret =3D mpam_write_monsel_reg(msc, MBWU, 0); + if (ret) + return ret; } =20 cfg->mon =3D i; --=20 2.43.0 From nobody Fri Jul 24 05:21:41 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 434A14D8D85; Thu, 23 Jul 2026 15:55:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822129; cv=none; b=FGvsQNaYn70YJYHvu+WAJfTflVM1jXg/+fbiZhIrVAxcvlFjOyzIeRJMqQ/+cJ7vbriJu+whrcYV+i339Oxc6KjlMOsH6u/mRZ2VlZPqu8+b6qQsgWiDe2trd+DqpfgBpZOkyfYx6B8ZIZhn/U4NvxDNTckSTE2HQT9MkVw9Nis= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822129; c=relaxed/simple; bh=lAx1ozqhso3gfmQsmzAoH/C16G8oKBBQpLc7oozcmIc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZhFbf3nIuk4S1FBh/V4WArEKnpCwoX5l3rtw/67k/bPsoYMOs6kuOlnNjHDKIfhTsKEqK1DsMIAIAhvlyat+FwTzLEWeTjVno3azJFInYq+tu1EKlNoKXo8sVMjJ2Dg5uE9gH0ycTaFF4Ze1f9Nh50gPn7rw3sFSO4aMBpVqCMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=nE9nfic6; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="nE9nfic6" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8E4601595; Thu, 23 Jul 2026 08:55:22 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 48A943F66F; Thu, 23 Jul 2026 08:55:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784822126; bh=lAx1ozqhso3gfmQsmzAoH/C16G8oKBBQpLc7oozcmIc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nE9nfic60xWZAsy6n0WnFLAUSunvfVwFYry+SSTRIUoedqF3ccOg+djaTb6hCx0EC VAJSyv8Vn+RZzYg1uF2M89AmCY70lTMbzTXw5Guds0lZefLINJ8HyrgYM4e9MMw2Q0 1eVr+c9t7S4+Cb3HZc2LXry0jugPGUoW4igaeFRU= From: Andre Przywara To: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 07/10] arm_mpam: prepare mon_sel locking for MPAM-Fb Date: Thu, 23 Jul 2026 17:54:51 +0200 Message-ID: <20260723155454.1760823-8-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723155454.1760823-1-andre.przywara@arm.com> References: <20260723155454.1760823-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MSC MON_SEL register needs to be accessed from hardirq for the overflow interrupt, and when taking an IPI to access these registers on platforms where MSCs are not accesible from every CPU. This makes an irqsave spinlock the obvious lock to protect these registers. On systems with MPAM-Fb mailbox MSC access it must be able to sleep, meaning a mutex must be used. So MPAM-Fb platforms cannot support an overflow interrupt easily. Clearly these two methods can't exist for one MSC at the same time. Change the mon_sel locking wrapper function to only use a spinlock when the MSC is accessed directly via MMIO. In case of MPAM-Fb, we use a mutex, but only if we are in a sleepable context. If that's not the case, we return an error. This should not happen, as MPAM-Fb by design does not require an MSC access to happen from a specific CPU, so there is no need for any IPIs or preemption disabling to satisfy CPU constraints. And since overflow interrupts are not supported at the moment anyway, we also wouldn't meet the other case. Bailing out early is already happening in rare occasions today. Signed-off-by: Andre Przywara --- drivers/resctrl/mpam_devices.c | 5 ++++- drivers/resctrl/mpam_internal.h | 32 ++++++++++++++++++++++++++------ 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 6329443c451f..e2cb884eacf4 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -2225,7 +2225,10 @@ static struct mpam_msc *do_mpam_msc_drv_probe(struct= platform_device *pdev) if (err) return ERR_PTR(err); =20 - mpam_mon_sel_lock_init(msc); + err =3D mpam_mon_sel_lock_init(dev, msc); + if (err) + return ERR_PTR(err); + msc->id =3D pdev->id; msc->pdev =3D pdev; INIT_LIST_HEAD_RCU(&msc->all_msc_list); diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 0c3f6a040b20..b3a6ed9ed175 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -126,6 +126,7 @@ struct mpam_msc { */ raw_spinlock_t _mon_sel_lock; unsigned long _mon_sel_flags; + struct mutex mon_sel_mutex; =20 void __iomem *mapped_hwpage; size_t mapped_hwpage_sz; @@ -139,27 +140,46 @@ struct mpam_msc { /* Returning false here means accesses to mon_sel must fail and report an = error. */ static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) { - /* Locking will require updating to support a firmware backed interface */ - if (WARN_ON_ONCE(msc->iface !=3D MPAM_IFACE_MMIO)) + if (msc->iface =3D=3D MPAM_IFACE_MMIO) { + raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); + + return true; + } + + if (!preemptible()) return false; =20 - raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); + mutex_lock(&msc->mon_sel_mutex); + return true; } =20 static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) { - raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); + if (msc->iface =3D=3D MPAM_IFACE_MMIO) { + raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, + msc->_mon_sel_flags); + + return; + } + + mutex_unlock(&msc->mon_sel_mutex); } =20 static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) { - lockdep_assert_held_once(&msc->_mon_sel_lock); + if (msc->iface =3D=3D MPAM_IFACE_MMIO) + lockdep_assert_held_once(&msc->_mon_sel_lock); + else + lockdep_assert_held_once(&msc->mon_sel_mutex); } =20 -static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) +static inline int mpam_mon_sel_lock_init(struct device *dev, + struct mpam_msc *msc) { raw_spin_lock_init(&msc->_mon_sel_lock); + + return devm_mutex_init(dev, &msc->mon_sel_mutex); } =20 DEFINE_GUARD(mon_sel, --=20 2.43.0 From nobody Fri Jul 24 05:21:41 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 02CB64D90BB; Thu, 23 Jul 2026 15:55:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822133; cv=none; b=XIU5k6QD0X1DLvg67Si8vKRq1NuEQfa92i8CjbC8EAGGn0SAAsJeAw6x0EY9ADItSjsOjF8ynuFqlEoqFRWNTbrxeOH3fciAsJZ6v6zQbqtmFkf8I0P17o2/wc/UjRa91RTgTEPQHTvCNnzD91rLdk9BdnCcYClzFTFAx4K52gc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822133; c=relaxed/simple; bh=Cl7AHxRPWn8epyM1zP1G23+G0RzWuiGZgw43nZneJW8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FPYMuIqGmVpaGc49JJf85TZ3YUeLpCTs2Ou51igFC+Mu3r64rC0hnYfq69YVaoDdcnlktYK6hXKMd5FmBRPfaWGeUmBsX1RNx83tHV/+ylCP0IzmGWXKUijyZ9xTwRch6Lk3bcBVElIKFQtA1VTUT59k07Gzu5gBgx4bC+iWprc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=CA3+Sd93; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="CA3+Sd93" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3ED23176A; Thu, 23 Jul 2026 08:55:26 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 05CD43FA7A; Thu, 23 Jul 2026 08:55:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784822130; bh=Cl7AHxRPWn8epyM1zP1G23+G0RzWuiGZgw43nZneJW8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CA3+Sd934EaA9D5zGWkqthCNKBMn4yDW0jv4aCJSpj10KVCBVnZNQCaPq9evbYRD0 KN/ih7HjtWrqKTcAlS5EsMn0xoOUGKy2REEgwNSn37kai6Kroowt/Nyw/hhM6PrQtY PQlG+jfgWoSagnDtVfHosg/GADsEybscgxi9NUok= From: Andre Przywara To: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 08/10] arm_mpam: add MPAM-Fb MSC firmware access support Date: Thu, 23 Jul 2026 17:54:52 +0200 Message-ID: <20260723155454.1760823-9-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723155454.1760823-1-andre.przywara@arm.com> References: <20260723155454.1760823-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Arm MPAM Firmware-backed (Fb) Profile document[1] describes an alternative way of accessing the "Memory System Components" (MSC) in an MPAM enabled system. Normally the MSCs are MMIO mapped, but in some implementations this might not be possible (MSC located outside of the local socket, MSC mapped secure-only) or desirable (direct MMIO access too slow or needs to be mediated through a control processor). MPAM-fb standardises a protocol to abstract MSC accesses, building on the SCMI protocol. Add functions that do an MSC read or write access by redirecting the request through a firmware interface. For now this done via an ACPI PCC shared memory and mailbox combination. Since the protocol used is only a small subset of the full SCMI spec, and the SCMI protocol has no full ACPI support anyway, open-code the (simple) SCMI message generation, for just the fields we need. [1] https://developer.arm.com/documentation/den0144/latest Signed-off-by: Andre Przywara --- drivers/resctrl/Makefile | 2 +- drivers/resctrl/mpam_devices.c | 27 ++++- drivers/resctrl/mpam_fb.c | 197 ++++++++++++++++++++++++++++++++ drivers/resctrl/mpam_internal.h | 20 ++++ include/linux/arm_mpam.h | 2 +- 5 files changed, 240 insertions(+), 8 deletions(-) create mode 100644 drivers/resctrl/mpam_fb.c diff --git a/drivers/resctrl/Makefile b/drivers/resctrl/Makefile index 4f6d0e81f9b8..097c036724e9 100644 --- a/drivers/resctrl/Makefile +++ b/drivers/resctrl/Makefile @@ -1,5 +1,5 @@ obj-$(CONFIG_ARM64_MPAM_DRIVER) +=3D mpam.o -mpam-y +=3D mpam_devices.o +mpam-y +=3D mpam_devices.o mpam_fb.o mpam-$(CONFIG_ARM64_MPAM_RESCTRL_FS) +=3D mpam_resctrl.o =20 ccflags-$(CONFIG_ARM64_MPAM_DRIVER_DEBUG) +=3D -DDEBUG diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index e2cb884eacf4..b8108ed4b32c 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -181,6 +181,9 @@ static int __mpam_read_reg(struct mpam_msc *msc, u16 re= g, u32 *res) { WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); =20 + if (msc->iface =3D=3D MPAM_IFACE_PCC) + return mpam_fb_send_read_request(msc, reg, res); + *res =3D readl_relaxed(msc->mapped_hwpage + reg); =20 return 0; @@ -197,9 +200,12 @@ static inline int _mpam_read_partsel_reg(struct mpam_m= sc *msc, u16 reg, =20 static int __mpam_write_reg(struct mpam_msc *msc, u16 reg, u32 val) { - WARN_ON_ONCE(reg + sizeof(u32) > msc->mapped_hwpage_sz); WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); =20 + if (msc->iface =3D=3D MPAM_IFACE_PCC) + return mpam_fb_send_write_request(msc, reg, val); + + WARN_ON_ONCE(reg + sizeof(u32) > msc->mapped_hwpage_sz); writel_relaxed(val, msc->mapped_hwpage + reg); =20 return 0; @@ -1136,7 +1142,8 @@ static int mpam_msc_read_mbwu_l(struct mpam_msc *msc,= u64 *res) =20 mpam_mon_sel_lock_held(msc); =20 - WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz); + if (msc->iface =3D=3D MPAM_IFACE_MMIO) + WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz); WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); =20 ret =3D __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2); @@ -1485,11 +1492,16 @@ static int _msmon_read(struct mpam_component *comp,= struct mon_read *arg) srcu_read_lock_held(&mpam_srcu)) { arg->ris =3D ris; =20 - err =3D smp_call_function_any(&msc->accessibility, - __ris_msmon_read, arg, - true); - if (!err && arg->err) + if (msc->iface =3D=3D MPAM_IFACE_MMIO) { + err =3D smp_call_function_any(&msc->accessibility, + __ris_msmon_read, + arg, true); + if (!err) + err =3D arg->err; + } else { + __ris_msmon_read(arg); err =3D arg->err; + } =20 /* * Save one error to be returned to the caller, but @@ -1916,6 +1928,9 @@ static int mpam_get_msc_preferred_cpu(struct mpam_msc= *msc) =20 static int mpam_touch_msc(struct mpam_msc *msc, int (*fn)(void *a), void *= arg) { + if (msc->iface !=3D MPAM_IFACE_MMIO) + return fn(arg); + lockdep_assert_irqs_enabled(); lockdep_assert_cpus_held(); WARN_ON_ONCE(!srcu_read_lock_held((&mpam_srcu))); diff --git a/drivers/resctrl/mpam_fb.c b/drivers/resctrl/mpam_fb.c new file mode 100644 index 000000000000..ec4bf0dd9182 --- /dev/null +++ b/drivers/resctrl/mpam_fb.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2024 Arm Ltd. + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "mpam_internal.h" + +#define MPAM_FB_PROTOCOL_ID 0x1a +#define MPAM_PROTOCOL_VERSION 0x0 +#define MPAM_MSC_ATTRIBUTES_CMD 0x3 +#define MPAM_MSC_READ_CMD 0x4 +#define MPAM_MSC_WRITE_CMD 0x5 + +#define MPAM_FB_ERR_SUCCESS 0 +#define MPAM_FB_ERR_NOT_SUPPORTED -1 +#define MPAM_FB_ERR_INVALID_PARAMETERS -2 +#define MPAM_FB_ERR_DENIED -3 +#define MPAM_FB_ERR_NOT_FOUND -4 +#define MPAM_FB_ERR_OUT_OF_RANGE -5 +#define MPAM_FB_ERR_BUSY -6 +#define MPAM_FB_ERR_COMMS_ERROR -7 +#define MPAM_FB_ERR_GENERIC_ERROR -8 +#define MPAM_FB_ERR_HW_ERROR -9 +#define MPAM_FB_ERR_PROTOCOL_ERROR -10 +#define MPAM_FB_ERR_IN_USE -11 + +#define MPAM_MSC_PROT_ID_MASK GENMASK(17, 10) +#define MPAM_MSC_TOKEN_MASK GENMASK(27, 18) + +struct mpam_fb_read_payload { + u32 msc_id; + u32 flags; + u32 reg_offset; +} __packed; + +struct mpam_fb_write_payload { + u32 msc_id; + u32 flags; + u32 reg_offset; + u32 value; +} __packed; + +#define PCC_CHAN_FLAGS_IRQ BIT(0) + +static atomic_t mpam_fb_token =3D ATOMIC_INIT(0); + +static void mpam_fb_build_version_message(unsigned int token, + void __iomem *msg_buf) +{ + struct acpi_pcct_ext_pcc_shared_memory __iomem *pcc_shmem =3D msg_buf; + + writel_relaxed(PCC_CHAN_FLAGS_IRQ, &pcc_shmem->flags); + writel_relaxed(MPAM_FB_PROT_HEADER_LEN, &pcc_shmem->length); + writel_relaxed(MPAM_PROTOCOL_VERSION | + FIELD_PREP(MPAM_MSC_TOKEN_MASK, token) | + FIELD_PREP(MPAM_MSC_PROT_ID_MASK, MPAM_FB_PROTOCOL_ID), + &pcc_shmem->command); +} + +static void mpam_fb_build_read_message(int msc_id, int reg, unsigned int t= oken, + void __iomem *msg_buf) +{ + struct acpi_pcct_ext_pcc_shared_memory __iomem *pcc_shmem =3D msg_buf; + struct mpam_fb_read_payload __iomem *payload =3D msg_buf + sizeof(*pcc_sh= mem); + int msg_size =3D MPAM_FB_PROT_HEADER_LEN + sizeof(*payload); + + writel_relaxed(PCC_CHAN_FLAGS_IRQ, &pcc_shmem->flags); + writel_relaxed(msg_size, &pcc_shmem->length); + writel_relaxed(MPAM_MSC_READ_CMD | + FIELD_PREP(MPAM_MSC_TOKEN_MASK, token) | + FIELD_PREP(MPAM_MSC_PROT_ID_MASK, MPAM_FB_PROTOCOL_ID), + &pcc_shmem->command); + + writel_relaxed(msc_id, &payload->msc_id); + writel_relaxed(0, &payload->flags); + writel_relaxed(reg, &payload->reg_offset); +} + +static void mpam_fb_build_write_message(int msc_id, int reg, u32 val, + unsigned int token, + void __iomem *msg_buf) +{ + struct acpi_pcct_ext_pcc_shared_memory __iomem *pcc_shmem =3D msg_buf; + struct mpam_fb_write_payload __iomem *payload =3D msg_buf + sizeof(*pcc_s= hmem); + int msg_size =3D MPAM_FB_PROT_HEADER_LEN + sizeof(*payload); + + writel_relaxed(PCC_CHAN_FLAGS_IRQ, &pcc_shmem->flags); + writel_relaxed(msg_size, &pcc_shmem->length); + writel_relaxed(MPAM_MSC_WRITE_CMD | + FIELD_PREP(MPAM_MSC_TOKEN_MASK, token) | + FIELD_PREP(MPAM_MSC_PROT_ID_MASK, MPAM_FB_PROTOCOL_ID), + &pcc_shmem->command); + + writel_relaxed(msc_id, &payload->msc_id); + writel_relaxed(0, &payload->flags); + writel_relaxed(reg, &payload->reg_offset); + writel_relaxed(val, &payload->value); +} + +static int mpam_fb_send_request(struct mpam_pcc_chan *pcc_chan, u32 msc_id, + u16 reg, u32 *result, int mpam_fb_command) +{ + unsigned int token =3D atomic_inc_return(&mpam_fb_token); + struct acpi_pcct_ext_pcc_shared_memory __iomem *pcc_shmem; + struct pcc_mbox_chan *chan; + void __iomem *payload_ofs; + u32 status; + int ret; + + if (!pcc_chan) + return -ENODEV; + + chan =3D pcc_chan->pcc_chan; + + /* prune token to fit into the 10 bits inside the command register */ + token =3D FIELD_GET(MPAM_MSC_TOKEN_MASK, + FIELD_PREP(MPAM_MSC_TOKEN_MASK, token)); + + guard(mutex)(&pcc_chan->pcc_chan_lock); + + switch (mpam_fb_command) { + case MPAM_MSC_WRITE_CMD: + mpam_fb_build_write_message(msc_id, reg, *result, + token, chan->shmem); + break; + case MPAM_MSC_READ_CMD: + mpam_fb_build_read_message(msc_id, reg, token, chan->shmem); + break; + case MPAM_PROTOCOL_VERSION: + mpam_fb_build_version_message(token, chan->shmem); + break; + } + + ret =3D mbox_send_message(chan->mchan, NULL); + if (ret < 0) + return ret; + + pcc_shmem =3D chan->shmem; + payload_ofs =3D chan->shmem + sizeof(*pcc_shmem); + status =3D readl(&pcc_shmem->command); + if (FIELD_GET(MPAM_MSC_TOKEN_MASK, status) !=3D token) + return -ETIMEDOUT; + + ret =3D readl(payload_ofs + 0x0); + if (ret < 0) { + switch (ret) { + case MPAM_FB_ERR_NOT_SUPPORTED: + return -EOPNOTSUPP; + case MPAM_FB_ERR_INVALID_PARAMETERS: + return -EINVAL; + case MPAM_FB_ERR_NOT_FOUND: + return -ENOENT; + case MPAM_FB_ERR_OUT_OF_RANGE: + return -ERANGE; + default: + return -EINVAL; + } + } + + if (mpam_fb_command !=3D MPAM_MSC_WRITE_CMD) + *result =3D readl(payload_ofs + 0x4); + + return 0; +} + +int mpam_fb_send_read_request(struct mpam_msc *msc, u16 reg, u32 *result) +{ + return mpam_fb_send_request(msc->pcc_chan, msc->mpam_fb_msc_id, + reg, result, MPAM_MSC_READ_CMD); +} + +int mpam_fb_send_write_request(struct mpam_msc *msc, u16 reg, u32 value) +{ + return mpam_fb_send_request(msc->pcc_chan, msc->mpam_fb_msc_id, + reg, &value, MPAM_MSC_WRITE_CMD); +} + +int mpam_fb_get_protocol_version(struct mpam_msc *msc) +{ + u32 version; + int ret; + + ret =3D mpam_fb_send_request(msc->pcc_chan, 0, + 0, &version, MPAM_PROTOCOL_VERSION); + if (ret) + return ret; + + return version; +} diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index b3a6ed9ed175..e4686ff0ba2e 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -57,6 +58,15 @@ struct mpam_garbage { struct platform_device *pdev; }; =20 +struct mpam_pcc_chan { + struct list_head pcc_chans; + struct mbox_client pcc_cl; + struct pcc_mbox_chan *pcc_chan; + struct mutex pcc_chan_lock; /* only one message at a time */ + struct kref refcount; + int subspace_id; +}; + struct mpam_msc { /* member of mpam_all_msc */ struct list_head all_msc_list; @@ -66,6 +76,8 @@ struct mpam_msc { =20 /* Not modified after mpam_is_enabled() becomes true */ enum mpam_msc_iface iface; + struct mpam_pcc_chan *pcc_chan; + int mpam_fb_msc_id; /* in its own name space */ u32 nrdy_usec; cpumask_t accessibility; bool has_extd_esr; @@ -511,6 +523,14 @@ static inline void mpam_resctrl_offline_cpu(unsigned i= nt cpu) { } static inline void mpam_resctrl_teardown_class(struct mpam_class *class) {= } #endif /* CONFIG_RESCTRL_FS */ =20 +/* MPAM-Fb Firmware-backed protocol wrappers */ +int mpam_fb_send_read_request(struct mpam_msc *msc, u16 reg, u32 *result); +int mpam_fb_send_write_request(struct mpam_msc *msc, u16 reg, u32 value); +int mpam_fb_get_protocol_version(struct mpam_msc *msc); + +#define MPAM_FB_PROT_HEADER_LEN sizeof(u32) +#define MPAM_FB_MAX_MSG_SIZE (MPAM_FB_PROT_HEADER_LEN + 4 * sizeof(u32)) + /* * MPAM MSCs have the following register layout. See: * Arm Memory System Resource Partitioning and Monitoring (MPAM) System diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h index f92a36187a52..002f56e15362 100644 --- a/include/linux/arm_mpam.h +++ b/include/linux/arm_mpam.h @@ -12,7 +12,7 @@ struct mpam_msc; =20 enum mpam_msc_iface { MPAM_IFACE_MMIO, /* a real MPAM MSC */ - MPAM_IFACE_PCC, /* a fake MPAM MSC */ + MPAM_IFACE_PCC, /* using the MPAM-Fb firmware redirection */ }; =20 enum mpam_class_types { --=20 2.43.0 From nobody Fri Jul 24 05:21:41 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E3DD7484232; Thu, 23 Jul 2026 15:55:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822136; cv=none; b=gIIF2R9OHrjDnQaUQbMm4Bg3jydFEt/YpIXAAOCFsGH9Js/+o+cyclZhhmzJmmXwv01vItCrJZVpqe6UMWvIY0AzvgQd/tOIBD5AQjA2Px8BLnu/0Qj2IilLer4jzBQn6x+3X+IPu54UbhBe+g4ou7VP+4Pb3w6iiuJkjclNw8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822136; c=relaxed/simple; bh=5UCprN2NQeJajnVI+vTpf77V2cpoFH+j7SWXoXNaRpk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oge6ahS5l/dLYNOd7a5tRwwMECC4zVoVSm6mj7JnN+eNET6gXpfePGbdvS0m42tfBTj68TzimkZ/brVLqgNIaFJVxFMwgBQ8y7FO32ASsis8I5HVPKWFEGlu+z0Ia859rhIOubsPUYMS8zfvs12fXTJWnbk2S1adsLZIHClwQUA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=vMyyzaAN; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="vMyyzaAN" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 057AC1595; Thu, 23 Jul 2026 08:55:30 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B6DB63F66F; Thu, 23 Jul 2026 08:55:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784822134; bh=5UCprN2NQeJajnVI+vTpf77V2cpoFH+j7SWXoXNaRpk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vMyyzaANv7YM4Yj2Et+PriXiRTUJr60ooXbBIscLpdyM9b7Mun3jnjYVXDpTVC6V1 5LzWczN14BPFgzrf+Lo92HVf/Rf6yS9e1lIzd66BQEq2vvKc2qHB6zwRNyJsC8o/Pz 0twMQEiO3L04+tflQYsbNpSt9PBOue/KGtLbZscg= From: Andre Przywara To: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/10] arm_mpam: prevent MPAM-Fb accesses inside IRQ handler Date: Thu, 23 Jul 2026 17:54:53 +0200 Message-ID: <20260723155454.1760823-10-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723155454.1760823-1-andre.przywara@arm.com> References: <20260723155454.1760823-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When an MPAM MSC gets into an error condition, it can trigger an error IRQ. We cannot really do much about those errors, but we at least query and log the error, then disable MPAM functionality. This error report relies on reading the MSC's error status register (ESR) in the IRQ handler, which is not possible for MPAM-Fb based MSC accesses, since they involve mailbox routines that might sleep. The same is true for clearing the interrupt at the source, which requires MSC access. For simplicity just skip the ESR read when the MSC is not using direct MMIO accesses, and just ignore the pending interrupts. We will wrap up MPAM functionality regardless, knowing the exact error value will not change that. Signed-off-by: Andre Przywara --- drivers/resctrl/mpam_devices.c | 36 +++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index b8108ed4b32c..fea3161ffbe9 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -2650,25 +2650,33 @@ static irqreturn_t __mpam_irq_handler(int irq, stru= ct mpam_msc *msc) &msc->accessibility))) return IRQ_NONE; =20 - mpam_msc_read_esr(msc, ®); + /* MPAM-Fb MSC accesses cannot be done in atomic context. */ + if (msc->iface =3D=3D MPAM_IFACE_MMIO) { + mpam_msc_read_esr(msc, ®); =20 - errcode =3D FIELD_GET(MPAMF_ESR_ERRCODE, reg); - if (!errcode) - return IRQ_NONE; + errcode =3D FIELD_GET(MPAMF_ESR_ERRCODE, reg); + if (!errcode) + return IRQ_NONE; =20 - /* Clear level triggered irq */ - mpam_msc_clear_esr(msc); + /* Clear level triggered irq */ + mpam_msc_clear_esr(msc); =20 - partid =3D FIELD_GET(MPAMF_ESR_PARTID_MON, reg); - pmg =3D FIELD_GET(MPAMF_ESR_PMG, reg); - ris =3D FIELD_GET(MPAMF_ESR_RIS, reg); + partid =3D FIELD_GET(MPAMF_ESR_PARTID_MON, reg); + pmg =3D FIELD_GET(MPAMF_ESR_PMG, reg); + ris =3D FIELD_GET(MPAMF_ESR_RIS, reg); =20 - pr_err_ratelimited("error irq from msc:%u '%s', partid:%u, pmg: %u, ris: = %u\n", - msc->id, mpam_errcode_names[errcode], partid, pmg, - ris); + pr_err_ratelimited("error irq from msc:%u '%s', partid:%u, pmg: %u, ris:= %u\n", + msc->id, mpam_errcode_names[errcode], partid, + pmg, ris); =20 - /* Disable this interrupt. */ - mpam_disable_msc_ecr(msc); + /* Disable this interrupt. */ + mpam_disable_msc_ecr(msc); + } else { + struct irq_data *d =3D irq_get_irq_data(irq); + + pr_err_ratelimited("unknown error irq %d/%ld from msc:%u\n", + irq, d ? irqd_to_hwirq(d) : -1, msc->id); + } =20 /* Are we racing with the thread disabling MPAM? */ if (!mpam_is_enabled()) --=20 2.43.0 From nobody Fri Jul 24 05:21:41 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9CC4B4DB569; Thu, 23 Jul 2026 15:55:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822140; cv=none; b=bWfBAwL6J0iGDcheN8UCAqpIQg7CiOKvro3D7dCqtGmdXSRuzfgqeu0iRUL0ulGcAR31n+sqRuP3dYWLe51yuATdD4J4guElbt2fOgeG70W/VB9J0MYI70rNpMJcU09RZM/AOxB09/LUGzcIVCLOdgZHAlulEDpaGl3cs4OVQQk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784822140; c=relaxed/simple; bh=puaj69qRzbjRL3t0MWqCptnRjoA/ON3kxaK9k+GBkkA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OgktPIIIjqq+D6o0yABVgwzWgtTQlSZ/1o1yufdltnZw/NHx4EuqM3Fwe+mgT6cjLQQp5iMDfHWiyHai9sLfR8kJ0HMw2647NFvqUJEU2TjCZ7EgOsPmfzT4tx1Q4pm+ic8yTa1GkuJUn5QHjjrX/4XFeWZvf7LWfX76QZj6+HE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=pUP7XKFR; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="pUP7XKFR" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B73F8176B; Thu, 23 Jul 2026 08:55:33 -0700 (PDT) Received: from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 835033F66F; Thu, 23 Jul 2026 08:55:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784822137; bh=puaj69qRzbjRL3t0MWqCptnRjoA/ON3kxaK9k+GBkkA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pUP7XKFRrLDn8C8dPk9DCU40gz879qwLoGCmizOxxvW6YtGOLeuteHtRQcFSSgqrB ND1Y6yf4Un9h4f43NB/B+BNt1N6OREtQMkA95z+EftjBDaAAA+uAu3803qtaMXWhex oBVVAMMw/gYf4vqz8diu7A9nNjdQO5+MHK3IgY3A= From: Andre Przywara To: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu Cc: Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 10/10] arm_mpam: detect and enable MPAM-Fb PCC support Date: Thu, 23 Jul 2026 17:54:54 +0200 Message-ID: <20260723155454.1760823-11-andre.przywara@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723155454.1760823-1-andre.przywara@arm.com> References: <20260723155454.1760823-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Arm MPAM-Fb specification [1] describes a protocol to access MSC registers through a firmware interface. This requires a shared memory region to hold the message, and a mailbox to trigger the access. For ACPI this is wrapped as a PCC channel, described using existing ACPI abstractions. Add code to parse those PCC table descriptions associated with an MSC, and store the parsed information in the MSC struct. There can be multiple PCC channels, and each channel can serve multiple MSCs, so we need to keep track of the channel usage, using a list and a refcount. This will be used by the MPAM-Fb access wrapper code. [1] https://developer.arm.com/documentation/den0144/latest Signed-off-by: Andre Przywara --- drivers/acpi/arm64/mpam.c | 6 +- drivers/resctrl/mpam_devices.c | 127 ++++++++++++++++++++++++++++++++- 2 files changed, 129 insertions(+), 4 deletions(-) diff --git a/drivers/acpi/arm64/mpam.c b/drivers/acpi/arm64/mpam.c index 84963a20c3e7..ca9b8754ae5f 100644 --- a/drivers/acpi/arm64/mpam.c +++ b/drivers/acpi/arm64/mpam.c @@ -220,8 +220,8 @@ static struct platform_device * __init acpi_mpam_parse_= msc(struct acpi_mpam_msc_ struct platform_device *pdev __free(platform_device_put) =3D platform_device_alloc("mpam_msc", tbl_msc->identifier); int next_res =3D 0, next_prop =3D 0, err; - /* pcc, nrdy, affinity and a sentinel */ - struct property_entry props[4] =3D { 0 }; + /* pcc, msc-id, nrdy, affinity and a sentinel */ + struct property_entry props[5] =3D { 0 }; /* mmio, 2xirq, no sentinel. */ struct resource res[3] =3D { 0 }; struct acpi_device *companion; @@ -256,6 +256,8 @@ static struct platform_device * __init acpi_mpam_parse_= msc(struct acpi_mpam_msc_ } else if (iface =3D=3D MPAM_IFACE_PCC) { props[next_prop++] =3D PROPERTY_ENTRY_U32("pcc-channel", tbl_msc->base_address); + props[next_prop++] =3D PROPERTY_ENTRY_U32("msc-id", + tbl_msc->identifier); } =20 acpi_mpam_parse_irqs(pdev, tbl_msc, res, &next_res); diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index fea3161ffbe9..fc4b5f87fbe9 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -19,14 +19,19 @@ #include #include #include +#include #include #include #include +#include #include #include #include #include =20 +#include +#include + #include "mpam_internal.h" =20 /* Values for the T241 errata workaround */ @@ -49,6 +54,86 @@ static LIST_HEAD(mpam_all_msc); =20 struct srcu_struct mpam_srcu; =20 +/* PCC channels might be serving multiple MSCs, so keep a refcounted list.= */ +static DEFINE_MUTEX(pcc_chan_list_lock); +static LIST_HEAD(pcc_chan_list); + +static void mpam_pcc_chan_release(struct kref *ref) +{ + struct mpam_pcc_chan *cur =3D container_of(ref, struct mpam_pcc_chan, + refcount); + + pcc_mbox_free_channel(cur->pcc_chan); + list_del(&cur->pcc_chans); + kfree(cur); +} + +static struct mpam_pcc_chan *mpam_pcc_chan_get(struct device *dev, + int subspace_id) +{ + struct mpam_pcc_chan *cur; + int ret; + + guard(mutex)(&pcc_chan_list_lock); + + list_for_each_entry(cur, &pcc_chan_list, pcc_chans) { + if (cur->subspace_id =3D=3D subspace_id) { + kref_get(&cur->refcount); + + return cur; + } + } + + cur =3D kzalloc_obj(*cur); + if (!cur) + return ERR_PTR(-ENOMEM); + + cur->pcc_cl.dev =3D dev; + cur->pcc_cl.tx_block =3D true; + + cur->pcc_chan =3D pcc_mbox_request_channel(&cur->pcc_cl, subspace_id); + if (IS_ERR(cur->pcc_chan)) { + long err =3D PTR_ERR(cur->pcc_chan); + + kfree(cur); + return ERR_PTR(err); + } + + /* Timeout based on the "nominal latency" from the PCC ACPI table. */ + cur->pcc_cl.tx_tout =3D cur->pcc_chan->latency * 5; + + ret =3D devm_mutex_init(dev, &cur->pcc_chan_lock); + if (ret) + return ERR_PTR(ret); + + cur->subspace_id =3D subspace_id; + kref_init(&cur->refcount); + + list_add_tail(&cur->pcc_chans, &pcc_chan_list); + + return cur; +} + +static int mpam_pcc_chan_put(struct mpam_pcc_chan *pcc_chan) +{ + struct mpam_pcc_chan *cur, *tmp; + + if (!pcc_chan) + return 0; + + guard(mutex)(&pcc_chan_list_lock); + + list_for_each_entry_safe(cur, tmp, &pcc_chan_list, pcc_chans) { + if (cur =3D=3D pcc_chan) { + kref_put(&cur->refcount, mpam_pcc_chan_release); + + return 0; + } + } + + return -ENOENT; +} + /* * Number of MSCs that have been probed. Once all MSCs have been probed MP= AM * can be enabled. @@ -2201,6 +2286,8 @@ static void mpam_msc_drv_remove(struct platform_devic= e *pdev) { struct mpam_msc *msc =3D platform_get_drvdata(pdev); =20 + mpam_pcc_chan_put(msc->pcc_chan); + mutex_lock(&mpam_list_lock); mpam_msc_destroy(msc); mutex_unlock(&mpam_list_lock); @@ -2211,7 +2298,7 @@ static void mpam_msc_drv_remove(struct platform_devic= e *pdev) static struct mpam_msc *do_mpam_msc_drv_probe(struct platform_device *pdev) { int err; - u32 tmp; + u32 pcc_subspace_id; struct mpam_msc *msc; struct resource *msc_res; struct device *dev =3D &pdev->dev; @@ -2259,7 +2346,8 @@ static struct mpam_msc *do_mpam_msc_drv_probe(struct = platform_device *pdev) if (err) return ERR_PTR(err); =20 - if (device_property_read_u32(&pdev->dev, "pcc-channel", &tmp)) + if (device_property_read_u32(&pdev->dev, "pcc-channel", + &pcc_subspace_id)) msc->iface =3D MPAM_IFACE_MMIO; else msc->iface =3D MPAM_IFACE_PCC; @@ -2275,6 +2363,41 @@ static struct mpam_msc *do_mpam_msc_drv_probe(struct= platform_device *pdev) } msc->mapped_hwpage_sz =3D msc_res->end - msc_res->start; msc->mapped_hwpage =3D io; + } else if (msc->iface =3D=3D MPAM_IFACE_PCC) { + u32 msc_id; + int ret; + + if (device_property_read_u32(&pdev->dev, "msc-id", &msc_id)) { + pr_err("missing MPAM-Fb MSC identifier\n"); + return ERR_PTR(-EINVAL); + } + msc->mpam_fb_msc_id =3D msc_id; + + msc->pcc_chan =3D mpam_pcc_chan_get(&pdev->dev, pcc_subspace_id); + if (IS_ERR(msc->pcc_chan)) { + pr_err("Failed to request MSC PCC channel\n"); + return ERR_CAST(msc->pcc_chan); + } + + if (msc->pcc_chan->pcc_chan->shmem_size < MPAM_FB_MAX_MSG_SIZE) { + pr_err("MPAM-Fb PCC channel size too small.\n"); + mpam_pcc_chan_put(msc->pcc_chan); + return ERR_PTR(-ENOMEM); + } + ret =3D mpam_fb_get_protocol_version(msc); + if (ret < 0) { + pr_err("Cannot query MPAM-Fb protocol version.\n"); + mpam_pcc_chan_put(msc->pcc_chan); + + /* ret is an MPAM-Fb error code, return a Linux one. */ + return ERR_PTR(-EIO); + } + if ((ret >> 16) !=3D 1) { + pr_err("Incompatible MPAM-Fb protocol version %d.%d\n", + ret >> 16, ret & 0xffff); + mpam_pcc_chan_put(msc->pcc_chan); + return ERR_PTR(-EINVAL); + } } else { return ERR_PTR(-EINVAL); } --=20 2.43.0