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Thu, 23 Jul 2026 08:41:57 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v19 1/4] pinctrl: renesas: rzg2l: Add SD channel POC support for RZ/G3L Date: Thu, 23 Jul 2026 16:41:47 +0100 Message-ID: <20260723154154.319674-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723154154.319674-1-biju.das.jz@bp.renesas.com> References: <20260723154154.319674-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das Add power-on control (POC) support for SD channels 1 and 2 on the RZ/G3L SoC (r9a08g046). Introduce PIN_CFG_IO_VMC_SD2 capability flag (bit 22) and SD_CH2_POC register offset (0x3024). Extend rzg2l_caps_to_pwr_reg() to return SD_CH2_POC when PIN_CFG_IO_VMC_SD2 is set. Replace RZG3L_MPXED_PIN_FUNCS() with RZG2L_MPXED_COMMON_PIN_FUNCS() for port PG and PH pins, dropping PIN_CFG_SOFT_PS which is inappropriate for SD pins, and annotate them with PIN_CFG_IO_VMC_SD1 and PIN_CFG_IO_VMC_SD2 respectively. Annotate all RZ/G3L SD0 dedicated pins (CLK, CMD, RST#, DS, DAT0=E2=80=93DA= T7) with PIN_CFG_IO_VMC_SD0 so that power-source register lookups work correctly for those pins. Add sd_ch2 field to rzg2l_register_offsets and rzg2l_pinctrl_reg_cache to save and restore the SD_CH2_POC register across suspend/resume cycles. Signed-off-by: Biju Das --- v18->v19: * No change. v17->v18: * Moved sd_ch2 variable near to sd_ch[]. v1->v17: * No change. --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 74 +++++++++++++++++-------- 1 file changed, 50 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index be52d47d77ae..e3e24ce917c9 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -69,6 +69,7 @@ #define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ #define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ #define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ +#define PIN_CFG_IO_VMC_SD2 BIT(22) /* known on RZ/G3L only */ =20 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ @@ -254,6 +255,7 @@ static const struct pin_config_item renesas_rzv2h_conf_= items[] =3D { * struct rzg2l_register_offsets - specific register offsets * @pwpr: PWPR register offset * @sd_ch: SD_CH register offset + * @sd_ch2: SD_CH2_POC register offset * @eth_poc: ETH_POC register offset * @oen: OEN register offset * @qspi: QSPI register offset @@ -262,6 +264,7 @@ static const struct pin_config_item renesas_rzv2h_conf_= items[] =3D { struct rzg2l_register_offsets { u16 pwpr; u16 sd_ch; + u16 sd_ch2; u16 eth_poc; u16 oen; u16 qspi; @@ -368,6 +371,7 @@ struct rzg2l_pinctrl_pin_settings { * @nod: NOD registers cache * @clone: Clone register cache * @sd_ch: SD_CH registers cache + * @sd_ch2: SD_CH2_POC registers cache * @eth_poc: ET_POC registers cache * @oen: Output Enable register cache * @other_poc: OTHER_POC register cache @@ -386,6 +390,7 @@ struct rzg2l_pinctrl_reg_cache { u32 *nod[2]; u32 clone; u8 sd_ch[2]; + u8 sd_ch2; u8 eth_poc[2]; u8 oen; u8 other_poc; @@ -474,20 +479,32 @@ static const u64 r9a08g046_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG3L_MPXED_PIN_FUNCS(B)), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG2L_MPXED_COMMON_PIN_FUNCS(B) = | PIN_CFG_IEN | + PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 6, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO= )), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 7, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO= )), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG3L_MPXED_PIN_FUNCS(B)), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), - RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_C= FG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG2L_MPXED_COMMON_PIN_FUNCS(B) | + PIN_CFG_IEN | PIN_CFG_IO_VMC_SD2), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 0, RZG3L_MPXED_PIN_FUNCS(A) | PIN_C= FG_IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 1, RZG3L_MPXED_PIN_FUNCS(A)), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 2, RZG3L_MPXED_PIN_FUNCS(A)), @@ -1053,6 +1070,8 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_r= egister_offsets *regs, return SD_CH(regs->sd_ch, 0); if (caps & PIN_CFG_IO_VMC_SD1) return SD_CH(regs->sd_ch, 1); + if (caps & PIN_CFG_IO_VMC_SD2) + return regs->sd_ch2; if (caps & PIN_CFG_IO_VMC_ETH0) return ETH_POC(regs->eth_poc, 0); if (caps & PIN_CFG_IO_VMC_ETH1) @@ -2677,28 +2696,28 @@ static const struct rzg2l_dedicated_configs rzg3l_d= edicated_pins[] =3D { (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, { "SCIF0_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, - { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B | PIN_CFG_IO_VM= C_SD0) }, { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, - { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B | PIN_CFG_IO_V= MC_SD0) }, { "SD0_DS", RZG2L_SINGLE_PIN_PACK(0x9, 5, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT0", RZG2L_SINGLE_PIN_PACK(0x0a, 0, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT1", RZG2L_SINGLE_PIN_PACK(0x0a, 1, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT2", RZG2L_SINGLE_PIN_PACK(0x0a, 2, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT3", RZG2L_SINGLE_PIN_PACK(0x0a, 3, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT4", RZG2L_SINGLE_PIN_PACK(0x0a, 4, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT5", RZG2L_SINGLE_PIN_PACK(0x0a, 5, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT6", RZG2L_SINGLE_PIN_PACK(0x0a, 6, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, { "SD0_DAT7", RZG2L_SINGLE_PIN_PACK(0x0a, 7, - (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD | PIN_CFG_IO_VMC_SD0)) }, }; =20 static const u32 r9a08g046_clone_channel_data[] =3D { @@ -3672,6 +3691,9 @@ static int rzg2l_pinctrl_suspend_noirq(struct device = *dev) cache->eth_poc[i] =3D readb(pctrl->base + ETH_POC(regs->eth_poc, i)); } =20 + if (regs->sd_ch2) + cache->sd_ch2 =3D readb(pctrl->base + regs->sd_ch2); + if (regs->qspi) cache->qspi =3D readb(pctrl->base + regs->qspi); cache->oen =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); @@ -3724,6 +3746,9 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) rzg2l_oen_write_with_pwpr(pctrl, cache->oen); raw_spin_unlock_irqrestore(&pctrl->lock, flags); =20 + if (regs->sd_ch2) + writeb(cache->sd_ch2, pctrl->base + regs->sd_ch2); + for (u8 i =3D 0; i < 2; i++) { if (regs->sd_ch) writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); @@ -3791,6 +3816,7 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg =3D { .regs =3D { .pwpr =3D 0x3000, .sd_ch =3D 0x3004, + .sd_ch2 =3D 0x3024, .eth_poc =3D 0x3010, .oen =3D 0x3018, .other_poc =3D OTHER_POC, --=20 2.43.0 From nobody Fri Jul 24 05:23:04 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF24546E00F for ; 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Thu, 23 Jul 2026 08:41:58 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:f073:32ed:a057:cd3d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957af5d3c2sm3411345e9.1.2026.07.23.08.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 08:41:58 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v19 2/4] arm64: dts: renesas: r9a08g046: Add SDHI nodes for RZ/G3L SoC and SDHI1 pincontrol on SMARC EVK Date: Thu, 23 Jul 2026 16:41:48 +0100 Message-ID: <20260723154154.319674-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723154154.319674-1-biju.das.jz@bp.renesas.com> References: <20260723154154.319674-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add device tree nodes for the three SDHI controllers (SDHI{0,1,2}) on the RZ/G3L SoC (r9a08g046) and enable SDHI1 on the RZ/G3L SMARC EVK platform with pincontrol and GPIO-based voltage switching regulator support. Signed-off-by: Biju Das --- v18->v19: * Renamed aclk->aclks as it is AXI bus slave clock. * Rearranged AXI bus master and slave clocks as per binding. v17->v18: * No change. * This patch depend on [1] [1] https://lore.kernel.org/all/20260622155610.184271-2-biju.das.jz@bp.rene= sas.com/ v1->v17: * No change. --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 73 ++++++++++++++- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 88 +++++++++++++++++++ 2 files changed, 160 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g046.dtsi index c63a857f0e5b..3665ccbdd91b 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -762,9 +762,80 @@ dmac: dma-controller@11820000 { dma-channels =3D <16>; }; =20 + sdhi0: mmc@11c00000 { + compatible =3D "renesas,sdhi-r9a08g046"; + reg =3D <0x0 0x11c00000 0 0x10000>; + interrupts =3D , + ; + clocks =3D <&cpg CPG_MOD R9A08G046_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A08G046_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A08G046_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A08G046_SDHI0_IACLKM>, + <&cpg CPG_MOD R9A08G046_SDHI0_IACLKS>; + clock-names =3D "core", "clkh", "cd", "aclkm", "aclks"; + max-frequency =3D <150000000>; + resets =3D <&cpg R9A08G046_SDHI0_IXRST>, + <&cpg R9A08G046_SDHI0_IXRSTAXIM>, + <&cpg R9A08G046_SDHI0_IXRSTAXIS>; + reset-names =3D "rst", "axim", "axis"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + sdhi1: mmc@11c10000 { + compatible =3D "renesas,sdhi-r9a08g046"; reg =3D <0x0 0x11c10000 0 0x10000>; - /* placeholder */ + interrupts =3D , + ; + clocks =3D <&cpg CPG_MOD R9A08G046_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A08G046_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A08G046_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A08G046_SDHI1_IACLKM>, + <&cpg CPG_MOD R9A08G046_SDHI1_IACLKS>; + clock-names =3D "core", "clkh", "cd", "aclkm", "aclks"; + max-frequency =3D <150000000>; + resets =3D <&cpg R9A08G046_SDHI1_IXRST>, + <&cpg R9A08G046_SDHI1_IXRSTAXIM>, + <&cpg R9A08G046_SDHI1_IXRSTAXIS>; + reset-names =3D "rst", "axim", "axis"; + power-domains =3D <&cpg>; + status =3D "disabled"; + + sdhi1_vqmmc: vqmmc-regulator { + regulator-name =3D "SDHI1-VQMMC"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <1200>; + status =3D "disabled"; + }; + }; + + sdhi2: mmc@11c20000 { + compatible =3D "renesas,sdhi-r9a08g046"; + reg =3D <0x0 0x11c20000 0 0x10000>; + interrupts =3D , + ; + clocks =3D <&cpg CPG_MOD R9A08G046_SDHI2_IMCLK>, + <&cpg CPG_MOD R9A08G046_SDHI2_CLK_HS>, + <&cpg CPG_MOD R9A08G046_SDHI2_IMCLK2>, + <&cpg CPG_MOD R9A08G046_SDHI2_IACLKM>, + <&cpg CPG_MOD R9A08G046_SDHI2_IACLKS>; + clock-names =3D "core", "clkh", "cd", "aclkm", "aclks"; + max-frequency =3D <150000000>; + resets =3D <&cpg R9A08G046_SDHI2_IXRST>, + <&cpg R9A08G046_SDHI2_IXRSTAXIM>, + <&cpg R9A08G046_SDHI2_IXRSTAXIS>; + reset-names =3D "rst", "axim", "axis"; + power-domains =3D <&cpg>; + status =3D "disabled"; + + sdhi2_vqmmc: vqmmc-regulator { + regulator-name =3D "SDHI2-VQMMC"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-ramp-delay =3D <1200>; + status =3D "disabled"; + }; }; =20 eth0: ethernet@11c30000 { diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a08g046l48-smarc.dts index 5289efd1a430..0b6b7e109200 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -14,6 +14,7 @@ #define SW_GPIO4 1 #define SW_I3C_EN 0 #define SW_SER0_PMOD 1 +#define SW_SDIO_M2E 0 =20 #define PMOD_GPIO4 0 #define PMOD_GPIO6 0 @@ -38,6 +39,7 @@ / { aliases { i2c2 =3D &i2c2; i2c3 =3D &i2c3; + mmc1 =3D &sdhi1; serial0 =3D &rsci2; serial1 =3D &rsci3; serial2 =3D &rsci1; @@ -69,6 +71,19 @@ codec_dai: codec { }; }; #endif + +#if RZ_BOOT_MODE3 + vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { + compatible =3D "regulator-gpio"; + regulator-name =3D "SD1_PVDD"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&pinctrl RZG3L_GPIO(J, 1) GPIO_ACTIVE_HIGH>; + gpios-states =3D <0>; + states =3D <3300000 0>, <1800000 1>; + regulator-ramp-delay =3D <1200>; + }; +#endif }; =20 &i2c2 { @@ -175,6 +190,68 @@ scif0_pins: scif0 { power-source =3D <1800>; }; =20 +#if RZ_BOOT_MODE3 + sd1-pwr-en-hog { + gpio-hog; + gpios =3D ; + output-high; + line-name =3D "sd1_pwr_en"; + }; +#endif + + sdhi1_pins: sd1 { + sd1-cd { + pinmux =3D ; /* SD1_CD */ + }; + + sd1-clk { + pinmux =3D ; /* SD1_CLK */ + power-source =3D <3300>; + }; + + sd1-cmd { + pinmux =3D ; /* SD1_CMD */ + input-enable; + power-source =3D <3300>; + bias-pull-up; + }; + + sd1-data { + pinmux =3D , /* SD1_DAT0 */ + , /* SD1_DAT1 */ + , /* SD1_DAT2 */ + ; /* SD1_DAT3 */ + input-enable; + power-source =3D <3300>; + }; + }; + + sdhi1_uhs_pins: sd1-uhs { + sd1-cd { + pinmux =3D ; /* SD1_CD */ + }; + + sd1-clk { + pinmux =3D ; /* SD1_CLK */ + power-source =3D <1800>; + }; + + sd1-cmd { + pinmux =3D ; /* SD1_CMD */ + input-enable; + power-source =3D <1800>; + }; + + sd1-data { + pinmux =3D , /* SD1_DAT0 */ + , /* SD1_DAT1 */ + , /* SD1_DAT2 */ + ; /* SD1_DAT3 */ + input-enable; + power-source =3D <1800>; + }; + }; + ssi0_pins: ssi0 { pinmux =3D , /* SSIF0_RXD */ , /* SSIF0_BCK */ @@ -230,6 +307,17 @@ &scif0 { pinctrl-names =3D "default"; }; =20 +#if RZ_BOOT_MODE3 +&sdhi1 { + pinctrl-0 =3D <&sdhi1_pins>; + pinctrl-1 =3D <&sdhi1_uhs_pins>; + pinctrl-names =3D "default", "state_uhs"; + + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <&vqmmc_sd1_pvdd>; +}; +#endif + #if !SW_SD2_EN &ssi0 { clocks =3D <&cpg CPG_MOD R9A08G046_SSI0_PCLK2>, --=20 2.43.0 From nobody Fri Jul 24 05:23:04 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBB6847124B for ; Thu, 23 Jul 2026 15:42:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784821328; cv=none; b=g+4er7X6fNaA0kpo5dR8JjVrk3f9L+d/tWOClmKQ7LgXIOD8IMzbD6gtniUyTZcSZMHg0+lRrkeNIKocYMgyPHCHnvQ+dn8jiGKSpoFGRuUXPtU4GLL6fut7phhqT6cdGTDt3yttFzq5i5XDKGotcdWsBPbXwMJeLPUaub3HVbg= ARC-Message-Signature: i=1; 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Thu, 23 Jul 2026 08:41:59 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:f073:32ed:a057:cd3d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957af5d3c2sm3411345e9.1.2026.07.23.08.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 08:41:59 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v19 3/4] arm64: dts: renesas: rzg3l-smarc-som: Enable SD/eMMC on SDHI0 Date: Thu, 23 Jul 2026 16:41:49 +0100 Message-ID: <20260723154154.319674-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723154154.319674-1-biju.das.jz@bp.renesas.com> References: <20260723154154.319674-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for enabling SD card or eMMC on SDHI0 on the RZ/G3L SMARC SoM. The selection between SD and eMMC is controlled by the SW_SD0_DEV_SEL macro in the board DTS, which must match the position of switch SYS.1 on the SoM. By default, eMMC is enabled. Signed-off-by: Biju Das --- v18->v19: * Split SD0_CLK and SD0_CMD separate as input enable not available for SD0_CLK. * Added bias_pull_down, input enable, default drive strength for SD0_DS. * Added input enable for SD0_CMD and SD0_DAT* * Added default drive-strength for all SD0 pins except cd. v17->v18: * No change. v1->v17: * No change. --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 1 + .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 145 ++++++++++++++++++ 2 files changed, 146 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm6= 4/boot/dts/renesas/r9a08g046l48-smarc.dts index 0b6b7e109200..96cc7ee46a6a 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -9,6 +9,7 @@ =20 /* Switch selection settings */ #define RZ_BOOT_MODE3 1 +#define SW_SD0_DEV_SEL 0 #define SW_SD2_EN 0 #define SW_DPI_EN 0 #define SW_GPIO4 1 diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3l-smarc-som.dtsi index 091a227233cb..c365b8087520 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -9,6 +9,10 @@ * Please set the below switch position on the SoM and the corresponding m= acro * on the board DTS: * + * Switch position SYS.1, Macro SW_SD0_DEV_SEL: + * 0 - SD0 is connected to eMMC (default) + * 1 - SD0 is connected to uSD0 card + * * Switch position SYS.2, Macro SW_I3C_EN: * 0 - SMARC_I2C_GP is enabled * 1 - I3C is enabled @@ -37,6 +41,7 @@ aliases { ethernet0 =3D ð0; ethernet1 =3D ð1; i2c0 =3D &i2c0; + mmc0 =3D &sdhi0; }; =20 memory@48000000 { @@ -63,6 +68,19 @@ reg_3p3v: regulator-3p3v { regulator-always-on; }; =20 +#if SW_SD0_DEV_SEL + vqmmc_sd0_pvdd: vqmmc-sd0-pvdd { + compatible =3D "regulator-gpio"; + regulator-name =3D "SD0_PVDD"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios =3D <&pinctrl RZG3L_GPIO(L, 4) GPIO_ACTIVE_HIGH>; + gpios-states =3D <0>; + states =3D <3300000 0>, <1800000 1>; + regulator-ramp-delay =3D <1200>; + }; +#endif + x2_clk: x2-clock { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -216,7 +234,134 @@ i2c0_pins: i2c0 { pinmux =3D , /* RIIC0_SCL */ ; /* RIIC0_SDA */ }; + + sd0-pwr-en-hog { + gpio-hog; + gpios =3D ; + output-high; + line-name =3D "sd0_pwr_en"; + }; + + sdhi0_emmc_pins: sd0-emmc { + sd0-clk { + pins =3D "SD0_CLK"; + power-source =3D <1800>; + drive-strength-microamp =3D <9000>; + }; + + sd0-cmd { + pins =3D "SD0_CMD"; + input-enable; + drive-strength-microamp =3D <9000>; + power-source =3D <1800>; + }; + + sd0-data { + pins =3D "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", + "SD0_DAT4", "SD0_DAT5", "SD0_DAT6", "SD0_DAT7"; + input-enable; + drive-strength-microamp =3D <9000>; + power-source =3D <1800>; + }; + + sd0-rst { + pins =3D "SD0_RST#"; + drive-strength-microamp =3D <9000>; + power-source =3D <1800>; + }; + + sd0-ds { + pins =3D "SD0_DS"; + input-enable; + bias-pull-down; + drive-strength-microamp =3D <9000>; + power-source =3D <1800>; + }; + }; + + sdhi0_usd_pins: sd0-usd { + sd0-cd { + pinmux =3D ; /* SD0_CD */ + }; + + sd0-clk { + pins =3D "SD0_CLK"; + drive-strength-microamp =3D <8000>; + power-source =3D <3300>; + }; + + sd0-cmd { + pins =3D "SD0_CMD"; + input-enable; + drive-strength-microamp =3D <8000>; + power-source =3D <3300>; + }; + + sd0-data { + pins =3D "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3"; + input-enable; + drive-strength-microamp =3D <8000>; + power-source =3D <3300>; + }; + }; + + sdhi0_usd_uhs_pins: sd0-usd-uhs { + sd0-cd { + pinmux =3D ; /* SD0_CD */ + }; + + sd0-clk { + pins =3D "SD0_CLK"; + drive-strength-microamp =3D <9000>; + power-source =3D <1800>; + }; + + sd0-cmd { + pins =3D "SD0_CMD"; + input-enable; + drive-strength-microamp =3D <9000>; + power-source =3D <1800>; + }; + + sd0-data { + pins =3D "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3"; + input-enable; + drive-strength-microamp =3D <9000>; + power-source =3D <1800>; + }; + }; +}; + +#if (SW_SD0_DEV_SEL) +&sdhi0 { + pinctrl-0 =3D <&sdhi0_usd_pins>; + pinctrl-1 =3D <&sdhi0_usd_uhs_pins>; + pinctrl-names =3D "default", "state_uhs"; + + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <&vqmmc_sd0_pvdd>; + bus-width =3D <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status =3D "okay"; +}; +#else +&sdhi0 { + pinctrl-0 =3D <&sdhi0_emmc_pins>; + pinctrl-1 =3D <&sdhi0_emmc_pins>; + pinctrl-names =3D "default", "state_uhs"; + + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <®_1p8v>; + bus-width =3D <8>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; 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Thu, 23 Jul 2026 08:41:59 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v19 4/4] arm64: dts: renesas: rzg3l-smarc-som: Enable SDHI2 Date: Thu, 23 Jul 2026 16:41:50 +0100 Message-ID: <20260723154154.319674-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723154154.319674-1-biju.das.jz@bp.renesas.com> References: <20260723154154.319674-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Enable SDHI2 on the RZ/G3L SMARC EVK platform using the internal voltage regulator for voltage switching. SDHI2 signals are muxed with I2S0; the selection is controlled by the SW_SD2_EN macro in the board DTS, which must match the position of switch SYS.4 on the SoM. By default, I2S0 is enabled. Signed-off-by: Biju Das --- v18->v19: * No change. v17->v18: * No change. v1->v17: * No change. --- .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3l-smarc-som.dtsi index c365b8087520..1b72c310830e 100644 --- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -42,6 +42,7 @@ aliases { ethernet1 =3D ð1; i2c0 =3D &i2c0; mmc0 =3D &sdhi0; + mmc2 =3D &sdhi2; }; =20 memory@48000000 { @@ -330,6 +331,74 @@ sd0-data { power-source =3D <1800>; }; }; + + sdhi2_pins: sd2 { + sd2-cd { + pinmux =3D ; /* SD2_CD */ + }; + + sd2-clk { + pinmux =3D ; /* SD2_CLK */ + power-source =3D <3300>; + }; + + sd2-cmd { + pinmux =3D ; /* SD2_CMD */ + input-enable; + power-source =3D <3300>; + }; + + sd2-data { + pinmux =3D , /* SD2_DAT0 */ + , /* SD2_DAT1 */ + , /* SD2_DAT2 */ + ; /* SD2_DAT3 */ + input-enable; + power-source =3D <3300>; + }; + + sd2-iovs { + pinmux =3D ; /* SD2_IOVS */ + }; + + sd2-pwen { + pinmux =3D ; /* SD2_PWEN */ + }; + }; + + sdhi2_pins_uhs: sd2-uhs { + sd2-cd { + pinmux =3D ; /* SD2_CD */ + }; + + sd2-clk { + pinmux =3D ; /* SD2_CLK */ + power-source =3D <1800>; + }; + + sd2-cmd { + pinmux =3D ; /* SD2_CMD */ + input-enable; + power-source =3D <1800>; + }; + + sd2-data { + pinmux =3D , /* SD2_DAT0 */ + , /* SD2_DAT1 */ + , /* SD2_DAT2 */ + ; /* SD2_DAT3 */ + input-enable; + power-source =3D <1800>; + }; + + sd2-iovs { + pinmux =3D ; /* SD2_IOVS */ + }; + + sd2-pwen { + pinmux =3D ; /* SD2_PWEN */ + }; + }; }; =20 #if (SW_SD0_DEV_SEL) @@ -363,6 +432,25 @@ &sdhi0 { }; #endif =20 +#if SW_SD2_EN +&sdhi2 { + pinctrl-0 =3D <&sdhi2_pins>; + pinctrl-1 =3D <&sdhi2_pins_uhs>; + pinctrl-names =3D "default", "state_uhs"; + + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <&sdhi2_vqmmc>; + bus-width =3D <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status =3D "okay"; +}; + +&sdhi2_vqmmc { + status =3D "okay"; +}; +#endif + &wdt0 { timeout-sec =3D <60>; status =3D "okay"; --=20 2.43.0