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Thu, 23 Jul 2026 08:10:28 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Wolfram Sang , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Conor Dooley Subject: [PATCH v22 01/13] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC Date: Thu, 23 Jul 2026 16:10:05 +0100 Message-ID: <20260723151024.318918-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> References: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI controller is similar to RZ/G2L but has five clocks (core, clkh, cd, aclkm, aclks) and three resets (rst, axim, axis), so update the clocks/clock-names maximum to 5 and resets/reset-names maximum to 3. It has an internal divider for all modes except HS400, and a 2048-bit divider compared to 512 on others. Acked-by: Conor Dooley Signed-off-by: Biju Das --- v21->v22: * No change. v20->v21: * No change. v19->v20: * No change. v18->v19: * Updated commit description * Updated clock and reset description with AXI master and AXI slave * Added else condition for reset and reset-names. * Renamed aclk->aclkm and reordered the axi clocks similar to resets. * Retained the tag as the changes are trivial. v17->v18: * No change. v1->v17: * Collected tag. --- .../devicetree/bindings/mmc/renesas,sdhi.yaml | 108 +++++++++++++----- 1 file changed, 81 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Docu= mentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 4d66966ce290..6d229a41a4b5 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -18,6 +18,7 @@ properties: - renesas,sdhi-r7s9210 # SH-Mobile AG5 - renesas,sdhi-r8a73a4 # R-Mobile APE6 - renesas,sdhi-r8a7740 # R-Mobile A1 + - renesas,sdhi-r9a08g046 # RZ/G3L - renesas,sdhi-r9a09g057 # RZ/V2H(P) - renesas,sdhi-sh73a0 # R-Mobile APE6 - items: @@ -86,11 +87,11 @@ properties: =20 clocks: minItems: 1 - maxItems: 4 + maxItems: 5 =20 clock-names: minItems: 1 - maxItems: 4 + maxItems: 5 =20 dmas: minItems: 4 @@ -116,7 +117,12 @@ properties: maxItems: 1 =20 resets: - maxItems: 1 + minItems: 1 + maxItems: 3 + + reset-names: + minItems: 1 + maxItems: 3 =20 pinctrl-0: minItems: 1 @@ -155,60 +161,106 @@ allOf: properties: compatible: contains: - enum: - - renesas,sdhi-r9a09g057 - - renesas,rzg2l-sdhi + const: renesas,sdhi-r9a08g046 then: properties: clocks: items: - description: IMCLK, SDHI channel main clock1. - description: CLK_HS, SDHI channel High speed clock which o= perates - 4 times that of SDHI channel main clock1. + 2 times that of SDHI channel main clock1. - description: IMCLK2, SDHI channel main clock2. When this c= lock is turned off, external SD card detection cannot= be detected. - - description: ACLK, SDHI channel bus clock. + - description: IACLKM, SDHI channel AXI master bus clock. + - description: IACLKS, SDHI channel AXI slave bus clock. clock-names: items: - const: core - const: clkh - const: cd - - const: aclk + - const: aclkm + - const: aclks + resets: + items: + - description: rst, Core reset. + - description: axim, SDHI channel AXI master bus reset. + - description: axis, SDHI channel AXI slave bus reset. + reset-names: + items: + - const: rst + - const: axim + - const: axis required: - clock-names - resets + - reset-names else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 if: properties: compatible: contains: enum: - - renesas,rcar-gen2-sdhi - - renesas,rcar-gen3-sdhi - - renesas,rcar-gen4-sdhi + - renesas,sdhi-r9a09g057 + - renesas,rzg2l-sdhi then: properties: clocks: - minItems: 1 - maxItems: 3 - clock-names: - minItems: 1 - uniqueItems: true items: - - const: core - - enum: [ clkh, cd ] - - const: cd - else: - properties: - clocks: - minItems: 1 - maxItems: 2 + - description: IMCLK, SDHI channel main clock1. + - description: CLK_HS, SDHI channel High speed clock which= operates + 4 times that of SDHI channel main clock1. + - description: IMCLK2, SDHI channel main clock2. When this= clock is + turned off, external SD card detection cann= ot be + detected. + - description: ACLK, SDHI channel bus clock. clock-names: - minItems: 1 items: - const: core + - const: clkh - const: cd + - const: aclk + resets: + maxItems: 1 + required: + - clock-names + - resets + else: + if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-sdhi + - renesas,rcar-gen3-sdhi + - renesas,rcar-gen4-sdhi + then: + properties: + clocks: + minItems: 1 + maxItems: 3 + clock-names: + minItems: 1 + uniqueItems: true + items: + - const: core + - enum: [ clkh, cd ] + - const: cd + else: + properties: + clocks: + minItems: 1 + maxItems: 2 + clock-names: + minItems: 1 + items: + - const: core + - const: cd =20 - if: properties: @@ -247,7 +299,9 @@ allOf: properties: compatible: contains: - const: renesas,sdhi-r9a09g057 + enum: + - renesas,sdhi-r9a08g046 + - renesas,sdhi-r9a09g057 then: properties: vqmmc-regulator: --=20 2.43.0 From nobody Fri Jul 24 05:23:06 2026 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A81144570E9 for ; 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charset="utf-8" From: Biju Das Clean up coding style inconsistencies across the Renesas SDHI host driver files. Remove redundant internal spacing in the struct definitions and static initializers to enforce a single space separator or uniform tabs, aligning the code with standard kernel formatting guidelines. While at it, add a "Sentinel." comment block to the empty terminating entries of the Open Firmware (OF) device matching tables to improve code readability and explicitly mark the table boundaries. Reviewed-by: Wolfram Sang Signed-off-by: Biju Das --- v21->v22: * No change. v20->v21: * No change. v19->v20: * No change. v18->v19: * Updated commit description. v17->v18: * Merged patch#4 and #5 * Updated commit description * Annotate the empty sentinel entries in the OF match tables with a "Sentinel." comment for clarity. * Retained the tag as it is trivial cleanups. v1->v17: * No change. --- drivers/mmc/host/renesas_sdhi.h | 2 +- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 6 +++--- drivers/mmc/host/renesas_sdhi_sys_dmac.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index afc36a407c2c..09bf9b24a8c3 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -25,7 +25,7 @@ struct renesas_sdhi_scc { =20 struct renesas_sdhi_of_data { unsigned long tmio_flags; - u32 tmio_ocr_mask; + u32 tmio_ocr_mask; unsigned long capabilities; unsigned long capabilities2; enum dma_slave_buswidth dma_buswidth; diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index 0c3967f758c2..b3f4a5f8dec0 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -271,8 +271,8 @@ static const struct renesas_sdhi_of_data_with_quirks of= _rcar_gen3_nohs400_compat }; =20 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = =3D { - .of_data =3D &of_data_rza2, - .quirks =3D &sdhi_quirks_fixed_addr, + .of_data =3D &of_data_rza2, + .quirks =3D &sdhi_quirks_fixed_addr, }; =20 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] =3D= { @@ -293,7 +293,7 @@ static const struct of_device_id renesas_sdhi_internal_= dmac_of_match[] =3D { { .compatible =3D "renesas,rzg2l-sdhi", .data =3D &of_rzg2l_compatible, }, { .compatible =3D "renesas,rcar-gen3-sdhi", .data =3D &of_rcar_gen3_compa= tible, }, { .compatible =3D "renesas,rcar-gen4-sdhi", .data =3D &of_rcar_gen3_compa= tible, }, - {}, + { /* Sentinel. */ } }; MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); =20 diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/re= nesas_sdhi_sys_dmac.c index 426308b73b49..7ae488e5c1e0 100644 --- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c @@ -27,7 +27,7 @@ #define TMIO_MMC_MIN_DMA_LEN 8 =20 static const struct renesas_sdhi_of_data of_default_cfg =3D { - .tmio_flags =3D TMIO_MMC_HAS_IDLE_WAIT, + .tmio_flags =3D TMIO_MMC_HAS_IDLE_WAIT, }; =20 static const struct renesas_sdhi_of_data of_rz_compatible =3D { @@ -89,7 +89,7 @@ static const struct of_device_id renesas_sdhi_sys_dmac_of= _match[] =3D { { .compatible =3D "renesas,rcar-gen1-sdhi", .data =3D &of_rcar_gen1_compa= tible, }, { .compatible =3D "renesas,rcar-gen2-sdhi", .data =3D &of_rcar_gen2_compa= tible, }, { .compatible =3D "renesas,sdhi-shmobile" }, - {}, + { /* Sentinel. */ } }; MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match); =20 --=20 2.43.0 From nobody Fri Jul 24 05:23:06 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D7B54570DF for ; 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charset="utf-8" From: Biju Das The clock divider on the RZ/G3L SoC features an 11-bit width, requiring a wider clock mask (0x200000200) in renesas_sdhi_set_clock() than the historically hardcoded 32-bit value (0x80000080). To accommodate SoC variants with wider clock divider masks, expand the internal clock control variables (clk and clock) from u32 to u64. Introduce a clk_mask field to both struct renesas_sdhi_of_data and struct tmio_mmc_data to allow platform configuration data to supply SoC-specific mask properties. Update renesas_sdhi_set_clock() to read the dynamic mask from platform data. During the probe phase, assign a default mask fallback of SDHI_CLK_MASK_DEFAULT (0x80000080) if no specific mask is specified, ensuring backward compatibility with existing hardware variants. Finally, explicitly populate clk_mask with the default value across all current internal and system DMAC configuration profiles, in preparation for the upcoming RZ/G3L clock customization. Signed-off-by: Biju Das --- v21->v22: * No change. v20->v21: * No change. v19->v20: * Replaced the check mmd->clk_mask with mmc_data->clk_mask and moved the code after assignment of variable mmd, this ensures assigning the default values for non-DT platforms and DT platforms with no device data. v18->v19: * Fixed the clk_mask for non-DT platforms. v18: * New patch dropping struct renesas_sdhi_hw_info instead using renesas_sdhi_of_data and tmio_mmc_data. --- drivers/mmc/host/renesas_sdhi.h | 2 ++ drivers/mmc/host/renesas_sdhi_core.c | 8 ++++++-- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 3 +++ drivers/mmc/host/renesas_sdhi_sys_dmac.c | 4 ++++ include/linux/platform_data/tmio.h | 1 + 5 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index 09bf9b24a8c3..f926a36f213c 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -22,6 +22,7 @@ struct renesas_sdhi_scc { }; =20 #define SDHI_FLAG_NEED_CLKH_FALLBACK BIT(0) +#define SDHI_CLK_MASK_DEFAULT 0x80000080 =20 struct renesas_sdhi_of_data { unsigned long tmio_flags; @@ -37,6 +38,7 @@ struct renesas_sdhi_of_data { unsigned int max_blk_count; unsigned short max_segs; unsigned long sdhi_flags; + u64 clk_mask; }; =20 #define SDHI_CALIB_TABLE_MAX 32 diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index f9ec78d699f4..604d886e483c 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -194,7 +194,7 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host= *host, unsigned int new_clock) { unsigned int clk_margin; - u32 clk =3D 0, clock; + u64 clk =3D 0, clock; =20 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); @@ -213,7 +213,7 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host= *host, * provided for actual_clock in renesas_sdhi_clk_update(). */ clk_margin =3D new_clock >> 10; - for (clk =3D 0x80000080; new_clock + clk_margin >=3D (clock << 1); clk >>= =3D 1) + for (clk =3D host->pdata->clk_mask; new_clock + clk_margin >=3D (clock <<= 1); clk >>=3D 1) clock <<=3D 1; =20 /* 1/1 clock is option */ @@ -1136,6 +1136,7 @@ int renesas_sdhi_probe(struct platform_device *pdev, mmc_data->dma_rx_offset =3D of_data->dma_rx_offset; mmc_data->max_blk_count =3D of_data->max_blk_count; mmc_data->max_segs =3D of_data->max_segs; + mmc_data->clk_mask =3D of_data->clk_mask; dma_priv->dma_buswidth =3D of_data->dma_buswidth; host->bus_shift =3D of_data->bus_shift; /* Fallback for old DTs */ @@ -1178,6 +1179,9 @@ int renesas_sdhi_probe(struct platform_device *pdev, if (mmd) *mmc_data =3D *mmd; =20 + if (!mmc_data->clk_mask) + mmc_data->clk_mask =3D SDHI_CLK_MASK_DEFAULT; + dma_priv->filter =3D shdma_chan_filter; dma_priv->enable =3D renesas_sdhi_enable_dma; =20 diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index b3f4a5f8dec0..c6db0418de15 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -101,6 +101,7 @@ static const struct renesas_sdhi_of_data of_data_rza2 = =3D { /* DMAC can handle 32bit blk count but only 1 segment */ .max_blk_count =3D UINT_MAX / TMIO_MAX_BLK_SIZE, .max_segs =3D 1, + .clk_mask =3D SDHI_CLK_MASK_DEFAULT, }; =20 static const struct renesas_sdhi_of_data of_data_rcar_gen3 =3D { @@ -118,6 +119,7 @@ static const struct renesas_sdhi_of_data of_data_rcar_g= en3 =3D { .max_blk_count =3D UINT_MAX / TMIO_MAX_BLK_SIZE, .max_segs =3D 1, .sdhi_flags =3D SDHI_FLAG_NEED_CLKH_FALLBACK, + .clk_mask =3D SDHI_CLK_MASK_DEFAULT, }; =20 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback= =3D { @@ -134,6 +136,7 @@ static const struct renesas_sdhi_of_data of_data_rcar_g= en3_no_sdh_fallback =3D { /* DMAC can handle 32bit blk count but only 1 segment */ .max_blk_count =3D UINT_MAX / TMIO_MAX_BLK_SIZE, .max_segs =3D 1, + .clk_mask =3D SDHI_CLK_MASK_DEFAULT, }; =20 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] =3D { diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/re= nesas_sdhi_sys_dmac.c index 7ae488e5c1e0..fcd2edfa69db 100644 --- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c @@ -28,6 +28,7 @@ =20 static const struct renesas_sdhi_of_data of_default_cfg =3D { .tmio_flags =3D TMIO_MMC_HAS_IDLE_WAIT, + .clk_mask =3D SDHI_CLK_MASK_DEFAULT, }; =20 static const struct renesas_sdhi_of_data of_rz_compatible =3D { @@ -36,6 +37,7 @@ static const struct renesas_sdhi_of_data of_rz_compatible= =3D { .tmio_ocr_mask =3D MMC_VDD_32_33, .capabilities =3D MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_WAIT_WHILE_BUSY, + .clk_mask =3D SDHI_CLK_MASK_DEFAULT, }; =20 static const struct renesas_sdhi_of_data of_rcar_gen1_compatible =3D { @@ -43,6 +45,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen1_com= patible =3D { .capabilities =3D MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_WAIT_WHILE_BUSY, .capabilities2 =3D MMC_CAP2_NO_WRITE_PROTECT, + .clk_mask =3D SDHI_CLK_MASK_DEFAULT, }; =20 /* Definitions for sampling clocks */ @@ -70,6 +73,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_com= patible =3D { .taps =3D rcar_gen2_scc_taps, .taps_num =3D ARRAY_SIZE(rcar_gen2_scc_taps), .max_blk_count =3D UINT_MAX / TMIO_MAX_BLK_SIZE, + .clk_mask =3D SDHI_CLK_MASK_DEFAULT, }; =20 static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] =3D { diff --git a/include/linux/platform_data/tmio.h b/include/linux/platform_da= ta/tmio.h index 426291713b83..76056d49f5e0 100644 --- a/include/linux/platform_data/tmio.h +++ b/include/linux/platform_data/tmio.h @@ -61,5 +61,6 @@ struct tmio_mmc_data { dma_addr_t dma_rx_offset; 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Thu, 23 Jul 2026 08:10:30 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v22 04/13] mmc: renesas_sdhi: Add max_divider field to support SoC-specific clock ranges Date: Thu, 23 Jul 2026 16:10:08 +0100 Message-ID: <20260723151024.318918-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> References: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G3L supports a wider clock divider range than the hardcoded 512 used by existing SoCs. Add a max_divider field to renesas_sdhi_of_data and tmio_mmc_data, and use it in renesas_sdhi_clk_enable(), renesas_sdhi_clk_update(), and renesas_sdhi_set_clock() instead of the fixed value. Default to SDHI_MAX_DIVIDER_DEFAULT (512) at probe time when platform data doesn't set it, and populate all existing internal/ sys DMAC of_data tables with this default to keep current SoCs unaffected. This paves the way for RZ/G3L's extended divider support. Signed-off-by: Biju Das --- v21->v22: * Updated comit description. v20->v21: * No change. v19->v20: * Replaced the check mmd->max_divider with mmc_data->max_divider and moved the code after assignment of variable mmd, this ensures assigning the default values for non-DT platforms and DT platforms with no device data. v18->v19: * Fixed max-divider setting for non-DT platforms. * Replaced the magic number '9' with ilog2 function in renesas_sdhi_clk_enable(). v18: * New patch. --- drivers/mmc/host/renesas_sdhi.h | 2 ++ drivers/mmc/host/renesas_sdhi_core.c | 12 ++++++++---- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 3 +++ drivers/mmc/host/renesas_sdhi_sys_dmac.c | 4 ++++ include/linux/platform_data/tmio.h | 1 + 5 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index f926a36f213c..438b2a7afe76 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -23,6 +23,7 @@ struct renesas_sdhi_scc { =20 #define SDHI_FLAG_NEED_CLKH_FALLBACK BIT(0) #define SDHI_CLK_MASK_DEFAULT 0x80000080 +#define SDHI_MAX_DIVIDER_DEFAULT 512 =20 struct renesas_sdhi_of_data { unsigned long tmio_flags; @@ -39,6 +40,7 @@ struct renesas_sdhi_of_data { unsigned short max_segs; unsigned long sdhi_flags; u64 clk_mask; + unsigned int max_divider; }; =20 #define SDHI_CALIB_TABLE_MAX 32 diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 604d886e483c..d893a263e770 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -117,7 +117,7 @@ static int renesas_sdhi_clk_enable(struct tmio_mmc_host= *host) * Minimum frequency is the minimum input clock frequency * divided by our maximum divider. */ - mmc->f_min =3D max(clk_round_rate(priv->clk, 1) / 512, 1L); + mmc->f_min =3D max(clk_round_rate(priv->clk, 1) / host->pdata->max_divide= r, 1L); =20 /* enable 16bit data access on SDBUF as default */ renesas_sdhi_sdbuf_width(host, 16); @@ -156,7 +156,7 @@ static unsigned int renesas_sdhi_clk_update(struct tmio= _mmc_host *host, /* * We want the bus clock to be as close as possible to, but no * greater than, new_clock. As we can divide by 1 << i for - * any i in [0, 9] we want the input clock to be as close as + * any i in [0, {9,11}] we want the input clock to be as close as * possible, but no greater than, new_clock << i. * * Add an upper limit of 1/1024 rate higher to the clock rate to fix @@ -165,7 +165,7 @@ static unsigned int renesas_sdhi_clk_update(struct tmio= _mmc_host *host, * for 533.333333 MHz will selects a slower 400 MHz due to rounding * error (533333333 Hz / 4 * 4 =3D 533333332 Hz < 533333333 Hz)). */ - for (i =3D min(9, ilog2(UINT_MAX / new_clock)); i >=3D 0; i--) { + for (i =3D min(ilog2(host->pdata->max_divider), ilog2(UINT_MAX / new_cloc= k)); i >=3D 0; i--) { freq =3D clk_round_rate(ref_clk, new_clock << i); new_upper_limit =3D (new_clock << i) + ((new_clock << i) >> 10); if (freq > new_upper_limit) { @@ -205,7 +205,7 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host= *host, } =20 host->mmc->actual_clock =3D renesas_sdhi_clk_update(host, new_clock); - clock =3D host->mmc->actual_clock / 512; + clock =3D host->mmc->actual_clock / host->pdata->max_divider; =20 /* * Add a margin of 1/1024 rate higher to the clock rate in order @@ -1137,6 +1137,7 @@ int renesas_sdhi_probe(struct platform_device *pdev, mmc_data->max_blk_count =3D of_data->max_blk_count; mmc_data->max_segs =3D of_data->max_segs; mmc_data->clk_mask =3D of_data->clk_mask; + mmc_data->max_divider =3D of_data->max_divider; dma_priv->dma_buswidth =3D of_data->dma_buswidth; host->bus_shift =3D of_data->bus_shift; /* Fallback for old DTs */ @@ -1182,6 +1183,9 @@ int renesas_sdhi_probe(struct platform_device *pdev, if (!mmc_data->clk_mask) mmc_data->clk_mask =3D SDHI_CLK_MASK_DEFAULT; =20 + if (!mmc_data->max_divider) + mmc_data->max_divider =3D SDHI_MAX_DIVIDER_DEFAULT; + dma_priv->filter =3D shdma_chan_filter; dma_priv->enable =3D renesas_sdhi_enable_dma; =20 diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index c6db0418de15..2bf354331b2d 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -102,6 +102,7 @@ static const struct renesas_sdhi_of_data of_data_rza2 = =3D { .max_blk_count =3D UINT_MAX / TMIO_MAX_BLK_SIZE, .max_segs =3D 1, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, + .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, }; =20 static const struct renesas_sdhi_of_data of_data_rcar_gen3 =3D { @@ -120,6 +121,7 @@ static const struct renesas_sdhi_of_data of_data_rcar_g= en3 =3D { .max_segs =3D 1, .sdhi_flags =3D SDHI_FLAG_NEED_CLKH_FALLBACK, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, + .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, }; =20 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback= =3D { @@ -137,6 +139,7 @@ static const struct renesas_sdhi_of_data of_data_rcar_g= en3_no_sdh_fallback =3D { .max_blk_count =3D UINT_MAX / TMIO_MAX_BLK_SIZE, .max_segs =3D 1, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, + .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, }; =20 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] =3D { diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/re= nesas_sdhi_sys_dmac.c index fcd2edfa69db..bb66ff7de065 100644 --- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c @@ -29,6 +29,7 @@ static const struct renesas_sdhi_of_data of_default_cfg =3D { .tmio_flags =3D TMIO_MMC_HAS_IDLE_WAIT, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, + .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, }; =20 static const struct renesas_sdhi_of_data of_rz_compatible =3D { @@ -38,6 +39,7 @@ static const struct renesas_sdhi_of_data of_rz_compatible= =3D { .capabilities =3D MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_WAIT_WHILE_BUSY, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, + .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, }; =20 static const struct renesas_sdhi_of_data of_rcar_gen1_compatible =3D { @@ -46,6 +48,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen1_com= patible =3D { MMC_CAP_WAIT_WHILE_BUSY, .capabilities2 =3D MMC_CAP2_NO_WRITE_PROTECT, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, + .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, }; =20 /* Definitions for sampling clocks */ @@ -74,6 +77,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_com= patible =3D { .taps_num =3D ARRAY_SIZE(rcar_gen2_scc_taps), .max_blk_count =3D UINT_MAX / TMIO_MAX_BLK_SIZE, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, + .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, }; =20 static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] =3D { diff --git a/include/linux/platform_data/tmio.h b/include/linux/platform_da= ta/tmio.h index 76056d49f5e0..27ea21c00419 100644 --- a/include/linux/platform_data/tmio.h +++ b/include/linux/platform_data/tmio.h @@ -62,5 +62,6 @@ struct tmio_mmc_data { unsigned int max_blk_count; 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Thu, 23 Jul 2026 08:10:31 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v22 05/13] mmc: renesas_sdhi: Make clock divider mask configurable Date: Thu, 23 Jul 2026 16:10:09 +0100 Message-ID: <20260723151024.318918-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> References: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add a clk_div_mask field to renesas_sdhi_of_data and tmio_mmc_data so each SoC can specify its own divider mask instead of the hardcoded CLK_CTL_DIV_MASK used in renesas_sdhi_set_clock(). Default to GENMASK(7, 0) at probe time when unset, and populate all existing internal/sys DMAC of_data tables with this value to keep current SoCs unaffected. This lets RZ/G3L, which has a wider divider field, reuse the same clock-setting code. Signed-off-by: Biju Das --- v21->v22: * Updated commit description. * Added clk_div_mask to of_default_cfg and of_rcar_gen2_compatible. v21: * New patch. --- drivers/mmc/host/renesas_sdhi.h | 1 + drivers/mmc/host/renesas_sdhi_core.c | 5 ++++- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 3 +++ drivers/mmc/host/renesas_sdhi_sys_dmac.c | 4 ++++ include/linux/platform_data/tmio.h | 1 + 5 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index 438b2a7afe76..db147af9068c 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -41,6 +41,7 @@ struct renesas_sdhi_of_data { unsigned long sdhi_flags; u64 clk_mask; unsigned int max_divider; + u16 clk_div_mask; }; =20 #define SDHI_CALIB_TABLE_MAX 32 diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index d893a263e770..44d9f5da0b4b 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -224,7 +224,7 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host= *host, clk &=3D ~0xff; } =20 - clock =3D clk & CLK_CTL_DIV_MASK; + clock =3D clk & host->pdata->clk_div_mask; if (clock !=3D CLK_CTL_DIV_MASK) host->mmc->actual_clock /=3D (1 << (ffs(clock) + 1)); =20 @@ -1186,6 +1186,9 @@ int renesas_sdhi_probe(struct platform_device *pdev, if (!mmc_data->max_divider) mmc_data->max_divider =3D SDHI_MAX_DIVIDER_DEFAULT; =20 + if (!mmc_data->clk_div_mask) + mmc_data->clk_div_mask =3D GENMASK(7, 0); + dma_priv->filter =3D shdma_chan_filter; dma_priv->enable =3D renesas_sdhi_enable_dma; =20 diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index 2bf354331b2d..9bf7aa9bd867 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -103,6 +103,7 @@ static const struct renesas_sdhi_of_data of_data_rza2 = =3D { .max_segs =3D 1, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, + .clk_div_mask =3D GENMASK(7, 0), }; =20 static const struct renesas_sdhi_of_data of_data_rcar_gen3 =3D { @@ -122,6 +123,7 @@ static const struct renesas_sdhi_of_data of_data_rcar_g= en3 =3D { .sdhi_flags =3D SDHI_FLAG_NEED_CLKH_FALLBACK, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, + .clk_div_mask =3D GENMASK(7, 0), }; =20 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback= =3D { @@ -140,6 +142,7 @@ static const struct renesas_sdhi_of_data of_data_rcar_g= en3_no_sdh_fallback =3D { .max_segs =3D 1, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, + .clk_div_mask =3D GENMASK(7, 0), }; =20 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] =3D { diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/re= nesas_sdhi_sys_dmac.c index bb66ff7de065..90e3bc6b954f 100644 --- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c @@ -30,6 +30,7 @@ static const struct renesas_sdhi_of_data of_default_cfg = =3D { .tmio_flags =3D TMIO_MMC_HAS_IDLE_WAIT, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, + .clk_div_mask =3D GENMASK(7, 0), }; =20 static const struct renesas_sdhi_of_data of_rz_compatible =3D { @@ -40,6 +41,7 @@ static const struct renesas_sdhi_of_data of_rz_compatible= =3D { MMC_CAP_WAIT_WHILE_BUSY, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, + .clk_div_mask =3D GENMASK(7, 0), }; =20 static const struct renesas_sdhi_of_data of_rcar_gen1_compatible =3D { @@ -49,6 +51,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen1_com= patible =3D { .capabilities2 =3D MMC_CAP2_NO_WRITE_PROTECT, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, + .clk_div_mask =3D GENMASK(7, 0), }; =20 /* Definitions for sampling clocks */ @@ -78,6 +81,7 @@ static const struct renesas_sdhi_of_data of_rcar_gen2_com= patible =3D { .max_blk_count =3D UINT_MAX / TMIO_MAX_BLK_SIZE, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, + .clk_div_mask =3D GENMASK(7, 0), }; =20 static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] =3D { diff --git a/include/linux/platform_data/tmio.h b/include/linux/platform_da= ta/tmio.h index 27ea21c00419..f684f4087a8f 100644 --- a/include/linux/platform_data/tmio.h +++ b/include/linux/platform_data/tmio.h @@ -63,5 +63,6 @@ struct tmio_mmc_data { unsigned short max_segs; u64 clk_mask; unsigned int max_divider; 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Thu, 23 Jul 2026 08:10:32 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v22 06/13] mmc: renesas_sdhi: Add tuning delay support for RZ/G2L Date: Thu, 23 Jul 2026 16:10:10 +0100 Message-ID: <20260723151024.318918-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> References: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G2L and later SoCs need a hardware adjustment delay written to SCC_TMPPORT2 on signal-voltage switch during tuning: 0x1 for 1.8V, 0x0 for 3.3V. Add a TMIO_MMC_TUNING_DELAY flag and renesas_sdhi_set_hw_adjustment_delay(), called from renesas_sdhi_start_signal_voltage_switch() after the regulator is set, and reset SCC_TMPPORT2 to 0 at the start of renesas_sdhi_execute_tuning() when the flag is set and tap_num =3D=3D 8. Add a dedicated of_data_rz_g2l descriptor with this flag and switch of_rzg2l_compatible to use it instead of the generic R-Car Gen3 descriptor. Signed-off-by: Biju Das --- v21->v22: * Updated commit description. * Added a renesas_sdhi_set_hw_adjustment_delay() call to renesas_sdhi_init_tuning(). v20->v21: * Added clk_div_mask to RZ/G2L of_data. v19->v20: * No change. v18->v19: * No change. v18: * New patch. --- drivers/mmc/host/renesas_sdhi_core.c | 88 ++++++++++++------- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 22 ++++- include/linux/platform_data/tmio.h | 3 + 3 files changed, 78 insertions(+), 35 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 44d9f5da0b4b..9c6a3c5fbc8d 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -256,40 +256,6 @@ static int renesas_sdhi_card_busy(struct mmc_host *mmc) TMIO_STAT_DAT0); } =20 -static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, - struct mmc_ios *ios) -{ - struct tmio_mmc_host *host =3D mmc_priv(mmc); - struct renesas_sdhi *priv =3D host_to_priv(host); - struct pinctrl_state *pin_state; - int ret; - - switch (ios->signal_voltage) { - case MMC_SIGNAL_VOLTAGE_330: - pin_state =3D priv->pins_default; - break; - case MMC_SIGNAL_VOLTAGE_180: - pin_state =3D priv->pins_uhs; - break; - default: - return -EINVAL; - } - - /* - * If anything is missing, assume signal voltage is fixed at - * 3.3V and succeed/fail accordingly. - */ - if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) - return ios->signal_voltage =3D=3D - MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; - - ret =3D mmc_regulator_set_vqmmc(host->mmc, ios); - if (ret < 0) - return ret; - - return pinctrl_select_state(priv->pinctrl, pin_state); -} - /* SCC registers */ #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 @@ -350,6 +316,55 @@ static inline void sd_scc_write32(struct tmio_mmc_host= *host, writel(val, priv->scc_ctl + (addr << host->bus_shift)); } =20 +static void renesas_sdhi_set_hw_adjustment_delay(struct tmio_mmc_host *hos= t) +{ + struct renesas_sdhi *priv =3D host_to_priv(host); + + if (!(host->pdata->flags & TMIO_MMC_TUNING_DELAY)) + return; + + if (host->mmc->ios.signal_voltage =3D=3D MMC_SIGNAL_VOLTAGE_330) + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0x0); + else + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0x1); +} + +static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct tmio_mmc_host *host =3D mmc_priv(mmc); + struct renesas_sdhi *priv =3D host_to_priv(host); + struct pinctrl_state *pin_state; + int ret; + + switch (ios->signal_voltage) { + case MMC_SIGNAL_VOLTAGE_330: + pin_state =3D priv->pins_default; + break; + case MMC_SIGNAL_VOLTAGE_180: + pin_state =3D priv->pins_uhs; + break; + default: + return -EINVAL; + } + + /* + * If anything is missing, assume signal voltage is fixed at + * 3.3V and succeed/fail accordingly. + */ + if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) + return ios->signal_voltage =3D=3D + MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; + + ret =3D mmc_regulator_set_vqmmc(host->mmc, ios); + if (ret < 0) + return ret; + + renesas_sdhi_set_hw_adjustment_delay(host); + + return pinctrl_select_state(priv->pinctrl, pin_state); +} + static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) { struct renesas_sdhi *priv; @@ -377,6 +392,8 @@ static unsigned int renesas_sdhi_init_tuning(struct tmi= o_mmc_host *host) =20 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); =20 + renesas_sdhi_set_hw_adjustment_delay(host); + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); =20 @@ -709,6 +726,9 @@ static int renesas_sdhi_execute_tuning(struct mmc_host = *mmc, u32 opcode) if (!priv->tap_num) return 0; /* Tuning is not supported */ =20 + if ((host->pdata->flags & TMIO_MMC_TUNING_DELAY) && priv->tap_num =3D=3D = 8) + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0); + if (priv->tap_num * 2 >=3D sizeof(priv->taps) * BITS_PER_BYTE) { dev_err(&host->pdev->dev, "Too many taps, please update 'taps' in tmio_mmc_host!\n"); diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index 9bf7aa9bd867..1799c6106102 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -145,6 +145,26 @@ static const struct renesas_sdhi_of_data of_data_rcar_= gen3_no_sdh_fallback =3D { .clk_div_mask =3D GENMASK(7, 0), }; =20 +static const struct renesas_sdhi_of_data of_data_rz_g2l =3D { + .tmio_flags =3D TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | + TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 | + TMIO_MMC_64BIT_DATA_PORT | TMIO_MMC_TUNING_DELAY, + .capabilities =3D MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | + MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, + .capabilities2 =3D MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, + .bus_shift =3D 2, + .scc_offset =3D 0x1000, + .taps =3D rcar_gen3_scc_taps, + .taps_num =3D ARRAY_SIZE(rcar_gen3_scc_taps), + /* DMAC can handle 32bit blk count but only 1 segment */ + .max_blk_count =3D UINT_MAX / TMIO_MAX_BLK_SIZE, + .max_segs =3D 1, + .sdhi_flags =3D SDHI_FLAG_NEED_CLKH_FALLBACK, + .clk_mask =3D SDHI_CLK_MASK_DEFAULT, + .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, + .clk_div_mask =3D GENMASK(7, 0), +}; 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charset="utf-8" From: Biju Das RZ/G3L has a fixed internal /2 clock divider active in all bus timing modes except HS400. Add a TMIO_MMC_INTERNAL_DIVIDER flag to mark controllers with this divider. Add renesas_sdhi_clk_get_rate() to fold the /2 division into the reported clock rate when the flag is set, and use it in renesas_sdhi_clk_update() in place of clk_get_rate(). Also adjust clkh_shift when computing the clkh rate for these controllers. No existing platform sets this flag, so this is infrastructure only, with no functional change for current SoCs. Signed-off-by: Biju Das --- v21->v22: * Updated commit description. * Added renesas_sdhi_is_internal_divider_enabled() and renesas_sdhi_clk_get_rate() to simplify the clock rate logic. v20->v21: * No change. v19->v20: * No change. v18->v19: * Updated commit description. * Dropped divider variable from struct renesas_sdhi. * Updated renesas_sdhi_clk_update() to return rate for HS400mode and nonHS400mode(uses 1/2 internal divider). v18: * New patch using flag. --- drivers/mmc/host/renesas_sdhi_core.c | 31 +++++++++++++++++++++++++--- include/linux/platform_data/tmio.h | 3 +++ 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 9c6a3c5fbc8d..638bbc990096 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -125,6 +125,27 @@ static int renesas_sdhi_clk_enable(struct tmio_mmc_hos= t *host) return 0; } =20 +static bool renesas_sdhi_is_internal_divider_enabled(struct tmio_mmc_host = *host) +{ + bool enable =3D false; + + if (host->pdata->flags & TMIO_MMC_INTERNAL_DIVIDER) + enable =3D true; + + return enable; +} + +static unsigned int renesas_sdhi_clk_get_rate(struct tmio_mmc_host *host, + struct clk *clk) +{ + unsigned int freq =3D clk_get_rate(clk); + + if (renesas_sdhi_is_internal_divider_enabled(host)) + freq /=3D 2; + + return freq; +} + static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, unsigned int wanted_clock) { @@ -141,7 +162,7 @@ static unsigned int renesas_sdhi_clk_update(struct tmio= _mmc_host *host, * clock during tuning, so we don't change the external clock setup. */ if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mm= c)) - return clk_get_rate(priv->clk); + return renesas_sdhi_clk_get_rate(host, priv->clk); =20 if (priv->clkh) { /* HS400 with 4TAP needs different clock settings */ @@ -184,10 +205,14 @@ static unsigned int renesas_sdhi_clk_update(struct tm= io_mmc_host *host, =20 clk_set_rate(ref_clk, best_freq); =20 - if (priv->clkh) + if (priv->clkh) { + if (host->pdata->flags & TMIO_MMC_INTERNAL_DIVIDER) + clkh_shift =3D 1; + clk_set_rate(priv->clk, best_freq >> clkh_shift); + } =20 - return clk_get_rate(priv->clk); + return renesas_sdhi_clk_get_rate(host, priv->clk); } =20 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, diff --git a/include/linux/platform_data/tmio.h b/include/linux/platform_da= ta/tmio.h index 77d3dc91c828..09b3411a59c9 100644 --- a/include/linux/platform_data/tmio.h +++ b/include/linux/platform_data/tmio.h @@ -53,6 +53,9 @@ /* Some controllers have tuning delay */ #define TMIO_MMC_TUNING_DELAY BIT(13) =20 +/* Some controllers have internal divider */ +#define TMIO_MMC_INTERNAL_DIVIDER BIT(14) + struct tmio_mmc_data { void *chan_priv_tx; void *chan_priv_rx; --=20 2.43.0 From nobody Fri Jul 24 05:23:06 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A80894570D9 for ; Thu, 23 Jul 2026 15:10:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" From: Biju Das The RZ/G3L SoC has axis/axim resets compared to other SoCs. Add two optional reset controls, rstc_axis and rstc_axim, to the renesas_sdhi struct. Both are acquired at probe time using devm_reset_control_get_optional_exclusive_deasserted() with the "axis" and "axim" reset names respectively. Include them alongside the existing rstc in bulk reset/assert/deassert operations: triggered together in renesas_sdhi_reset(), and managed via reset_control_bulk_assert/deassert() in the suspend and resume paths, replacing the previous single-control calls. Being optional, these resets are a no-op on platforms that do not provide them, so existing behaviour is preserved. Signed-off-by: Biju Das --- v21->v22: * No change. v20->v21: * No change. v19->v20: * Fixed the ordering of resets in suspend/resume paths. V18->v19: * No change. v17->v18: * Fixed ordering of reset in renesas_sdhi_reset(). v1->v17: * No change. --- drivers/mmc/host/renesas_sdhi.h | 2 ++ drivers/mmc/host/renesas_sdhi_core.c | 26 +++++++++++++++++++++++--- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index db147af9068c..a085a4cb2e38 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -101,6 +101,8 @@ struct renesas_sdhi { unsigned int tap_set; =20 struct reset_control *rstc; + struct reset_control *rstc_axis; + struct reset_control *rstc_axim; struct tmio_mmc_host *host; struct regulator_dev *rdev; }; diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 638bbc990096..6d8f32e2fc38 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -641,6 +641,8 @@ static void renesas_sdhi_reset(struct tmio_mmc_host *ho= st, bool preserve) sd_status =3D sd_ctrl_read32(host, CTL_SD_STATUS); =20 reset_control_reset(priv->rstc); + reset_control_reset(priv->rstc_axim); + reset_control_reset(priv->rstc_axis); /* Unknown why but without polling reset status, it will hang */ read_poll_timeout(reset_control_status, ret, ret =3D=3D 0, 1, 100, false, priv->rstc); @@ -1155,6 +1157,14 @@ int renesas_sdhi_probe(struct platform_device *pdev, if (IS_ERR(priv->rstc)) return PTR_ERR(priv->rstc); =20 + priv->rstc_axim =3D devm_reset_control_get_optional_exclusive_deasserted(= &pdev->dev, "axim"); + if (IS_ERR(priv->rstc_axim)) + return PTR_ERR(priv->rstc_axim); + + priv->rstc_axis =3D devm_reset_control_get_optional_exclusive_deasserted(= &pdev->dev, "axis"); + if (IS_ERR(priv->rstc_axis)) + return PTR_ERR(priv->rstc_axis); + priv->pinctrl =3D devm_pinctrl_get(&pdev->dev); if (!IS_ERR(priv->pinctrl)) { priv->pins_default =3D pinctrl_lookup_state(priv->pinctrl, @@ -1384,13 +1394,18 @@ int renesas_sdhi_suspend(struct device *dev) { struct tmio_mmc_host *host =3D dev_get_drvdata(dev); struct renesas_sdhi *priv =3D host_to_priv(host); + struct reset_control_bulk_data resets[] =3D { + { .rstc =3D priv->rstc_axis }, + { .rstc =3D priv->rstc_axim }, + { .rstc =3D priv->rstc }, + }; int ret; =20 ret =3D pm_runtime_force_suspend(dev); if (ret) return ret; =20 - ret =3D reset_control_assert(priv->rstc); + ret =3D reset_control_bulk_assert(ARRAY_SIZE(resets), resets); if (ret) pm_runtime_force_resume(dev); =20 @@ -1402,15 +1417,20 @@ int renesas_sdhi_resume(struct device *dev) { struct tmio_mmc_host *host =3D dev_get_drvdata(dev); struct renesas_sdhi *priv =3D host_to_priv(host); + struct reset_control_bulk_data resets[] =3D { + { .rstc =3D priv->rstc_axis }, + { .rstc =3D priv->rstc_axim }, + { .rstc =3D priv->rstc }, + }; int ret; =20 - ret =3D reset_control_deassert(priv->rstc); + ret =3D reset_control_bulk_deassert(ARRAY_SIZE(resets), resets); if (ret) return ret; =20 ret =3D pm_runtime_force_resume(dev); if (ret) - reset_control_assert(priv->rstc); + reset_control_bulk_assert(ARRAY_SIZE(resets), resets); =20 return ret; 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Thu, 23 Jul 2026 08:10:34 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v22 09/13] mmc: renesas_sdhi: Add RZ/G3L SDHI support Date: Thu, 23 Jul 2026 16:10:13 +0100 Message-ID: <20260723151024.318918-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> References: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Biju Das RZ/G3L (r9a08g046) has an SDHI controller that differs from existing platforms in clock divider width, a second HW adjustment register, and an extra tuning register. Add TMIO_MMC_HWADJ to mark controllers with a second HWADJ2 register (offset 0x010), programmed by renesas_sdhi_set_hw_adjustment_delay() alongside TMPPORT2 (0x3FFF at 3.3V, 0xFF at 1.8V). Clear the new HWADJ4 register (0x022) at tuning start when TMIO_MMC_INTERNAL_DIVIDER is set. Update renesas_sdhi_set_clock() to write the clock control register with a 32-bit access when max_divider isn't the default, moving bits [9:8] of the clock value into bits [17:16] of the register =E2=80=94 needed to drive RZ/G3L's wider 11-bit divider field via the max_divider/ clk_div_mask support added earlier in this series. Add SDHI_VER_RZ_G3L_SDMMC (0xce10) and handle it in renesas_sdhi_sdbuf_width(). Add of_data_rzg3l with RZ/G3L's wider clk_mask, an 11-bit max_divider of 2048, a dedicated tap table, and the relevant flags including TMIO_MMC_INTERNAL_DIVIDER and TMIO_MMC_HWADJ. Wire it up via of_rzg3l_compatible (fixed_addr_mode quirk) and register the "renesas,sdhi-r9a08g046" compatible string. Signed-off-by: Biju Das --- v21->v22: * Updated commit description. * Added `clock &=3D ~GENMASK(9, 8)` to clear the divider mask bits in the register value. v20->v21: * Added clk_div_mask to RZ/G3L of_data. * Restored actual_clk calculation in renesas_sdhi_set_clock(). v19->v20: * Added bitfield.h header file. * Reworked on renesas_sdhi_set_clock() to handle the 11-bit divider case and the 32-bit register write. v18->v19: * Update commit description. * Updated handling for clk divider. * Renamed TMIO_MMC_HWADJ2->TMIO_MMC_HWADJ to make it generic for hardware tuning delays * Dropped duplicate SH_MOBILE_SDHI_SCC_TMPPORT2 macro v18: * New patch. --- drivers/mmc/host/renesas_sdhi_core.c | 31 +++++++++++++-- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 38 +++++++++++++++++++ include/linux/platform_data/tmio.h | 3 ++ 3 files changed, 68 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 6d8f32e2fc38..be7720305d32 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -18,6 +18,7 @@ * */ =20 +#include #include #include #include @@ -59,6 +60,7 @@ #define SDHI_VER_GEN2_SDR104 0xcb0d #define SDHI_VER_GEN3_SD 0xcc10 #define SDHI_VER_GEN3_SDMMC 0xcd10 +#define SDHI_VER_RZ_G3L_SDMMC 0xce10 =20 #define SDHI_GEN3_MMC0_ADDR 0xee140000 =20 @@ -79,6 +81,7 @@ static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host= *host, int width) break; case SDHI_VER_GEN3_SD: case SDHI_VER_GEN3_SDMMC: + case SDHI_VER_RZ_G3L_SDMMC: if (width =3D=3D 64) val =3D HOST_MODE_GEN3_64BIT; else if (width =3D=3D 32) @@ -253,7 +256,17 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_hos= t *host, if (clock !=3D CLK_CTL_DIV_MASK) host->mmc->actual_clock /=3D (1 << (ffs(clock) + 1)); =20 - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock); + if (host->pdata->max_divider !=3D SDHI_MAX_DIVIDER_DEFAULT) { + u64 tmp; + + tmp =3D FIELD_GET(GENMASK(9, 8), clk); + clock |=3D FIELD_PREP(GENMASK(17, 16), tmp); + clock &=3D ~GENMASK(9, 8); + sd_ctrl_write32(host, CTL_SD_CARD_CLK_CTL, clock); + } else { + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock); + } + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) usleep_range(10000, 11000); =20 @@ -289,12 +302,14 @@ static int renesas_sdhi_card_busy(struct mmc_host *mm= c) #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C -#define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E +#define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E /* G3L: SDm_SCC_HS400MODE1 */ +#define RZG3L_SDHI_SCC_HWADJ2 0x010 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C +#define RZG3L_SDHI_SCC_HWADJ4 0x022 =20 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 @@ -344,14 +359,20 @@ static inline void sd_scc_write32(struct tmio_mmc_hos= t *host, static void renesas_sdhi_set_hw_adjustment_delay(struct tmio_mmc_host *hos= t) { struct renesas_sdhi *priv =3D host_to_priv(host); + bool hwadj2 =3D host->pdata->flags & TMIO_MMC_HWADJ; =20 if (!(host->pdata->flags & TMIO_MMC_TUNING_DELAY)) return; =20 - if (host->mmc->ios.signal_voltage =3D=3D MMC_SIGNAL_VOLTAGE_330) + if (host->mmc->ios.signal_voltage =3D=3D MMC_SIGNAL_VOLTAGE_330) { sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0x0); - else + if (hwadj2) + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HWADJ2, 0x3FFF); + } else { sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0x1); + if (hwadj2) + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HWADJ2, 0xFF); + } } =20 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, @@ -418,6 +439,8 @@ static unsigned int renesas_sdhi_init_tuning(struct tmi= o_mmc_host *host) sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); =20 renesas_sdhi_set_hw_adjustment_delay(host); + if (host->pdata->flags & TMIO_MMC_HWADJ) + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HWADJ4, 0x0); =20 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index 1799c6106102..893d9395e9d6 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -88,6 +88,13 @@ static struct renesas_sdhi_scc rcar_gen3_scc_taps[] =3D { }, }; =20 +static struct renesas_sdhi_scc rzg3l_scc_taps[] =3D { + { + .clk_rate =3D 0, + .tap =3D 0x00000300, + }, +}; + static const struct renesas_sdhi_of_data of_data_rza2 =3D { .tmio_flags =3D TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | TMIO_MMC_HAVE_CBSY, @@ -165,6 +172,27 @@ static const struct renesas_sdhi_of_data of_data_rz_g2= l =3D { .clk_div_mask =3D GENMASK(7, 0), }; =20 +static const struct renesas_sdhi_of_data of_data_rzg3l =3D { + .tmio_flags =3D TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | + TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 | + TMIO_MMC_64BIT_DATA_PORT | TMIO_MMC_TUNING_DELAY | + TMIO_MMC_INTERNAL_DIVIDER | TMIO_MMC_HWADJ, + .capabilities =3D MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | + MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, + .capabilities2 =3D MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, + .bus_shift =3D 2, + .scc_offset =3D 0x1000, + .taps =3D rzg3l_scc_taps, + .taps_num =3D ARRAY_SIZE(rzg3l_scc_taps), + /* DMAC can handle 32bit blk count but only 1 segment */ + .max_blk_count =3D UINT_MAX / TMIO_MAX_BLK_SIZE, + .max_segs =3D 1, + .sdhi_flags =3D SDHI_FLAG_NEED_CLKH_FALLBACK, + .clk_mask =3D 0x200000200, + .max_divider =3D 2048, + .clk_div_mask =3D GENMASK(9, 0), +}; + static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] =3D { { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, @@ -245,6 +273,10 @@ static const struct renesas_sdhi_quirks sdhi_quirks_rz= g2l =3D { .hs400_disabled =3D true, }; =20 +static const struct renesas_sdhi_quirks sdhi_quirks_rzg3l =3D { + .fixed_addr_mode =3D true, +}; + /* * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of n= ow. * So, we want to treat them equally and only have a match for ES1.2 to en= force @@ -304,6 +336,11 @@ static const struct renesas_sdhi_of_data_with_quirks o= f_rza2_compatible =3D { .quirks =3D &sdhi_quirks_fixed_addr, }; =20 +static const struct renesas_sdhi_of_data_with_quirks of_rzg3l_compatible = =3D { + .of_data =3D &of_data_rzg3l, + .quirks =3D &sdhi_quirks_rzg3l, +}; + static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] =3D= { { .compatible =3D "renesas,sdhi-r7s9210", .data =3D &of_rza2_compatible, = }, { .compatible =3D "renesas,sdhi-mmc-r8a77470", .data =3D &of_rcar_gen3_co= mpatible, }, @@ -317,6 +354,7 @@ static const struct of_device_id renesas_sdhi_internal_= dmac_of_match[] =3D { { .compatible =3D "renesas,sdhi-r8a77990", .data =3D &of_r8a77990_compati= ble, }, { .compatible =3D "renesas,sdhi-r8a77995", .data =3D &of_rcar_gen3_nohs40= 0_compatible, }, { .compatible =3D "renesas,sdhi-r8a779md", .data =3D &of_rcar_gen3_nohs40= 0_compatible, }, + { .compatible =3D "renesas,sdhi-r9a08g046", .data =3D &of_rzg3l_compatibl= e, }, { .compatible =3D "renesas,sdhi-r9a09g011", .data =3D &of_rzg2l_compatibl= e, }, { .compatible =3D "renesas,sdhi-r9a09g057", .data =3D &of_rzg2l_compatibl= e, }, { .compatible =3D "renesas,rzg2l-sdhi", .data =3D &of_rzg2l_compatible, }, diff --git a/include/linux/platform_data/tmio.h b/include/linux/platform_da= ta/tmio.h index 09b3411a59c9..99b05c8c840a 100644 --- a/include/linux/platform_data/tmio.h +++ b/include/linux/platform_data/tmio.h @@ -56,6 +56,9 @@ /* Some controllers have internal divider */ #define TMIO_MMC_INTERNAL_DIVIDER BIT(14) =20 +/* Some controllers have hw adjustment delay */ +#define TMIO_MMC_HWADJ BIT(15) + struct tmio_mmc_data { void *chan_priv_tx; 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Thu, 23 Jul 2026 08:10:35 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v22 10/13] mmc: renesas_sdhi: Save and restore IOVS across suspend/resume Date: Thu, 23 Jul 2026 16:10:14 +0100 Message-ID: <20260723151024.318918-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> References: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The SD_STATUS register, specifically the IOVS (I/O Voltage Switch) bit, is not automatically restored after a suspend/resume cycle, causing the regulator to report an incorrect voltage on resume. Fix this by caching the CTL_SD_STATUS register value in the renesas_sdhi private struct at suspend time and writing it back during resume. The save/restore is only performed when a regulator device (rdev) is present, as the IOVS bit is only relevant in that context. Signed-off-by: Biju Das --- v21->v22: * No change. v20->v21: * No change. v19->v20: * Updated resume() with scoped PM runtime call. v18->v19: * Updated suspend/resume with scoped runtime calls in suspend. v17->v18: * No change. v1->v17: * No change. --- drivers/mmc/host/renesas_sdhi.h | 2 ++ drivers/mmc/host/renesas_sdhi_core.c | 26 +++++++++++++++++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index a085a4cb2e38..e2c26917b884 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -105,6 +105,8 @@ struct renesas_sdhi { struct reset_control *rstc_axim; struct tmio_mmc_host *host; struct regulator_dev *rdev; + + u32 cache_sd_status; }; =20 #define host_to_priv(host) \ diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index be7720305d32..70ebe5902f6c 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -1424,6 +1424,15 @@ int renesas_sdhi_suspend(struct device *dev) }; int ret; =20 + if (priv->rdev) { + PM_RUNTIME_ACQUIRE_IF_ENABLED(dev, pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret < 0) + return ret; + + priv->cache_sd_status =3D sd_ctrl_read32(host, CTL_SD_STATUS); + } + ret =3D pm_runtime_force_suspend(dev); if (ret) return ret; @@ -1453,8 +1462,23 @@ int renesas_sdhi_resume(struct device *dev) =20 ret =3D pm_runtime_force_resume(dev); if (ret) - reset_control_bulk_assert(ARRAY_SIZE(resets), resets); + goto err_assert; + + if (priv->rdev) { + PM_RUNTIME_ACQUIRE_IF_ENABLED(dev, pm); + ret =3D PM_RUNTIME_ACQUIRE_ERR(&pm); + if (ret < 0) + goto err_pm; + + sd_ctrl_write32(host, CTL_SD_STATUS, priv->cache_sd_status); + } + + return 0; =20 +err_pm: + pm_runtime_force_suspend(dev); +err_assert: + reset_control_bulk_assert(ARRAY_SIZE(resets), resets); return ret; } EXPORT_SYMBOL_GPL(renesas_sdhi_resume); --=20 2.43.0 From nobody Fri Jul 24 05:23:06 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 636704D90BE for ; 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Thu, 23 Jul 2026 08:10:37 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:f073:32ed:a057:cd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85bb81dcsm15886823f8f.12.2026.07.23.08.10.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 08:10:37 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v22 11/13] mmc: renesas_sdhi: Make HS400 OSEL bit configurable per SoC Date: Thu, 23 Jul 2026 16:10:15 +0100 Message-ID: <20260723151024.318918-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> References: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G3L and R-Car both use SH_MOBILE_SDHI_SCC_TMPPORT2 but interpret its bitfields differently. R-Car uses BIT(4) (HS400OSEL) to control HS400 data output timing, while RZ/G3L uses the lower 16 bits for tuning delay and does not require the OSEL bit. Remove the hardcoded SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL constant and replace it with a per-platform osel_tmpout field in both renesas_sdhi_of_data and tmio_mmc_data. The field is propagated during probe and consumed in renesas_sdhi_hs400_complete() and renesas_sdhi_reset_hs400_mode() when setting or clearing the HS400EN bit in TMPPORT2. Set osel_tmpout =3D BIT(4) explicitly on of_data_rcar_gen3 and of_data_rcar_gen3_no_sdh_fallback; platforms that omit it (such as RZ/G2L and RZ/G3L) default to zero, leaving the OSEL bit untouched during HS400 mode transitions. Signed-off-by: Biju Das --- v21->v22: * No change. v20->v21: * No change. v19->v20: * No change. v18->v19: * No change. v18: * New patch. --- drivers/mmc/host/renesas_sdhi.h | 1 + drivers/mmc/host/renesas_sdhi_core.c | 6 +++--- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 2 ++ include/linux/platform_data/tmio.h | 1 + 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdh= i.h index e2c26917b884..7ed92229e937 100644 --- a/drivers/mmc/host/renesas_sdhi.h +++ b/drivers/mmc/host/renesas_sdhi.h @@ -41,6 +41,7 @@ struct renesas_sdhi_of_data { unsigned long sdhi_flags; u64 clk_mask; unsigned int max_divider; + u32 osel_tmpout; u16 clk_div_mask; }; =20 diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 70ebe5902f6c..0d38fbc53512 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -327,7 +327,6 @@ static int renesas_sdhi_card_busy(struct mmc_host *mmc) #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) =20 -#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) =20 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ @@ -475,7 +474,7 @@ static void renesas_sdhi_hs400_complete(struct mmc_host= *mmc) =20 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | - SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | + host->pdata->osel_tmpout) | sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); =20 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, @@ -616,7 +615,7 @@ static void renesas_sdhi_reset_hs400_mode(struct tmio_m= mc_host *host, =20 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | - SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & + host->pdata->osel_tmpout) & sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); =20 if (sdhi_has_quirk(priv, hs400_calib_table) || sdhi_has_quirk(priv, hs400= _bad_taps)) @@ -1216,6 +1215,7 @@ int renesas_sdhi_probe(struct platform_device *pdev, mmc_data->max_segs =3D of_data->max_segs; mmc_data->clk_mask =3D of_data->clk_mask; mmc_data->max_divider =3D of_data->max_divider; + mmc_data->osel_tmpout =3D of_data->osel_tmpout; dma_priv->dma_buswidth =3D of_data->dma_buswidth; host->bus_shift =3D of_data->bus_shift; /* Fallback for old DTs */ diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index 893d9395e9d6..b1146dca94ca 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -130,6 +130,7 @@ static const struct renesas_sdhi_of_data of_data_rcar_g= en3 =3D { .sdhi_flags =3D SDHI_FLAG_NEED_CLKH_FALLBACK, .clk_mask =3D SDHI_CLK_MASK_DEFAULT, .max_divider =3D SDHI_MAX_DIVIDER_DEFAULT, + .osel_tmpout =3D BIT(4), .clk_div_mask =3D GENMASK(7, 0), }; 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Thu, 23 Jul 2026 08:10:38 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a702:d301:f073:32ed:a057:cd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85bb81dcsm15886823f8f.12.2026.07.23.08.10.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 08:10:38 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v22 12/13] mmc: renesas_sdhi: Add RZ/G3L HS400 support Date: Thu, 23 Jul 2026 16:10:16 +0100 Message-ID: <20260723151024.318918-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> References: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add HS400 support for the RZ/G3L SoC. RZ/G3L needs a second HS400 enable register, SDm_SCC_HS400MODE2 (offset 0x020), alongside the existing TMPPORT2 path. Add a TMIO_MMC_HS400MODE2 flag (bit 16) for controllers that need it. renesas_sdhi_hs400_complete() now also sets HS400EN2 in HS400MODE2 when the flag is set, and renesas_sdhi_reset_hs400_mode() clears it on exit. Add renesas_sdhi_set_tmpport() to mask off only the lower 16 bits (TMPOUT) of TMPPORT2 when writing it, preserving the upper bits on controllers with HS400MODE2, instead of the previous unconditional zero write. RZ/G3L HS400 supports only one divider value, so renesas_sdhi_set_clock() now forces the clock value to 0 before masking when HS400MODE2 is set and the internal divider isn't currently enabled, rejecting any other divider. This also completes renesas_sdhi_is_internal_divider_enabled() from earlier in the series, which now additionally checks that the current timing mode is not MMC_TIMING_MMC_HS400 before reporting the internal divider as enabled. Enable TMIO_MMC_HS400MODE2 in of_data_rzg3l to complete RZ/G3L HS400 support. Signed-off-by: Biju Das --- v21->v22: * Updated commit description * Added a renesas_sdhi_set_tmpport() helper to set delay values. * Added a check in renesas_sdhi_is_internal_divider_enabled() to return disabled status when in HS400 mode. v20->v21: * Updated renesas_sdhi_set_clock() for RZ/G3L HS400 clock handling as it supports only single clk divider value and other values are prohibited. * Updated commit description. v19->v20: * No change. v18->v19: * Updated commit description. * Fixed extra space in HS400MODE2 comment block. * Updated the comment HS400mode2->HS400MODE2. * Dropped the updation of clk handling as it is taken care in previous patches. v18: * New patch. --- drivers/mmc/host/renesas_sdhi_core.c | 42 +++++++++++++++++-- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 3 +- include/linux/platform_data/tmio.h | 3 ++ 3 files changed, 43 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 0d38fbc53512..541321e43a13 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -132,7 +132,8 @@ static bool renesas_sdhi_is_internal_divider_enabled(st= ruct tmio_mmc_host *host) { bool enable =3D false; =20 - if (host->pdata->flags & TMIO_MMC_INTERNAL_DIVIDER) + if ((host->pdata->flags & TMIO_MMC_INTERNAL_DIVIDER) && + host->mmc->ios.timing !=3D MMC_TIMING_MMC_HS400) enable =3D true; =20 return enable; @@ -252,6 +253,14 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_hos= t *host, clk &=3D ~0xff; } =20 + /* + * RZ/G3L SoC HS400 mode has only 1 divider value. + * Other divider values are prohibited + */ + if ((host->pdata->flags & TMIO_MMC_HS400MODE2) && + !renesas_sdhi_is_internal_divider_enabled(host)) + clk =3D 0; + clock =3D clk & host->pdata->clk_div_mask; if (clock !=3D CLK_CTL_DIV_MASK) host->mmc->actual_clock /=3D (1 << (ffs(clock) + 1)); @@ -309,6 +318,7 @@ static int renesas_sdhi_card_busy(struct mmc_host *mmc) #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C +#define RZG3L_SDHI_SCC_HS400MODE2 0x020 #define RZG3L_SDHI_SCC_HWADJ4 0x022 =20 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) @@ -341,6 +351,7 @@ static int renesas_sdhi_card_busy(struct mmc_host *mmc) #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) +#define RZG3L_SDHI_SCC_HS400MODE2_HS400EN2 BIT(0) =20 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, struct renesas_sdhi *priv, int addr) @@ -355,6 +366,22 @@ static inline void sd_scc_write32(struct tmio_mmc_host= *host, writel(val, priv->scc_ctl + (addr << host->bus_shift)); } =20 +static void renesas_sdhi_set_tmpport(struct tmio_mmc_host *host, u32 tmppo= rt) +{ + struct renesas_sdhi *priv =3D host_to_priv(host); + u32 val; + + if (host->pdata->flags & TMIO_MMC_HS400MODE2) { + val =3D sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2); + val &=3D ~GENMASK(15, 0); /* TMPOUT MASK */ + val |=3D tmpport; + } else { + val =3D tmpport; + } + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, val); +} + static void renesas_sdhi_set_hw_adjustment_delay(struct tmio_mmc_host *hos= t) { struct renesas_sdhi *priv =3D host_to_priv(host); @@ -364,11 +391,11 @@ static void renesas_sdhi_set_hw_adjustment_delay(stru= ct tmio_mmc_host *host) return; =20 if (host->mmc->ios.signal_voltage =3D=3D MMC_SIGNAL_VOLTAGE_330) { - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0x0); + renesas_sdhi_set_tmpport(host, 0x0); if (hwadj2) sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HWADJ2, 0x3FFF); } else { - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0x1); + renesas_sdhi_set_tmpport(host, 0x1); if (hwadj2) sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HWADJ2, 0xFF); } @@ -477,6 +504,10 @@ static void renesas_sdhi_hs400_complete(struct mmc_hos= t *mmc) host->pdata->osel_tmpout) | sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); =20 + if (host->pdata->flags & TMIO_MMC_HS400MODE2) + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HS400MODE2, + RZG3L_SDHI_SCC_HS400MODE2_HS400EN2); + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | sd_scc_read32(host, priv, @@ -618,6 +649,9 @@ static void renesas_sdhi_reset_hs400_mode(struct tmio_m= mc_host *host, host->pdata->osel_tmpout) & sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); =20 + if (host->pdata->flags & TMIO_MMC_HS400MODE2) + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HS400MODE2, 0x0); + if (sdhi_has_quirk(priv, hs400_calib_table) || sdhi_has_quirk(priv, hs400= _bad_taps)) renesas_sdhi_adjust_hs400_mode_disable(host); =20 @@ -776,7 +810,7 @@ static int renesas_sdhi_execute_tuning(struct mmc_host = *mmc, u32 opcode) return 0; /* Tuning is not supported */ =20 if ((host->pdata->flags & TMIO_MMC_TUNING_DELAY) && priv->tap_num =3D=3D = 8) - sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0); + renesas_sdhi_set_tmpport(host, 0); =20 if (priv->tap_num * 2 >=3D sizeof(priv->taps) * BITS_PER_BYTE) { dev_err(&host->pdev->dev, diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index b1146dca94ca..8cd3ced88b81 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -178,7 +178,8 @@ static const struct renesas_sdhi_of_data of_data_rzg3l = =3D { .tmio_flags =3D TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 | TMIO_MMC_64BIT_DATA_PORT | TMIO_MMC_TUNING_DELAY | - TMIO_MMC_INTERNAL_DIVIDER | TMIO_MMC_HWADJ, + TMIO_MMC_INTERNAL_DIVIDER | TMIO_MMC_HWADJ | + TMIO_MMC_HS400MODE2, .capabilities =3D MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, .capabilities2 =3D MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, diff --git a/include/linux/platform_data/tmio.h b/include/linux/platform_da= ta/tmio.h index 501ca4355c34..81a37d6baefc 100644 --- a/include/linux/platform_data/tmio.h +++ b/include/linux/platform_data/tmio.h @@ -59,6 +59,9 @@ /* Some controllers have hw adjustment delay */ #define TMIO_MMC_HWADJ BIT(15) =20 +/* Some controllers have HS400MODE2 */ +#define TMIO_MMC_HS400MODE2 BIT(16) + struct tmio_mmc_data { void *chan_priv_tx; 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Thu, 23 Jul 2026 08:10:38 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Wolfram Sang , Ulf Hansson Cc: Biju Das , linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v22 13/13] mmc: renesas_sdhi: Add HS400 enhanced strobe support for RZ/G3L Date: Thu, 23 Jul 2026 16:10:17 +0100 Message-ID: <20260723151024.318918-14-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> References: <20260723151024.318918-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das RZ/G3L's HS400 enhanced strobe mode needs extra SCC register programming beyond the standard HS400 path. Add a TMIO_MMC_HS400ES flag (bit 17) for controllers that support it. Add renesas_sdhi_hs400_enhanced_strobe(), registered as host->ops.hs400_enhanced_strobe when the flag is set. On enable, it clears DTSEL and TAPEN, programs TMPPORT3 and HWADJ2, sets the HS400 interface bit in SDIF_MODE, sets HS400EN2 in HS400MODE2, and sets HS400EN plus the new HS400MODE1_ENHANCED_STROBE bit in TMPPORT2. On disable, only the enhanced-strobe-related bits are cleared. Also mask off HS400MODE1_ENHANCED_STROBE in renesas_sdhi_reset_hs400_mode() when TMIO_MMC_HS400ES is set, for a clean reset on mode exit. Since a controller reset clears these SCC registers, renesas_sdhi_reset() now re-invokes renesas_sdhi_hs400_enhanced_strobe() after reset whenever TMIO_MMC_HS400ES is set and the controller is currently in HS400 with enhanced strobe active, restoring the enhanced-strobe state instead of losing it across a reset. Enable TMIO_MMC_HS400ES in of_data_rzg3l to finalize RZ/G3L HS400 support. Signed-off-by: Biju Das --- v21->v22: * Updated commit description. * Restored the patch after fixing inode corruption. * renesas_sdhi_reset() now restores data strobe register values after reset. v20->v21: * Dropped the patch due to inode corruption during boot. v19->v20: * SD_CLK_CTRL clk enable turned off before updating SCC_CKSEL_DTSEL register. v18->v19: * Updated commit description. * HS400ES support is enabled based on of_data. * Fixed the space in HS400ES comment block. v18: * New patch. --- drivers/mmc/host/renesas_sdhi_core.c | 68 +++++++++++++++++-- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 2 +- include/linux/platform_data/tmio.h | 3 + 3 files changed, 68 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesa= s_sdhi_core.c index 541321e43a13..1db5b3339508 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -337,7 +337,8 @@ static int renesas_sdhi_card_busy(struct mmc_host *mmc) #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) =20 -#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) +#define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) +#define SH_MOBILE_SDHI_SCC_HS400MODE1_ENHANCED_STROBE BIT(30) =20 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) @@ -635,6 +636,8 @@ static void renesas_sdhi_adjust_hs400_mode_disable(stru= ct tmio_mmc_host *host) static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, struct renesas_sdhi *priv) { + u32 val =3D ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | host->pdata->osel_tmp= out); + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); =20 @@ -644,10 +647,11 @@ static void renesas_sdhi_reset_hs400_mode(struct tmio= _mmc_host *host, =20 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); =20 + if (host->pdata->flags & TMIO_MMC_HS400ES) + val &=3D ~SH_MOBILE_SDHI_SCC_HS400MODE1_ENHANCED_STROBE; + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, - ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | - host->pdata->osel_tmpout) & - sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); + val & sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); =20 if (host->pdata->flags & TMIO_MMC_HS400MODE2) sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HS400MODE2, 0x0); @@ -678,6 +682,53 @@ static void renesas_sdhi_scc_reset(struct tmio_mmc_hos= t *host, struct renesas_sd sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); } =20 +static void renesas_sdhi_hs400_enhanced_strobe(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct tmio_mmc_host *host =3D mmc_priv(mmc); + struct renesas_sdhi *priv =3D host_to_priv(host); + u32 val =3D sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2); + + if (!(host->pdata->flags & TMIO_MMC_HS400ES)) + return; + + if (ios->enhanced_strobe) { + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, + ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, + ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & + sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL)); + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, BIT(8) | BIT(9)); + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HWADJ2, 0xFF); + sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | + sd_ctrl_read16(host, CTL_SDIF_MODE)); + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HS400MODE2, + RZG3L_SDHI_SCC_HS400MODE2_HS400EN2); + + val |=3D SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | + SH_MOBILE_SDHI_SCC_HS400MODE1_ENHANCED_STROBE; + } else { + val &=3D ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | + SH_MOBILE_SDHI_SCC_HS400MODE1_ENHANCED_STROBE); + + sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & + sd_ctrl_read16(host, CTL_SDIF_MODE)); + + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HS400MODE2, 0); + } + + sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, val); +} + /* only populated for TMIO_MMC_MIN_RCAR2 */ static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve) { @@ -702,6 +753,13 @@ static void renesas_sdhi_reset(struct tmio_mmc_host *h= ost, bool preserve) /* Unknown why but without polling reset status, it will hang */ read_poll_timeout(reset_control_status, ret, ret =3D=3D 0, 1, 100, false, priv->rstc); + + /* Restore data strobe registers */ + if ((host->pdata->flags & TMIO_MMC_HS400ES) && + host->mmc->ios.timing =3D=3D MMC_TIMING_MMC_HS400 && + host->mmc->ios.enhanced_strobe) + renesas_sdhi_hs400_enhanced_strobe(host->mmc, &host->mmc->ios); + /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); if (priv->rdev) @@ -1399,6 +1457,8 @@ int renesas_sdhi_probe(struct platform_device *pdev, host->ops.prepare_hs400_tuning =3D renesas_sdhi_prepare_hs400_tuning; host->ops.hs400_downgrade =3D renesas_sdhi_disable_scc; host->ops.hs400_complete =3D renesas_sdhi_hs400_complete; + if (host->pdata->flags & TMIO_MMC_HS400ES) + host->ops.hs400_enhanced_strobe =3D renesas_sdhi_hs400_enhanced_strobe; } =20 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_al= l); diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/ho= st/renesas_sdhi_internal_dmac.c index 8cd3ced88b81..a47f17e9bf81 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -179,7 +179,7 @@ static const struct renesas_sdhi_of_data of_data_rzg3l = =3D { TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 | TMIO_MMC_64BIT_DATA_PORT | TMIO_MMC_TUNING_DELAY | TMIO_MMC_INTERNAL_DIVIDER | TMIO_MMC_HWADJ | - TMIO_MMC_HS400MODE2, + TMIO_MMC_HS400MODE2 | TMIO_MMC_HS400ES, .capabilities =3D MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, .capabilities2 =3D MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, diff --git a/include/linux/platform_data/tmio.h b/include/linux/platform_da= ta/tmio.h index 81a37d6baefc..758b29308955 100644 --- a/include/linux/platform_data/tmio.h +++ b/include/linux/platform_data/tmio.h @@ -62,6 +62,9 @@ /* Some controllers have HS400MODE2 */ #define TMIO_MMC_HS400MODE2 BIT(16) =20 +/* Some controllers have HS400ES */ +#define TMIO_MMC_HS400ES BIT(17) + struct tmio_mmc_data { void *chan_priv_tx; void *chan_priv_rx; --=20 2.43.0