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charset="utf-8" Add a binding for the Qualcomm LPASS VA CSR rate generator node that exposes the lpass_heartbeat_pulse clock on hawi. The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the start of the DMAs and Codec Interfaces for the audio usecase and can serve as a periodic wakeup source for the DSP. Signed-off-by: Sarath Ganapathiraju --- .../bindings/clock/qcom,lpass-va-csr.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,lpass-va-c= sr.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,lpass-va-csr.yaml= b/Documentation/devicetree/bindings/clock/qcom,lpass-va-csr.yaml new file mode 100644 index 000000000000..b4bc33a86640 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,lpass-va-csr.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,lpass-va-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS VA CSR heartbeat pulse clock provider + +maintainers: + - Srinivas Kandagatla + - Sarath Ganapathiraju + +description: + The LPASS (Low Power Audio Subsystem) VA CSR block contains a rate + generator that produces a periodic HeartBeat Pulse, also known as + the RateGen Pulse. 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charset="utf-8" The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the start of the DMAs and Codec Interfaces for the audio usecases and can serve as a periodic wakeup source for the DSP. Add the LPASS VA CSR driver that models the rate generator as a clock provider so it is enabled and disabled automatically alongside the other clocks during runtime PM resume and suspend. Signed-off-by: Sarath Ganapathiraju --- drivers/clk/qcom/Kconfig | 12 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpass-va-csr.c | 143 ++++++++++++++++++++++++++++++++ sound/soc/codecs/Kconfig | 1 + 4 files changed, 157 insertions(+) create mode 100644 drivers/clk/qcom/lpass-va-csr.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 63f271aff177..6ebdccfe37e0 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1998,6 +1998,18 @@ config CLK_GFM_LPASS_SM8250 Support for the Glitch Free Mux (GFM) Low power audio subsystem (LPASS) clocks found on SM8250 SoCs. =20 +config QCOM_CLK_LPASS_VA_CSR + tristate "Qualcomm LPASS VA CSR heartbeat pulse clock provider" + depends on COMMON_CLK + select REGMAP_MMIO + help + Qualcomm LPASS VA CSR block contains the rate generator hardware + that produces the HeartBeat Pulse (also known as RateGen Pulse). + This driver models the rate generator as a clock provider so + that consumers can enable or disable it via the common clock + framework, and it can be used to synchronize the start of DMAs + and Codec Interfaces or as a periodic wakeup source for the DSP. + config SM_VIDEOCC_8450 tristate "SM8450 Video Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index db7689ee5dc6..2be7da737eba 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_ELIZA_DISPCC) +=3D dispcc-eliza.o obj-$(CONFIG_CLK_ELIZA_GCC) +=3D gcc-eliza.o obj-$(CONFIG_CLK_ELIZA_TCSRCC) +=3D tcsrcc-eliza.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) +=3D lpass-gfm-sm8250.o +obj-$(CONFIG_QCOM_CLK_LPASS_VA_CSR) +=3D lpass-va-csr.o obj-$(CONFIG_CLK_GLYMUR_CAMCC) +=3D camcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_DISPCC) +=3D dispcc-glymur.o obj-$(CONFIG_CLK_GLYMUR_EVACC) +=3D evacc-glymur.o diff --git a/drivers/clk/qcom/lpass-va-csr.c b/drivers/clk/qcom/lpass-va-cs= r.c new file mode 100644 index 000000000000..1d0805789e25 --- /dev/null +++ b/drivers/clk/qcom/lpass-va-csr.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#define LPASS_RATE_GEN_CTRL 0xd000 +#define LPASS_RATE_GEN_COUNTER_0 0xd004 +#define LPASS_RATE_GEN_DELAY 0xd010 + +#define LPASS_RATE_GEN_MAX_REG LPASS_RATE_GEN_DELAY + +#define LPASS_RG_CTRL_EN BIT(0) + +struct lpass_va_csr_data { + u32 counter_0; + u32 delay; +}; + +static const struct lpass_va_csr_data hawi_csr_data =3D { + .counter_0 =3D 0x960, + .delay =3D 0x16, +}; + +static const struct regmap_config lpass_rate_gen_regmap_config =3D { + .name =3D "lpass_rate_gen", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D LPASS_RATE_GEN_MAX_REG, + .cache_type =3D REGCACHE_MAPLE, +}; + +struct lpass_va_csr { + struct regmap *regmap; + const struct lpass_va_csr_data *data; + struct clk_hw hb_hw; +}; + +#define to_lpass_va_csr(_hw) container_of(_hw, struct lpass_va_csr, hb_hw) + +static int heartbeat_pulse_prepare(struct clk_hw *hw) +{ + struct lpass_va_csr *csr =3D to_lpass_va_csr(hw); + int ret; + + ret =3D regmap_write(csr->regmap, LPASS_RATE_GEN_COUNTER_0, csr->data->co= unter_0); + if (ret) + return ret; + + ret =3D regmap_write(csr->regmap, LPASS_RATE_GEN_DELAY, csr->data->delay); + if (ret) + return ret; + + return regmap_set_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_EN= ); +} + +static void heartbeat_pulse_unprepare(struct clk_hw *hw) +{ + struct lpass_va_csr *csr =3D to_lpass_va_csr(hw); + + regmap_clear_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_EN); +} + +static int heartbeat_pulse_is_prepared(struct clk_hw *hw) +{ + struct lpass_va_csr *csr =3D to_lpass_va_csr(hw); + + return regmap_test_bits(csr->regmap, LPASS_RATE_GEN_CTRL, LPASS_RG_CTRL_E= N); +} + +static const struct clk_ops heartbeat_pulse_ops =3D { + .prepare =3D heartbeat_pulse_prepare, + .unprepare =3D heartbeat_pulse_unprepare, + .is_prepared =3D heartbeat_pulse_is_prepared, +}; + +static int lpass_va_csr_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct lpass_va_csr *csr; + struct clk_init_data init =3D { + .name =3D "lpass_heartbeat_pulse", + .ops =3D &heartbeat_pulse_ops, + }; + void __iomem *base; + int ret; + + csr =3D devm_kzalloc(dev, sizeof(*csr), GFP_KERNEL); + if (!csr) + return -ENOMEM; + + csr->data =3D of_device_get_match_data(dev); + if (!csr->data) + return dev_err_probe(dev, -EINVAL, "no variant data for compatible\n"); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + csr->regmap =3D devm_regmap_init_mmio(dev, base, + &lpass_rate_gen_regmap_config); + if (IS_ERR(csr->regmap)) + return dev_err_probe(dev, PTR_ERR(csr->regmap), + "failed to init regmap\n"); + + csr->hb_hw.init =3D &init; + + ret =3D devm_clk_hw_register(dev, &csr->hb_hw); + if (ret) + return dev_err_probe(dev, ret, "failed to register heartbeat clock\n"); + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &csr->hb_h= w); + if (ret) + return dev_err_probe(dev, ret, "failed to add clock provider\n"); + + return 0; +} + +static const struct of_device_id lpass_va_csr_dt_match[] =3D { + { .compatible =3D "qcom,hawi-lpass-va-csr", .data =3D &hawi_csr_data }, + {} +}; +MODULE_DEVICE_TABLE(of, lpass_va_csr_dt_match); + +static struct platform_driver lpass_va_csr_driver =3D { + .driver =3D { + .name =3D "qcom-lpass-va-csr", + .of_match_table =3D lpass_va_csr_dt_match, + }, + .probe =3D lpass_va_csr_probe, +}; + +module_platform_driver(lpass_va_csr_driver); + +MODULE_DESCRIPTION("Qualcomm LPASS VA CSR heartbeat pulse clock provider"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 76e90144ea91..704401faa147 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -2907,6 +2907,7 @@ config SND_SOC_LPASS_VA_MACRO depends on PM_CLK select REGMAP_MMIO select SND_SOC_LPASS_MACRO_COMMON + select QCOM_CLK_LPASS_VA_CSR tristate "Qualcomm VA Macro in LPASS(Low Power Audio SubSystem)" =20 config SND_SOC_LPASS_RX_MACRO --=20 2.34.1