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Thu, 23 Jul 2026 01:27:11 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Aleksandr Loktionov , Alexander Lobakin , Arthur Kiyanovski , Daniel Zahka , David Ahern , "Gal Pressman" , Jiri Pirko , Jiri Pirko , Jonathan Corbet , Leon Romanovsky , , , , Mark Bloch , Nikolay Aleksandrov , "Nikolay Aleksandrov" , Petr Machata , "Przemek Kitszel" , Ratheesh Kannoth , Saeed Mahameed , Shuah Khan , Simon Horman , Tariq Toukan , Vlad Dumitrescu Subject: [PATCH net-next V4 1/2] devlink: add generic device max_sfs parameter Date: Thu, 23 Jul 2026 11:26:42 +0300 Message-ID: <20260723082643.1870844-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260723082643.1870844-1-tariqt@nvidia.com> References: <20260723082643.1870844-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001708E:EE_|CY5PR12MB6384:EE_ X-MS-Office365-Filtering-Correlation-Id: 8b96deac-3e3c-4260-7469-08dee8943e52 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|82310400026|7416014|23010399003|376014|22082099003|18002099003|11063799006|10067099003|56012099006|6133799003; X-Microsoft-Antispam-Message-Info: wqjAd3raF/2I9Ib4giXlUSv94UMHp5GU9Wc32YR84z9DyHRk2GGb1lppLJl2TxIU8ZbxFoKBBCpwgjAyR+hmMbGeIXqLvOs5dMpXcaxypcIRNPOwChRGIpyI0Zxqvx4vjpRZhvGc6iD6m1bcEPvVGbSXvIm5FnFn+XQ+fWBum3HO9fKk6FTx7f4Pean0lB2BB9x8nvOqFVqOU1XvFJptuyRtlmyfAOAlNw6V0vcT7fYDxtmQFItDjUdwPUo7/AAT0384Ojg8jfpIAz5OS2mu9W4RxdxjOiccd12ab/9/fDsEGnHGqBlO+2RbqczZjQJbHJ+Cp9HKceE34qxTuw0GNT2AuJINlJxwnALeU0OOuofwpDefFwamsEAKxW88Gv9M5AbCYO2jnHEp7aEW3DOSqoh0z3+mXuuIK2Wbp7X30oP0Qs8CWlgYU7Jx9f18fq9kPl/OrfL57dybqg+R2ycGvE+yZcN366r/rRMelKNoootuZZlu47JVOvF/sN42waosBeMGGohOiz8+bOMYXzMmsYDc0kNzOhQQx8Cy984TCmz8u1KHTV8o1kcqiMY78U50gdaufS0WN5cPL+Ue2e8apUyrtQDPnB3Gal0jTldjo0cZe+DOoUiqc8cdFW+3jGkt5OfpNADQOLZQkvCG3zgi1dZUj2re5PUhpSH5tBi54rYw46bqrON3oDorL58YuDOyWXdc8LOLmPPeSYldQMEW2Q== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(82310400026)(7416014)(23010399003)(376014)(22082099003)(18002099003)(11063799006)(10067099003)(56012099006)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: frz1MyO6q9IBEAc1gP0GLmfoERM4XpDUm/l9a2K/Q5ffiiG/K/++yFteudH2Kf7lka6RnMXvxfYVzdVCKX8FZJJaxF55ScX5JmgCyvzi4SpNAxxqnb3N075VauFIvPBA4DJAJ/6Fh0afKev3W9GzpAz3SG+TKJulYPhIr9xpcLG6EP+r9vJ6ghtOn+dvJFIkyCVO1gukKNrZyDVAqCqQ0eqYnBv8Y7HvM0iWWpGKb9wWr8TX+vdPCNQ/d07Mc9CD6WfQho4M79RB7/9l4JRQR42uBMBjSiOZXnhouZJscmoMWBIVIXbhJtl1ijQhM4ZRIqfhod+fQMtvm8RO0TjTjzKwiG8em7iVIAfKO49Bx94RPt03F74PHbH+IQZdkUZl2R4gWz16JT67jr19RhE4Lob7jLnwcRIJK90DqNlZBFJDQNVXs9DIvPdtTh0jEtK/ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2026 08:27:33.0128 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8b96deac-3e3c-4260-7469-08dee8943e52 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001708E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6384 Content-Type: text/plain; charset="utf-8" From: Nikolay Aleksandrov Add a new generic devlink device parameter (max_sfs) to control if and how many light-weight NIC subfunctions can be created. Subfunctions are a light-weight network functions backed by an underlying PCI function. Their lifecycle can already be managed by devlink, but currently users cannot enable them in the device. They can be enabled/disabled only via external vendor tools. This parameter allows subfunctions to be enabled (>0) or disabled (0) via devlink. A subsequent patch will add support for max_sfs to the mlx5 driver. Signed-off-by: Nikolay Aleksandrov Reviewed-by: David Ahern Reviewed-by: Jiri Pirko Reviewed-by: Aleksandr Loktionov Reviewed-by: Alexander Lobakin Signed-off-by: Tariq Toukan --- Documentation/networking/devlink/devlink-params.rst | 6 ++++++ include/net/devlink.h | 4 ++++ net/devlink/param.c | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/Documentation/networking/devlink/devlink-params.rst b/Document= ation/networking/devlink/devlink-params.rst index ca19ee3e63c8..13eb8aa84c38 100644 --- a/Documentation/networking/devlink/devlink-params.rst +++ b/Documentation/networking/devlink/devlink-params.rst @@ -165,3 +165,9 @@ own name. - u32 - Controls the maximum number of MAC address filters that can be assi= gned to a Virtual Function (VF). + * - ``max_sfs`` + - u32 + - The maximum number of subfunctions which can be created on the devi= ce. + Modifying this parameter may require a device restart and PCI bus + rescanning because the BAR layout may change. A value of 0 disables + subfunction creation. diff --git a/include/net/devlink.h b/include/net/devlink.h index 4830aba4087a..7abd23376319 100644 --- a/include/net/devlink.h +++ b/include/net/devlink.h @@ -554,6 +554,7 @@ enum devlink_param_generic_id { DEVLINK_PARAM_GENERIC_ID_TOTAL_VFS, DEVLINK_PARAM_GENERIC_ID_NUM_DOORBELLS, DEVLINK_PARAM_GENERIC_ID_MAX_MAC_PER_VF, + DEVLINK_PARAM_GENERIC_ID_MAX_SFS, =20 /* add new param generic ids above here*/ __DEVLINK_PARAM_GENERIC_ID_MAX, @@ -627,6 +628,9 @@ enum devlink_param_generic_id { #define DEVLINK_PARAM_GENERIC_MAX_MAC_PER_VF_NAME "max_mac_per_vf" #define DEVLINK_PARAM_GENERIC_MAX_MAC_PER_VF_TYPE DEVLINK_PARAM_TYPE_U32 =20 +#define DEVLINK_PARAM_GENERIC_MAX_SFS_NAME "max_sfs" +#define DEVLINK_PARAM_GENERIC_MAX_SFS_TYPE DEVLINK_PARAM_TYPE_U32 + #define DEVLINK_PARAM_GENERIC(_id, _cmodes, _get, _set, _validate) \ { \ .id =3D DEVLINK_PARAM_GENERIC_ID_##_id, \ diff --git a/net/devlink/param.c b/net/devlink/param.c index 1cc562a6ebfd..8ca0f3ed646c 100644 --- a/net/devlink/param.c +++ b/net/devlink/param.c @@ -117,6 +117,11 @@ static const struct devlink_param devlink_param_generi= c[] =3D { .name =3D DEVLINK_PARAM_GENERIC_MAX_MAC_PER_VF_NAME, .type =3D DEVLINK_PARAM_GENERIC_MAX_MAC_PER_VF_TYPE, }, + { + .id =3D DEVLINK_PARAM_GENERIC_ID_MAX_SFS, + .name =3D DEVLINK_PARAM_GENERIC_MAX_SFS_NAME, + .type =3D DEVLINK_PARAM_GENERIC_MAX_SFS_TYPE, + }, }; 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Thu, 23 Jul 2026 01:27:20 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Aleksandr Loktionov , Alexander Lobakin , Arthur Kiyanovski , Daniel Zahka , David Ahern , "Gal Pressman" , Jiri Pirko , Jiri Pirko , Jonathan Corbet , Leon Romanovsky , , , , Mark Bloch , Nikolay Aleksandrov , "Nikolay Aleksandrov" , Petr Machata , "Przemek Kitszel" , Ratheesh Kannoth , Saeed Mahameed , Shuah Khan , Simon Horman , Tariq Toukan , Vlad Dumitrescu Subject: [PATCH net-next V4 2/2] net/mlx5: implement max_sfs parameter Date: Thu, 23 Jul 2026 11:26:43 +0300 Message-ID: <20260723082643.1870844-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260723082643.1870844-1-tariqt@nvidia.com> References: <20260723082643.1870844-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7C:EE_|MN0PR12MB5836:EE_ X-MS-Office365-Filtering-Correlation-Id: aca507f8-1a17-43a4-ef3f-08dee8944552 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|376014|7416014|82310400026|1800799024|6133799003|56012099006|11063799006|10067099003|22082099003|18002099003|3023799007; X-Microsoft-Antispam-Message-Info: RlrXOZks7RIK57B/YsVELHG6cYp0aRhFcZ7OKW0NOtPKL7J1pjD7tMCdRqRC2v/YTVp10vUgza8Mw8nSmzcMBfhMtP8PMumrF8zml9D3PKXqOJCOd2Oue2Qydz86Svu4dWSjVtllhudxLla8P7MZkf/CJTxp4Q2uO6ZPYOl1sC9yzkwf1rFgNRyg8O5E+Jb34TyjJ8oxMQNq2LLjmPPLQrutStz42/C3UdQb2FfZ5awGBwMWOMw9DlMnzoKFl1+6MDCuvkWcffUfNlYTIhOj7+y8MqW7PxGYzmAXI2W8vZHhVjb8MGFZ52TQVZqqeCbyeDxDcot2w3o9cjf5LHjwXxlUP2DlSdXouRc9IS3NqoWHZf7wBlw3TTyHlslik1j9wbhmXq3NGtyj2KEOcus5gvHEVsGwj+9YOnhBfMPqTyKZKFIlZ7rFFHwiONPqHXpxkkFCzvhe0IKuRBsVEP4wFVXiGJPuYMKWy0WmD8pD3UbJQITxLOq8RlwbFEsie1qJKriyXr0l08t+rFyxwJQDkx9T7NmIUvagT6Ych7cSf+hmFSsZ9yJRtgkicEniwTPVJp5YjDuhqZpKEiaVA36W9RR7JmJ2WprurhMZsot03Fz1KWS7hVq8TW/batymG3azkJp/zV7iGkvVXVQbuTcZXVeBN5MyLLW1DUN1nqJGJ1n1yWzVrprGE4nPR4bj7ptnwzzkF5NMc+3QBXANVGbwTA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(23010399003)(376014)(7416014)(82310400026)(1800799024)(6133799003)(56012099006)(11063799006)(10067099003)(22082099003)(18002099003)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MJzN7w1SY0H+ivaEC7yIWzhau+QOJBYy2PyAEm5cpBlJHG9LZvpFU9fYqYFsSI1YDXik72IFXmg+w7X4QvukuTmsZ73czCiNEqUuRCUWDXHMJUmx6kEZyrme6nZzhi6UXaIFbIAuATXCa7zcqWzZTIO0L/uv4n3OdaZLuQO0j7drcnLjprM9/13PWdqvAtnJ0Sgw2VQmh/DobUNiwNGylxAaZzD55pbrGqN8PMbWetMsIu2bQaTLx2VAB9geegFYYHRw5J+Qt7QjOYQ8zU3HknLPTygOUIfbGnLoKlrE7Z7+kp8K1xK1ARZT+7rUfYpa9Fsw9AligLi5jrDeMIhRe9uwIt8vYIks4JtWZHCY12sKoQ4ZwIoyG1dDe4/Zu93U0MUmgOt8yRFBseY6MmsNf4UnzBrADPuMY6FR6H5ICq/7Ovls14dCh6fCA47ZE/7I X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jul 2026 08:27:44.7467 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aca507f8-1a17-43a4-ef3f-08dee8944552 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5836 Content-Type: text/plain; charset="utf-8" From: Nikolay Aleksandrov Implement max_sfs generic parameter to allow users to control the total light-weight NIC subfunctions that can be created using devlink instead of external vendor tools. A value of 0 will effectively disable creation of new subfunction devices. A warning is sent to user-space via extack (returning extack without error code is interpreted as a warning by user-space tools). The maximum value is capped at U16_MAX. Signed-off-by: Nikolay Aleksandrov Reviewed-by: David Ahern Reviewed-by: Alexander Lobakin Signed-off-by: Tariq Toukan --- Documentation/networking/devlink/mlx5.rst | 7 +- .../mellanox/mlx5/core/lib/nv_param.c | 118 +++++++++++++++++- 2 files changed, 121 insertions(+), 4 deletions(-) diff --git a/Documentation/networking/devlink/mlx5.rst b/Documentation/netw= orking/devlink/mlx5.rst index cf1dffa67669..9421c89951a0 100644 --- a/Documentation/networking/devlink/mlx5.rst +++ b/Documentation/networking/devlink/mlx5.rst @@ -45,8 +45,13 @@ Parameters - The range is between 1 and a device-specific max. - Applies to each physical function (PF) independently, if the device supports it. Otherwise, it applies symmetrically to all PFs. + * - ``max_sfs`` + - permanent + - The range is between 0 and a device-specific max. + - Applies to each physical function (PF) independently. =20 -Note: permanent parameters such as ``enable_sriov`` and ``total_vfs`` requ= ire FW reset to take effect +Note: permanent parameters such as ``enable_sriov``, ``total_vfs`` and ``m= ax_sfs`` + require FW reset to take effect =20 .. code-block:: bash =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c b/drive= rs/net/ethernet/mellanox/mlx5/core/lib/nv_param.c index 4a7275e8b62e..492ae0d56a97 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c @@ -68,7 +68,9 @@ struct mlx5_ifc_mnvda_reg_bits { =20 struct mlx5_ifc_nv_global_pci_conf_bits { u8 sriov_valid[0x1]; - u8 reserved_at_1[0x10]; + u8 reserved_at_1[0xa]; + u8 per_pf_num_sf[0x1]; + u8 reserved_at_c[0x5]; u8 per_pf_total_vf[0x1]; u8 reserved_at_12[0xe]; =20 @@ -93,9 +95,11 @@ struct mlx5_ifc_nv_global_pci_cap_bits { }; =20 struct mlx5_ifc_nv_pf_pci_conf_bits { - u8 reserved_at_0[0x9]; + u8 log_sf_bar_size[0x8]; + u8 pf_total_sf_en[0x1]; u8 pf_total_vf_en[0x1]; - u8 reserved_at_a[0x16]; + u8 reserved_at_a[0x6]; + u8 total_sf[0x10]; =20 u8 reserved_at_20[0x20]; =20 @@ -158,6 +162,8 @@ struct mlx5_ifc_nv_sw_accelerate_conf_bits { #define MLX5_GET_CFG_HDR_LEN(_mnvda_ptr) \ MLX5_GET(mnvda_reg, _mnvda_ptr, configuration_item_header.length) =20 +#define MLX5_DEFAULT_LOG_SF_BAR_SIZE 12 + static int mlx5_nv_param_read(struct mlx5_core_dev *dev, void *mnvda, size_t len) { @@ -755,6 +761,108 @@ static int mlx5_devlink_total_vfs_validate(struct dev= link *devlink, u32 id, return 0; } =20 +static int mlx5_devlink_max_sfs_get(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct mlx5_core_dev *dev =3D devlink_priv(devlink); + u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] =3D {}; + void *data; + int err; + + err =3D mlx5_nv_param_read_global_pci_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to read global PCI configuration"); + return err; + } + + data =3D MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + if (!MLX5_GET(nv_global_pci_conf, data, per_pf_num_sf)) { + ctx->val.vu32 =3D 0; + return 0; + } + + memset(mnvda, 0, sizeof(mnvda)); + err =3D mlx5_nv_param_read_per_host_pf_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, "Failed to read PF configuration"); + return err; + } + + data =3D MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + if (MLX5_GET(nv_pf_pci_conf, data, pf_total_sf_en)) + ctx->val.vu32 =3D MLX5_GET(nv_pf_pci_conf, data, total_sf); + else + ctx->val.vu32 =3D 0; + + return 0; +} + +static int mlx5_devlink_max_sfs_validate(struct devlink *devlink, u32 id, + union devlink_param_value *val, + struct netlink_ext_ack *extack) +{ + if (val->vu32 > U16_MAX) { + NL_SET_ERR_MSG_FMT_MOD(extack, + "Max SFs allowed value is %u", U16_MAX); + return -EINVAL; + } + + return 0; +} + +static int mlx5_devlink_max_sfs_set(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct mlx5_core_dev *dev =3D devlink_priv(devlink); + u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] =3D {}; + void *data; + int err; + + err =3D mlx5_nv_param_read_global_pci_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to read global PCI configuration"); + return err; + } + + data =3D MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + MLX5_SET(nv_global_pci_conf, data, per_pf_num_sf, !!ctx->val.vu32); + + err =3D mlx5_nv_param_write(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to change per_pf_num_sf global PCI configuration"); + return err; + } + + memset(mnvda, 0, sizeof(mnvda)); + err =3D mlx5_nv_param_read_per_host_pf_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, "Failed to read PF configuration"); + return err; + } + + data =3D MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + MLX5_SET(nv_pf_pci_conf, data, log_sf_bar_size, + ctx->val.vu32 ? MLX5_DEFAULT_LOG_SF_BAR_SIZE : 0); + MLX5_SET(nv_pf_pci_conf, data, pf_total_sf_en, !!ctx->val.vu32); + MLX5_SET(nv_pf_pci_conf, data, total_sf, ctx->val.vu32); + + err =3D mlx5_nv_param_write(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to change PF PCI configuration"); + return err; + } + NL_SET_ERR_MSG(extack, + "Modifying max_sfs requires a FW reset and PCI bus rescan"); + + return 0; +} + static const struct devlink_param mlx5_nv_param_devlink_params[] =3D { DEVLINK_PARAM_GENERIC(ENABLE_SRIOV, BIT(DEVLINK_PARAM_CMODE_PERMANENT), mlx5_devlink_enable_sriov_get, @@ -763,6 +871,10 @@ static const struct devlink_param mlx5_nv_param_devlin= k_params[] =3D { mlx5_devlink_total_vfs_get, mlx5_devlink_total_vfs_set, mlx5_devlink_total_vfs_validate), + DEVLINK_PARAM_GENERIC(MAX_SFS, BIT(DEVLINK_PARAM_CMODE_PERMANENT), + mlx5_devlink_max_sfs_get, + mlx5_devlink_max_sfs_set, + mlx5_devlink_max_sfs_validate), DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_CQE_COMPRESSION_TYPE, "cqe_compress_type", DEVLINK_PARAM_TYPE_STRING, BIT(DEVLINK_PARAM_CMODE_PERMANENT), --=20 2.44.0