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Avoid registering a reset controller in such cases by checking desc->num_resets. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Vladimir Zapolskiy Signed-off-by: Imran Shaik --- drivers/clk/qcom/common.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 2c09abaf1d2a15b7fbbbfeb67c03075381185a00..d6ff83045da8f308dcb9c5836af= 48090323248de 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -359,17 +359,19 @@ int qcom_cc_really_probe(struct device *dev, qcom_cc_clk_regs_configure(dev, desc->driver_data, regmap); } =20 - reset =3D &cc->reset; - reset->rcdev.of_node =3D dev->of_node; - reset->rcdev.ops =3D &qcom_reset_ops; - reset->rcdev.owner =3D dev->driver->owner; - reset->rcdev.nr_resets =3D desc->num_resets; - reset->regmap =3D regmap; - reset->reset_map =3D desc->resets; - - ret =3D devm_reset_controller_register(dev, &reset->rcdev); - if (ret) - goto put_rpm; + if (desc->num_resets) { + reset =3D &cc->reset; + reset->rcdev.of_node =3D dev->of_node; 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Signed-off-by: Imran Shaik --- .../bindings/clock/qcom,shikra-audiocorecc.yaml | 55 ++++++++++++++++++= ++++ .../bindings/reset/qcom,shikra-audiocore-csr.yaml | 42 +++++++++++++++++ .../dt-bindings/clock/qcom,shikra-audiocorecc.h | 49 +++++++++++++++++++ 3 files changed, 146 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorec= c.yaml b/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.ya= ml new file mode 100644 index 0000000000000000000000000000000000000000..d59f7e47a0d7d9ee9def49be995= 4038e43785e91 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,shikra-audiocorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Audio Core Clock Controller for Qualcomm Shikra SoC + +maintainers: + - Imran Shaik + +description: | + Audio core clock control module provides the clocks on Qualcomm Shikra + SoC platform. + + See also: + - include/dt-bindings/clock/qcom,shikra-audiocorecc.h + +properties: + compatible: + const: qcom,shikra-audiocorecc + + clocks: + items: + - description: Board XO source + - description: Board sleep clock + - description: Audio ref clock source + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + #include + clock-controller@a0a0000 { + compatible =3D "qcom,shikra-audiocorecc"; + reg =3D <0x0a0a0000 0x10000>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&aud_ref_clk_src>; + #clock-cells =3D <1>; + }; +... diff --git a/Documentation/devicetree/bindings/reset/qcom,shikra-audiocore-= csr.yaml b/Documentation/devicetree/bindings/reset/qcom,shikra-audiocore-cs= r.yaml new file mode 100644 index 0000000000000000000000000000000000000000..bfad1d20e7cd1281c4c182d5f9f= 887d8c4c86125 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/qcom,shikra-audiocore-csr.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/qcom,shikra-audiocore-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Audio Core CSR for Qualcomm Shikra SoC + +maintainers: + - Imran Shaik + +description: | + Audio Core CSR module provides the resets on Qualcomm Shikra SoC platfor= m. + + See also: + - include/dt-bindings/clock/qcom,shikra-audiocorecc.h + +properties: + compatible: + const: qcom,shikra-audiocore-csr + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + reset-controller@a0b4000 { + compatible =3D "qcom,shikra-audiocore-csr"; + reg =3D <0x0a0b4000 0x1000>; + #reset-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,shikra-audiocorecc.h b/include/= dt-bindings/clock/qcom,shikra-audiocorecc.h new file mode 100644 index 0000000000000000000000000000000000000000..0e64a42523f1ec4213ce8cbbbe6= f8262d414f0eb --- /dev/null +++ b/include/dt-bindings/clock/qcom,shikra-audiocorecc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_AUDIO_CORE_CC_SHIKRA_H +#define _DT_BINDINGS_CLK_QCOM_AUDIO_CORE_CC_SHIKRA_H + +/* AUDIO_CORE_CC clocks */ +#define AUDIO_CORE_CC_DIG_PLL_OUT_AUX 0 +#define AUDIO_CORE_CC_DIG_PLL_OUT_AUX2 1 +#define AUDIO_CORE_CC_DIG_PLL 2 +#define AUDIO_CORE_CC_AIF_IF0_CLK_SRC 3 +#define AUDIO_CORE_CC_AIF_IF0_EBIT_CLK 4 +#define AUDIO_CORE_CC_AIF_IF0_IBIT_CLK 5 +#define AUDIO_CORE_CC_AIF_IF1_CLK_SRC 6 +#define AUDIO_CORE_CC_AIF_IF1_EBIT_CLK 7 +#define AUDIO_CORE_CC_AIF_IF1_IBIT_CLK 8 +#define AUDIO_CORE_CC_AIF_IF2_CLK_SRC 9 +#define AUDIO_CORE_CC_AIF_IF2_EBIT_CLK 10 +#define AUDIO_CORE_CC_AIF_IF2_IBIT_CLK 11 +#define AUDIO_CORE_CC_AIF_IF3_CLK_SRC 12 +#define AUDIO_CORE_CC_AIF_IF3_EBIT_CLK 13 +#define AUDIO_CORE_CC_AIF_IF3_IBIT_CLK 14 +#define AUDIO_CORE_CC_AUD_DMA_CLK 15 +#define AUDIO_CORE_CC_AUD_DMA_CLK_SRC 16 +#define AUDIO_CORE_CC_AUD_DMA_MEM_CLK 17 +#define AUDIO_CORE_CC_BUS_CLK 18 +#define AUDIO_CORE_CC_BUS_CLK_SRC 19 +#define AUDIO_CORE_CC_CDIV_TX_MCLK_DIV_CLK_SRC 20 +#define AUDIO_CORE_CC_EXT_MCLKA_CLK_SRC 21 +#define AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK 22 +#define AUDIO_CORE_CC_EXT_MCLKB_CLK_SRC 23 +#define AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK 24 +#define AUDIO_CORE_CC_IM_SLEEP_CLK 25 +#define AUDIO_CORE_CC_LPAIF_PCMOE_CLK 26 +#define AUDIO_CORE_CC_LPAIF_PCMOE_CLK_SRC 27 +#define AUDIO_CORE_CC_RX_MCLK_2X_CLK 28 +#define AUDIO_CORE_CC_RX_MCLK_CLK 29 +#define AUDIO_CORE_CC_SAMPLING_CLK 30 +#define AUDIO_CORE_CC_TX_MCLK_2X_CLK 31 +#define AUDIO_CORE_CC_TX_MCLK_CLK 32 +#define AUDIO_CORE_CC_TX_MCLK_RCG_CLK_SRC 33 + +/* AUDIO_CORE_CSR resets */ +#define AUDIO_CORE_CSR_RX_SWR_CGCR 0 +#define AUDIO_CORE_CSR_TX_SWR_CGCR 1 + +#endif --=20 2.34.1 From nobody Fri Jul 24 05:22:24 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD2B244E671 for ; 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Thu, 23 Jul 2026 08:46:22 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf8efd7157sm36242625ad.18.2026.07.23.08.46.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 08:46:22 -0700 (PDT) From: Imran Shaik Date: Thu, 23 Jul 2026 21:15:52 +0530 Subject: [PATCH v3 3/4] clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-shikra-audiocorecc-v3-3-90b878ae0d4e@oss.qualcomm.com> References: <20260723-shikra-audiocorecc-v3-0-90b878ae0d4e@oss.qualcomm.com> In-Reply-To: <20260723-shikra-audiocorecc-v3-0-90b878ae0d4e@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Imran Shaik , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Proofpoint-ORIG-GUID: qxaEM0Gw7ZXr1-QDO_9Z89Xdly4aBQTN X-Proofpoint-GUID: qxaEM0Gw7ZXr1-QDO_9Z89Xdly4aBQTN X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIzMDE1NSBTYWx0ZWRfX3epZsvW1AmqE EdcG8HKb3UiULphTNyEUW7TdK2PYQJeOdKGopTZdm7Xh9JvnP529UMSbpUrVCuCFQmpu6vWYzVQ n6hXR7OzlJs5XFTY7iRVPTIGC2OEAEY= X-Authority-Analysis: v=2.4 cv=L/ItheT8 c=1 sm=1 tr=0 ts=6a623751 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=F_syqbkkfc-CeLG8pkkA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIzMDE1NSBTYWx0ZWRfXwWQ2/xduUlVv MrMwiBYk0OZZdBozGL3E78RoFsrfjbWvMBJThdZsRZe4l9ePJjeQOQSX9egYZaSQR7KXEEZEuSU qQ130fjAuhQXPAgwUR0XW9SAjpk6h6TKeqcZTNaeKk3t+f4k3WOfaQSRhAlk8+FomJDldwRIB6M cNPgYZyeU7sxF6NNmH/9Ab+9/IYFzl2iXnzti//H6HBH2K1BG0APNHc2K+k8BtgW5siPVCtdLhm BNd2DDij8WpNmdoGRwWKgZ92CAb1tcxuJwPdnUL3PypwT34h2nk+J8tHzlrfYwuwrK0URR/kvGM k/jaXXhaWOSbqybVpKTFNlsMSUXTbK2LGtfWh8tHtnCArDtaIp93GkWDZZ4zAjAfEI7avgi8aOh 4yWYVH6xZJs9usgdLMqzalXWYGvcOW9HXEvgANtmMBzF0cmkSv5ZizLXjJcyk2BmJQyXXeoF5eg i4iZi7qiaK0+u5bNFVg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-23_04,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607230155 Add support for Audio Core Clock Controller (AUDIOCORECC) and Audio Core CSR resets on Qualcomm Shikra SoC. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Imran Shaik --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/audiocorecc-shikra.c | 809 ++++++++++++++++++++++++++++++= ++++ 3 files changed, 820 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 63f271aff1771bea0885fb753dd28d02fd7d4ab6..29ae37ece3141438d6fb8162cc7= ad3a361c5323c 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -192,6 +192,16 @@ config CLK_NORD_GCC SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination of GCC, SE_GCC, NE_GCC and NW_GCC. =20 +config CLK_SHIKRA_AUDIOCORECC + tristate "Shikra Audio Core Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_SHIKRA_GCC + default m if ARCH_QCOM + help + Support for the Audio Core clock controller on Qualcomm Shikra devices. + Say Y if you want to use AudioCoreCC clocks required to support audio + devices and it's functionality. + config CLK_SHIKRA_GCC tristate "Shikra Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index db7689ee5dc63bc8b7d12b8222188bc1e1ff78ba..f26a79658bb88c957f990d76d29= 5a5a9a09bb7ee 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o +obj-$(CONFIG_CLK_SHIKRA_AUDIOCORECC) +=3D audiocorecc-shikra.o obj-$(CONFIG_CLK_SHIKRA_GCC) +=3D gcc-shikra.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o diff --git a/drivers/clk/qcom/audiocorecc-shikra.c b/drivers/clk/qcom/audio= corecc-shikra.c new file mode 100644 index 0000000000000000000000000000000000000000..76017240f7684da5e2fc5b8ab7e= c2d3a3793da56 --- /dev/null +++ b/drivers/clk/qcom/audiocorecc-shikra.c @@ -0,0 +1,809 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_AUD_REF_CLK_SRC, +}; + +enum { + P_AUD_REF_CLK_SRC, + P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, + P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, + P_BI_TCXO, + P_SLEEP_CLK, +}; + +static const struct pll_vco spark_vco[] =3D { + { 500000000, 1000000000, 2 }, +}; + +/* 614.4 MHz Configuration */ +static const struct alpha_pll_config audio_core_cc_dig_pll_config =3D { + .l =3D 0x20, + .alpha =3D 0x0, + .vco_val =3D BIT(21), + .post_div_val =3D 0x28100, + .post_div_mask =3D GENMASK(17, 8), + .vco_mask =3D GENMASK(21, 20), + .main_output_mask =3D BIT(0), + .aux_output_mask =3D BIT(1), + .aux2_output_mask =3D BIT(2), + .config_ctl_val =3D 0x4001055b, + .test_ctl_hi_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, +}; + +static struct clk_alpha_pll audio_core_cc_dig_pll =3D { + .offset =3D 0x0, + .config =3D &audio_core_cc_dig_pll_config, + .vco_table =3D spark_vco, + .num_vco =3D ARRAY_SIZE(spark_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_dig_pll", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_ops, + }, + }, +}; + +static struct clk_fixed_factor audio_core_cc_dig_pll_out_aux =3D { + .mult =3D 1, + .div =3D 5, + .hw.init =3D &(struct clk_init_data) { + .name =3D "audio_core_cc_dig_pll_out_aux", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &audio_core_cc_dig_pll.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static struct clk_fixed_factor audio_core_cc_dig_pll_out_aux2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data) { + .name =3D "audio_core_cc_dig_pll_out_aux2", + .parent_data =3D &(const struct clk_parent_data) { + .hw =3D &audio_core_cc_dig_pll.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_fixed_factor_ops, + }, +}; + +static const struct parent_map audio_core_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_AUD_REF_CLK_SRC, 1 }, + { P_SLEEP_CLK, 2 }, + { P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 4 }, + { P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 6 }, +}; + +static const struct clk_parent_data audio_core_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_AUD_REF_CLK_SRC }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &audio_core_cc_dig_pll_out_aux.hw }, + { .hw =3D &audio_core_cc_dig_pll_out_aux2.hw }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_aif_if0_clk_src[] =3D { + F(240000, P_BI_TCXO, 10, 1, 8), + F(256000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 32), + F(512000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 16), + F(768000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 16), + F(1024000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 8), + F(1536000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 8), + F(2048000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 4), + F(3072000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 4), + F(4096000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 2), + F(6144000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 2), + F(8192000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 0, 0), + F(9600000, P_BI_TCXO, 2, 0, 0), + F(12288000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_aif_if0_clk_src =3D { + .cmd_rcgr =3D 0x104c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if0_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 audio_core_cc_aif_if1_clk_src =3D { + .cmd_rcgr =3D 0x10b0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if1_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 audio_core_cc_aif_if2_clk_src =3D { + .cmd_rcgr =3D 0x1114, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if2_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_aif_if3_clk_src[] =3D { + F(240000, P_BI_TCXO, 10, 1, 8), + F(256000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 32), + F(512000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 16), + F(768000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 16), + F(1024000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 8), + F(1536000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 8), + F(2048000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 4), + F(3072000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 4), + F(4096000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 1, 2), + F(6144000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 1, 2), + F(8192000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 15, 0, 0), + F(9600000, P_BI_TCXO, 2, 0, 0), + F(12288000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 10, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0), + F(49152000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_aif_if3_clk_src =3D { + .cmd_rcgr =3D 0x1178, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aif_if3_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if3_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_aud_dma_clk_src[] =3D { + F(38400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 8, 0, 0), + F(102400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 3, 0, 0), + F(153600000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 2, 0, 0), + F(307200000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 1, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_aud_dma_clk_src =3D { + .cmd_rcgr =3D 0x1028, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aud_dma_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aud_dma_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_bus_clk_src[] =3D { + F(38400000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 8, 0, 0), + F(76800000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX2, 4, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_bus_clk_src =3D { + .cmd_rcgr =3D 0x1008, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_bus_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_bus_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 audio_core_cc_ext_mclka_clk_src =3D { + .cmd_rcgr =3D 0x123c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_ext_mclka_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 audio_core_cc_ext_mclkb_clk_src =3D { + .cmd_rcgr =3D 0x125c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_aif_if0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_ext_mclkb_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_lpaif_pcmoe_clk_src[] =3D { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(15360000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 8, 0, 0), + F(30720000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 4, 0, 0), + F(61440000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 2, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_lpaif_pcmoe_clk_src =3D { + .cmd_rcgr =3D 0x12ac, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_lpaif_pcmoe_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_lpaif_pcmoe_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_audio_core_cc_tx_mclk_rcg_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24576000, P_AUDIO_CORE_CC_DIG_PLL_OUT_AUX, 5, 0, 0), + { } +}; + +static struct clk_rcg2 audio_core_cc_tx_mclk_rcg_clk_src =3D { + .cmd_rcgr =3D 0x127c, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D audio_core_cc_parent_map_0, + .freq_tbl =3D ftbl_audio_core_cc_tx_mclk_rcg_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_tx_mclk_rcg_clk_src", + .parent_data =3D audio_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(audio_core_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div audio_core_cc_cdiv_tx_mclk_div_clk_src =3D { + .reg =3D 0x129c, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_cdiv_tx_mclk_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch audio_core_cc_aif_if0_ebit_clk =3D { + .halt_reg =3D 0x1068, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if0_ebit_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if0_ibit_clk =3D { + .halt_reg =3D 0x1064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if0_ibit_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_aif_if0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if1_ebit_clk =3D { + .halt_reg =3D 0x10cc, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x10cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if1_ebit_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if1_ibit_clk =3D { + .halt_reg =3D 0x10c8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x10c8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if1_ibit_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_aif_if1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if2_ebit_clk =3D { + .halt_reg =3D 0x1130, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1130, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if2_ebit_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if2_ibit_clk =3D { + .halt_reg =3D 0x112c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x112c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if2_ibit_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_aif_if2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if3_ebit_clk =3D { + .halt_reg =3D 0x1194, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x1194, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if3_ebit_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aif_if3_ibit_clk =3D { + .halt_reg =3D 0x1190, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1190, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aif_if3_ibit_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_aif_if3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aud_dma_clk =3D { + .halt_reg =3D 0x1040, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x1040, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aud_dma_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_aud_dma_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_aud_dma_mem_clk =3D { + .halt_reg =3D 0x1044, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x1044, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x1044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_aud_dma_mem_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_aud_dma_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_bus_clk =3D { + .halt_reg =3D 0x1020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x1020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_bus_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_bus_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_ext_mclka_out_clk =3D { + .halt_reg =3D 0x1254, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1254, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_ext_mclka_out_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_ext_mclka_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_ext_mclkb_out_clk =3D { + .halt_reg =3D 0x1274, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1274, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_ext_mclkb_out_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_ext_mclkb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_im_sleep_clk =3D { + .halt_reg =3D 0x12cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_im_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_lpaif_pcmoe_clk =3D { + .halt_reg =3D 0x12c4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12c4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_lpaif_pcmoe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_lpaif_pcmoe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_rx_mclk_2x_clk =3D { + .halt_reg =3D 0x1298, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1298, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_rx_mclk_2x_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_rx_mclk_clk =3D { + .halt_reg =3D 0x12a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_rx_mclk_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_sampling_clk =3D { + .halt_reg =3D 0x1000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_sampling_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_tx_mclk_2x_clk =3D { + .halt_reg =3D 0x1294, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x1294, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_tx_mclk_2x_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_tx_mclk_rcg_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch audio_core_cc_tx_mclk_clk =3D { + .halt_reg =3D 0x12a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x12a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "audio_core_cc_tx_mclk_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &audio_core_cc_cdiv_tx_mclk_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_hw *audio_core_cc_shikra_hws[] =3D { + [AUDIO_CORE_CC_DIG_PLL_OUT_AUX] =3D &audio_core_cc_dig_pll_out_aux.hw, + [AUDIO_CORE_CC_DIG_PLL_OUT_AUX2] =3D &audio_core_cc_dig_pll_out_aux2.hw, +}; + +static struct clk_regmap *audio_core_cc_shikra_clocks[] =3D { + [AUDIO_CORE_CC_AIF_IF0_CLK_SRC] =3D &audio_core_cc_aif_if0_clk_src.clkr, + [AUDIO_CORE_CC_AIF_IF0_EBIT_CLK] =3D &audio_core_cc_aif_if0_ebit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF0_IBIT_CLK] =3D &audio_core_cc_aif_if0_ibit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF1_CLK_SRC] =3D &audio_core_cc_aif_if1_clk_src.clkr, + [AUDIO_CORE_CC_AIF_IF1_EBIT_CLK] =3D &audio_core_cc_aif_if1_ebit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF1_IBIT_CLK] =3D &audio_core_cc_aif_if1_ibit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF2_CLK_SRC] =3D &audio_core_cc_aif_if2_clk_src.clkr, + [AUDIO_CORE_CC_AIF_IF2_EBIT_CLK] =3D &audio_core_cc_aif_if2_ebit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF2_IBIT_CLK] =3D &audio_core_cc_aif_if2_ibit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF3_CLK_SRC] =3D &audio_core_cc_aif_if3_clk_src.clkr, + [AUDIO_CORE_CC_AIF_IF3_EBIT_CLK] =3D &audio_core_cc_aif_if3_ebit_clk.clkr, + [AUDIO_CORE_CC_AIF_IF3_IBIT_CLK] =3D &audio_core_cc_aif_if3_ibit_clk.clkr, + [AUDIO_CORE_CC_AUD_DMA_CLK] =3D &audio_core_cc_aud_dma_clk.clkr, + [AUDIO_CORE_CC_AUD_DMA_CLK_SRC] =3D &audio_core_cc_aud_dma_clk_src.clkr, + [AUDIO_CORE_CC_AUD_DMA_MEM_CLK] =3D &audio_core_cc_aud_dma_mem_clk.clkr, + [AUDIO_CORE_CC_BUS_CLK] =3D &audio_core_cc_bus_clk.clkr, + [AUDIO_CORE_CC_BUS_CLK_SRC] =3D &audio_core_cc_bus_clk_src.clkr, + [AUDIO_CORE_CC_CDIV_TX_MCLK_DIV_CLK_SRC] =3D &audio_core_cc_cdiv_tx_mclk_= div_clk_src.clkr, + [AUDIO_CORE_CC_DIG_PLL] =3D &audio_core_cc_dig_pll.clkr, + [AUDIO_CORE_CC_EXT_MCLKA_CLK_SRC] =3D &audio_core_cc_ext_mclka_clk_src.cl= kr, + [AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK] =3D &audio_core_cc_ext_mclka_out_clk.cl= kr, + [AUDIO_CORE_CC_EXT_MCLKB_CLK_SRC] =3D &audio_core_cc_ext_mclkb_clk_src.cl= kr, + [AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK] =3D &audio_core_cc_ext_mclkb_out_clk.cl= kr, + [AUDIO_CORE_CC_IM_SLEEP_CLK] =3D &audio_core_cc_im_sleep_clk.clkr, + [AUDIO_CORE_CC_LPAIF_PCMOE_CLK] =3D &audio_core_cc_lpaif_pcmoe_clk.clkr, + [AUDIO_CORE_CC_LPAIF_PCMOE_CLK_SRC] =3D &audio_core_cc_lpaif_pcmoe_clk_sr= c.clkr, + [AUDIO_CORE_CC_RX_MCLK_2X_CLK] =3D &audio_core_cc_rx_mclk_2x_clk.clkr, + [AUDIO_CORE_CC_RX_MCLK_CLK] =3D &audio_core_cc_rx_mclk_clk.clkr, + [AUDIO_CORE_CC_SAMPLING_CLK] =3D &audio_core_cc_sampling_clk.clkr, + [AUDIO_CORE_CC_TX_MCLK_2X_CLK] =3D &audio_core_cc_tx_mclk_2x_clk.clkr, + [AUDIO_CORE_CC_TX_MCLK_CLK] =3D &audio_core_cc_tx_mclk_clk.clkr, + [AUDIO_CORE_CC_TX_MCLK_RCG_CLK_SRC] =3D &audio_core_cc_tx_mclk_rcg_clk_sr= c.clkr, +}; + +static struct clk_alpha_pll *audio_core_cc_shikra_plls[] =3D { + &audio_core_cc_dig_pll, +}; + +static const struct qcom_cc_driver_data audio_core_cc_shikra_driver_data = =3D { + .alpha_plls =3D audio_core_cc_shikra_plls, + .num_alpha_plls =3D ARRAY_SIZE(audio_core_cc_shikra_plls), +}; + +static const struct regmap_config audio_core_cc_shikra_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x305c, + .fast_io =3D true, +}; + +static const struct qcom_reset_map audio_core_csr_shikra_resets[] =3D { + [AUDIO_CORE_CSR_RX_SWR_CGCR] =3D { 0x1c, 1 }, + [AUDIO_CORE_CSR_TX_SWR_CGCR] =3D { 0x30, 1 }, +}; + +static const struct regmap_config audio_core_csr_shikra_regmap_config =3D { + .name =3D "audio_core_cc_shikra_reset", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0x34, +}; + +static const struct qcom_cc_desc audio_core_csr_shikra_desc =3D { + .config =3D &audio_core_csr_shikra_regmap_config, + .resets =3D audio_core_csr_shikra_resets, + .num_resets =3D ARRAY_SIZE(audio_core_csr_shikra_resets), +}; + +static const struct qcom_cc_desc audio_core_cc_shikra_desc =3D { + .config =3D &audio_core_cc_shikra_regmap_config, + .clk_hws =3D audio_core_cc_shikra_hws, + .num_clk_hws =3D ARRAY_SIZE(audio_core_cc_shikra_hws), + .clks =3D audio_core_cc_shikra_clocks, + .num_clks =3D ARRAY_SIZE(audio_core_cc_shikra_clocks), + .driver_data =3D &audio_core_cc_shikra_driver_data, +}; + +static const struct of_device_id audio_core_cc_shikra_match_table[] =3D { + { .compatible =3D "qcom,shikra-audiocorecc", .data =3D &audio_core_cc_shi= kra_desc }, + { .compatible =3D "qcom,shikra-audiocore-csr", .data =3D &audio_core_csr_= shikra_desc }, + { } +}; +MODULE_DEVICE_TABLE(of, audio_core_cc_shikra_match_table); + +static int audio_core_cc_shikra_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc; + + desc =3D device_get_match_data(&pdev->dev); + + return qcom_cc_probe(pdev, desc); +} + +static struct platform_driver audio_core_cc_shikra_driver =3D { + .probe =3D audio_core_cc_shikra_probe, + .driver =3D { + .name =3D "audiocorecc-shikra", + .of_match_table =3D audio_core_cc_shikra_match_table, + }, +}; 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Thu, 23 Jul 2026 08:46:28 -0700 (PDT) X-Received: by 2002:a17:903:3c4d:b0:2c7:f5c6:c4a6 with SMTP id d9443c01a7336-2cfa947647fmr36538195ad.7.1784821588047; Thu, 23 Jul 2026 08:46:28 -0700 (PDT) Received: from hu-imrashai-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf8efd7157sm36242625ad.18.2026.07.23.08.46.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 08:46:27 -0700 (PDT) From: Imran Shaik Date: Thu, 23 Jul 2026 21:15:53 +0530 Subject: [PATCH v3 4/4] arm64: dts: qcom: shikra: Add support for AudioCoreCC and AudioCoreCSR nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-shikra-audiocorecc-v3-4-90b878ae0d4e@oss.qualcomm.com> References: <20260723-shikra-audiocorecc-v3-0-90b878ae0d4e@oss.qualcomm.com> In-Reply-To: <20260723-shikra-audiocorecc-v3-0-90b878ae0d4e@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Imran Shaik X-Mailer: b4 0.14.2 X-Proofpoint-ORIG-GUID: 7ldg0hey7LAy9wk8rKaPFg2dBSYcH1Yt X-Proofpoint-GUID: 7ldg0hey7LAy9wk8rKaPFg2dBSYcH1Yt X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIzMDE1NSBTYWx0ZWRfX7IzF6YNTG6ea FK6+Fv53P9iwSCmFvdnKicQDuci69ZiWSG/7YGPfqXKpWuTAyZ9TvbsukeU39O7sHJlusIICLgZ 7tzHuQ41Qk/5km34SASdPtm4OanihcY= X-Authority-Analysis: v=2.4 cv=L/ItheT8 c=1 sm=1 tr=0 ts=6a623755 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=3-fpjux48RbdSrvt_gcA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIzMDE1NSBTYWx0ZWRfXzyiA65jqh8/C m+4pCVk6YIxKUfug5tXBlI+4fiv6JYya41FX6MKmS4W3jyCnndNFezsI8ep2V5x2Vg1KB37PFIB +E906U7uJf70UrDxZZdk4LPHA2wFCYaQKyC7HvHRn0tNLZB6LST0iEC6Ra9etBRvHffteEH3I0e coQUNjn8gTGoN/iVxU1J1yACYphF10GSdEwPTlLFaLxC5JPvyTjW7xxeho7JGe4rEiR6Mchinug Kwx8g1orlb4eLqkELj7mBn2ggDhxQjkGSCLif+6+U1nXeim76Z4MZSAaO+FTSh0XxQE1hMLo0qm RdKIsrw1JONnzb0Z43gVXXNvZVY4cofvxY1GR20IShLeKwc2RXb2jiei66aZmZhJRzKOKUfI21X k4RTgICcedx7wbFSwfcuJjNbqlXqEJWPAvqR7gCqTwYD1oqsObd+drRmLS5GJXWouD0GMrvC6xy iMHVYpEIW3gHLRsecZw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-23_04,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 adultscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 bulkscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607230155 Add support for Audio Core Clock Controller (AudioCoreCC) and Audio Core CSR nodes on Qualcomm Shikra SoC. The Audio Core Clocks and Resets support differs across Shikra variants based on Audio subsystem enablement as follows: - CQM variant: The QAIF driver runs on HLOS, hence both clocks and resets are required to be supported on HLOS. - CQS variant: The QAIF driver runs on the Modem, and required clocks are handled on Modem, so from HLOS only resets are needed. - IQS variant: no soundwire codes, hence no clocks/resets are needed. Signed-off-by: Imran Shaik --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 4 ++++ arch/arm64/boot/dts/qcom/shikra.dtsi | 17 +++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/= dts/qcom/shikra-cqm-evk.dts index 0a52ab9b7a4c34d371f5ac23efe59d1c9d2723f4..0883c480bfbc80d7bead966b9ba= 932dee8a77bbf 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -23,6 +23,10 @@ chosen { }; }; =20 +&audiocorecc { + status =3D "okay"; +}; + &sdhc_1 { vmmc-supply =3D <&pm4125_l20>; vqmmc-supply =3D <&pm4125_l14>; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index 4e5bc9e17c8ed8914733ac9fdc9b69128b40216e..b744534572d63349c4274ffbe5c= acbb8fdb4197d 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -640,6 +641,22 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, }; }; =20 + audiocorecc: clock-controller@a0a0000 { + compatible =3D "qcom,shikra-audiocorecc"; + reg =3D <0x0 0x0a0a0000 0x0 0x10000>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <0>; + #clock-cells =3D <1>; + status =3D "reserved"; /* Owned by Modem firmware */ + }; + + audiocore_csr: reset-controller@a0b4000 { + compatible =3D "qcom,shikra-audiocore-csr"; + reg =3D <0x0 0x0a0b4000 0x0 0x1000>; + #reset-cells =3D <1>; + }; + sram@c11e000 { compatible =3D "qcom,shikra-imem", "mmio-sram"; reg =3D <0x0 0x0c11e000 0x0 0x1000>; --=20 2.34.1