From nobody Fri Jul 24 05:21:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C75A47DD4D; Thu, 23 Jul 2026 13:24:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784813041; cv=none; b=qElCaiLjUAWTwEdRvG8VVd4ZOH867u85brTdjwN96uMwnjhatQjFyd3dvDX1Rzq/lFVm+1aIiWkw0nl5fvDaDl9ojpi+z7oHjDLIXtPBKY7SS/kK2l1ZkkOraj1wC3Gje28bbm5FgpBgIW7JmPvxNLlWCOHPi8cgfguPNKBzjbc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784813041; c=relaxed/simple; bh=3rCc+lsHFX2bNhHzFlHVmccE0pVnx+cTVMWetQmUK6g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nneJSj6iVgVXiHV/804rKJ1cwu7a+rvluH82638PvkfDQB2gjGBgJ7BSm7VQ+8eEC6zW9qMalnz40Hl+baOib1vsM/oK4n5kF+xRHZ3QBiijxhqGNWR/TyLAlMJwKEMYigpQx+GCMLxncZPIgfUboWW1tBzmhVH2ySjSKJzLuKI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lyC8y6PU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lyC8y6PU" Received: by smtp.kernel.org (Postfix) with ESMTPS id B0EF2C2BCC7; Thu, 23 Jul 2026 13:24:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784813040; bh=3rCc+lsHFX2bNhHzFlHVmccE0pVnx+cTVMWetQmUK6g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lyC8y6PUtcabPlvB4rHJgaKrAMOaKhJhZzHY/BPI9z9r9IKjhHRDqt9sElvF4RieE mChP3a2Hv26MiGCJQJnoscfx19pBQWrA4b7SSFpoVrb4W8t3kHFGfER9LeWRvxFS5W 6t3fS3vC1Nf5V69cHNS2jdg9hLaBO0kaHkT6K0/d8TYuyGV9QNjOSDu0eP0kPN5Uuu NIkVoLB7t8lDgfI6R59StUe0XLvT7Hlu5pzOzKGZUHO1g9IRxzZbJYA9+/BsSxCKS9 5QFOx5U2CuxAgk/16CbU+qzn7M/YvDpWFFt5Vz9YopfB15tLNh46wUGNxlDzIx2Oo7 0ZjdziNuXtrAw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90CE8C531CB; Thu, 23 Jul 2026 13:24:00 +0000 (UTC) From: Alexandre Hamamdjian via B4 Relay Date: Thu, 23 Jul 2026 20:23:59 +0700 Subject: [PATCH v5 1/3] dt-bindings: arm: qcom: document the Ayaneo Pocket DS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-pocketds-v5-1-74508388c716@gmail.com> References: <20260723-pocketds-v5-0-74508388c716@gmail.com> In-Reply-To: <20260723-pocketds-v5-0-74508388c716@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandre Hamamdjian , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784813038; l=906; i=azkali.limited@gmail.com; s=20260510; h=from:subject:message-id; bh=oBrsCM7jjcemh5kkcBaIFnGWn5xiruOoVHMMuBw01l8=; b=4pfB4cCyIBA36TYYi1iLeL51Kn2MxxgcIs9mcOrlLiIpJLSsjOx/ncv6psRSxhE8Sx5SOmOyj AJVpL+3LzZgDZca24kyR32bPVzZ6nZXuTY5MtTAGhjOftcifQxsgRLq X-Developer-Key: i=azkali.limited@gmail.com; a=ed25519; pk=I0Z0IdCdQJqNGX+FQUnXhrHg950u3cM6Xzz3YT6JOyQ= X-Endpoint-Received: by B4 Relay for azkali.limited@gmail.com/20260510 with auth_id=774 X-Original-From: Alexandre Hamamdjian Reply-To: azkali.limited@gmail.com From: Alexandre Hamamdjian Document the Qualcomm QCS8550 based Ayaneo Pocket DS gaming console. Signed-off-by: Alexandre Hamamdjian Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 2741c07e9f41..b5dad29a8606 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1107,6 +1107,12 @@ properties: - const: qcom,qcs8550 - const: qcom,sm8550 =20 + - items: + - enum: + - ayaneo,pocket-ds + - const: qcom,qcs8550 + - const: qcom,sm8550 + - items: - enum: - ayaneo,pocket-s2 --=20 2.55.0 From nobody Fri Jul 24 05:21:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C64147987F; Thu, 23 Jul 2026 13:24:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784813041; cv=none; b=ToqhwfqB6+xHgbFQSH/5FwSQFdOSZQujloB1JNiVD9R0mVXRrM5J355DBKeW3je6bq+7uPVgBF3RabhoZTwkSlMTE8QQb648L1UcucwTOKnYnezh1nicbQbPv0r4ZYfcMZczVmhzS2OQglW+dpm9PCSg5qGcG8SxOkUutbpfzwA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784813041; c=relaxed/simple; bh=pFrNQ+vXwn2SVn0jpMivPcgXgNhBFkuVJxH9gKNMncQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=G5JP8JBgf/pvCYmqTWRspkh4y+6GGDsrAFgCGEP30uUMDvRn5sxDf7KleJVIlH0xSrNza74I5YnbQK4xp1FO970ajGSkxepvwME3QC0tuRhuUWTxzVVhu1XrRA+gsaO7ApmmU3UNuconhJ3A6egAGW5FOJRWpaJ4Lxsa1eovh1k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SFKpYkYG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SFKpYkYG" Received: by smtp.kernel.org (Postfix) with ESMTPS id C0E39C2BCFA; Thu, 23 Jul 2026 13:24:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784813040; bh=pFrNQ+vXwn2SVn0jpMivPcgXgNhBFkuVJxH9gKNMncQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SFKpYkYGMaihSknIOT7v8cRkyHCCHycPHbIt6jhN0mEu3+SxY8/F7Qbd42GCGyUrA wv00Z4K/RjZfna9f9jIZKta7BOTrfeCYsMOmMChguV2HrUvtR4JwzZQu0cMU1uID27 b+nYttheZacoFBL5S0qDfo2Gb8W0J3WRhs70Lm/TaB4hoBR5iSO5waaVD0qMBfXeg1 1m5uuKSgPyfMfQP1X6Id2bfNtD/+5dQ7EJGM5x61gl3LaRueIAjjlfVEKGCFxX9yN6 Y4htzUXPbv2bFd3RbI6X5/gAj8K6T69lb2D81O5IcxWxTXOI1G4+y7Z8mcwHTKsuWo 0rHkwbjRD/8+g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2B80C531D1; Thu, 23 Jul 2026 13:24:00 +0000 (UTC) From: Alexandre Hamamdjian via B4 Relay Date: Thu, 23 Jul 2026 20:24:00 +0700 Subject: [PATCH v5 2/3] arm64: dts: qcom: sm8550: add UART11 node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-pocketds-v5-2-74508388c716@gmail.com> References: <20260723-pocketds-v5-0-74508388c716@gmail.com> In-Reply-To: <20260723-pocketds-v5-0-74508388c716@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandre Hamamdjian , Konrad Dybcio X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784813038; l=2426; i=azkali.limited@gmail.com; s=20260510; h=from:subject:message-id; bh=UsTWpRDwbdpHTBDdFtzyoL0z7QNs2yHTYuBRh3JZWP0=; b=yLFGt/SwyhDRjBpgFNCTH2PiDpQlgEc/SbBJLwml8X1cifJUvYba8vpc4F4xm6QNC0rHkmekv 1/WQ8lsAi2bB5wqW/tKmoWXId0ufhrya9EPRv12SMJgnmER36laKc+J X-Developer-Key: i=azkali.limited@gmail.com; a=ed25519; pk=I0Z0IdCdQJqNGX+FQUnXhrHg950u3cM6Xzz3YT6JOyQ= X-Endpoint-Received: by B4 Relay for azkali.limited@gmail.com/20260510 with auth_id=774 X-Original-From: Alexandre Hamamdjian Reply-To: azkali.limited@gmail.com From: Alexandre Hamamdjian Add the QUPv3_2 SE3 UART (UART11) controller node and its default pinctrl state to sm8550.dtsi, so boards with a peripheral wired to that serial engine can enable it through &uart11. The serial engine at 0x88c000 is already described as i2c11 and spi11, so the UART node takes the same qup_opp_table_120mhz they use: it is the same block behind the same GCC_QUPV3_WRAP2_S3_CLK, and its core clock tops out at 120 MHz rather than the 100 MHz the other table allows. TX and RX are biased pull-up, matching qup_uart14_default, so the lines idle high on boards that do not fit external pull-ups. Signed-off-by: Alexandre Hamamdjian Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 912525e9bca6..165c0248da53 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1084,6 +1084,24 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, status =3D "disabled"; }; =20 + uart11: serial@88c000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0 0x0088c000 0 0x4000>; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_uart11_default>; + interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", "qup-config"; + operating-points-v2 =3D <&qup_opp_table_120mhz>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + status =3D "disabled"; + }; + i2c12: i2c@890000 { compatible =3D "qcom,geni-i2c"; reg =3D <0 0x00890000 0 0x4000>; @@ -5102,6 +5120,14 @@ qup_uart7_default: qup-uart7-default-state { bias-disable; }; =20 + qup_uart11_default: qup-uart11-default-state { + /* TX, RX */ + pins =3D "gpio70", "gpio71"; + function =3D "qup2_se3"; + drive-strength =3D <2>; + bias-pull-up; + }; + qup_uart14_default: qup-uart14-default-state { /* TX, RX */ pins =3D "gpio78", "gpio79"; --=20 2.55.0 From nobody Fri Jul 24 05:21:42 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C5204746D5; Thu, 23 Jul 2026 13:24:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-pocketds-v5-3-74508388c716@gmail.com> References: <20260723-pocketds-v5-0-74508388c716@gmail.com> In-Reply-To: <20260723-pocketds-v5-0-74508388c716@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandre Hamamdjian , Teguh Sobirin X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784813038; l=42245; i=azkali.limited@gmail.com; s=20260510; h=from:subject:message-id; bh=KykgWbPKSsnxBA4pNz4Div3LBocABlgjRRy6FA5meck=; b=GyN37KcGrs1xDhvcDFqd7UFoou0QT8q9/ejDjduqw9E5G78oCB9/JDgaux+GitQw8tbQmfSV6 qayw6clNj9iDHv4nC473llxf+JLsuikFnkM3VHzCKvY4wT1C3O5ZHk6 X-Developer-Key: i=azkali.limited@gmail.com; a=ed25519; pk=I0Z0IdCdQJqNGX+FQUnXhrHg950u3cM6Xzz3YT6JOyQ= X-Endpoint-Received: by B4 Relay for azkali.limited@gmail.com/20260510 with auth_id=774 X-Original-From: Alexandre Hamamdjian Reply-To: azkali.limited@gmail.com From: Teguh Sobirin Add initial Device Tree for the Ayaneo Pocket DS gaming console based on the Qualcomm QCS8550 platform. The design is similar to a phone without the modem: game controls are exposed through a Renesas uPD720201 PCIe USB 3.0 host controller hung off PCIe1, while a dedicated gamepad MCU is reached over UART11. DisplayPort is muxed over the USB-C connector with all four lanes wired, with an ON Semi NB7VPQ904M redriver handling SS and SBU AUX muxing. Only the basics are wired up at this stage (boot to console, core peripherals, USB-C and DP, microSD, WiFi/BT, gaming controls); DSI panel support will follow in a later submission once the panel bindings are reviewed. The FT5426 touchscreen on i2c4 clock-stretches past the GENI controller's timeout at 400 kHz. The qcom-geni-i2c controller implements no i2c_bus_recovery, so a stuck SCL can only be cleared by an FSM reset, which is itself the operation that times out. i2c4 is therefore run at 100 kHz, well within the FT5426's clock-stretch tolerance and with ample bandwidth for its sub-256-byte reports. PCIe0 hosts the WCN7850 WiFi and is pinned to Gen2 (max-link-speed =3D <2>), the link speed validated on this board. sdhc_2 sets qcom,dll-config to 0x0007442c, the DLL_CONFIG value the QCS8550 vendor device tree ships for this SDCC2 instance, in place of the generic sm8550 default of 0x0007642c; the vendor value is the one validated for SDR104 operation on this board. The board uses the &thermal_cpuss[0-3], &thermal_cpu7_top and &thermal_gpuss[0-7] labels to extend the SoC thermal zones with an active trip point and a cooling map driving the on-board PWM fan; those labels are added to sm8550.dtsi as part of this change so the board has a real user from the same patch. Signed-off-by: Teguh Sobirin Co-developed-by: Alexandre Hamamdjian Signed-off-by: Alexandre Hamamdjian --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/qcs8550-ayaneo-pocket-ds.dts | 1618 ++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 +- 3 files changed, 1632 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index cc42829f92eb..81abb05529ec 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -185,6 +185,7 @@ qcs8300-ride-el2-dtbs :=3D qcs8300-ride.dtb monaco-el2.= dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8300-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-ayaneo-pocket-ds.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride-r3.dtb =20 diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocket-ds.dts b/arch/a= rm64/boot/dts/qcom/qcs8550-ayaneo-pocket-ds.dts new file mode 100644 index 000000000000..9057af176315 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocket-ds.dts @@ -0,0 +1,1618 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Teguh Sobirin. + * Copyright (c) 2025, ROCKNIX (https://github.com/ROCKNIX) + */ + +/dts-v1/; + +#include +#include +#include +#include "qcs8550.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +/delete-node/ &aop_image_mem; +/delete-node/ &aop_config_mem; +/delete-node/ &camera_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &mpss_dsm_mem; +/delete-node/ &mpss_mem; +/delete-node/ &q6_mpss_dtb_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &q6_cdsp_dtb_mem; + +/ { + model =3D "AYANEO Pocket DS"; + compatible =3D "ayaneo,pocket-ds", "qcom,qcs8550", "qcom,sm8550"; + + aliases { + serial0 =3D &uart7; + serial1 =3D &uart14; + hsuart0 =3D &uart11; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&volume_up_n>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + }; + }; + + pmic-glink { + compatible =3D "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + orientation-gpios =3D <&tlmm 11 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible =3D "usb-c-connector"; + + reg =3D <0>; + + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint =3D <&redriver_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint =3D <&redriver_sbu>; + }; + }; + }; + }; + }; + + pwm_fan: pwm-fan { + compatible =3D "pwm-fan"; + + pinctrl-0 =3D <&fan_pwm_active>, <&fan_int>; + pinctrl-1 =3D <&fan_pwm_sleep>, <&fan_int>; + pinctrl-names =3D "default", "sleep"; + + fan-supply =3D <&vdd_fan_5v0>; + pwms =3D <&pm8550_pwm 3 40000>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <64 IRQ_TYPE_EDGE_FALLING>; + + #cooling-cells =3D <2>; + cooling-levels =3D <0 30 45 60 70 90 120 150>; + }; + + reserved-memory { + hyp_mem: hyp-region@80000000 { + reg =3D <0 0x80000000 0 0xa00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-region@80a00000 { + reg =3D <0 0x80a00000 0 0x400000>; + no-map; + }; + + hyp_tags_mem: hyp-tags-region@80e00000 { + reg =3D <0 0x80e00000 0 0x3d0000>; + no-map; + }; + + xbl_sc_mem: xbl-sc-region@d8100000 { + reg =3D <0 0xd8100000 0 0x40000>; + no-map; + }; + + hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { + reg =3D <0 0x811d0000 0 0x30000>; + no-map; + }; + + xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { + reg =3D <0 0x81a00000 0 0x260000>; + no-map; + }; + + aop_config_merged_mem: aop-config-merged-region@81c80000 { + reg =3D <0 0x81c80000 0 0x74000>; + no-map; + }; + + chipinfo_mem: chipinfo-region@81cf4000 { + reg =3D <0 0x81cf4000 0 0x1000>; + no-map; + }; + + global_sync_mem: global-sync-region@82600000 { + reg =3D <0 0x82600000 0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat-region@82700000 { + reg =3D <0 0x82700000 0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw-region@d8140000 { + reg =3D <0 0xd8140000 0 0x1c0000>; + no-map; + }; + + qtee_mem: qtee-region@d8300000 { + reg =3D <0 0xd8300000 0 0x500000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf-region@e6440000 { + reg =3D <0 0xe6440000 0 0x2dd000>; + no-map; + }; + + hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { + reg =3D <0 0xff700000 0 0x100000>; + no-map; + }; + + llcc_lpi_mem: llcc-lpi-region@ff800000 { + reg =3D <0 0xff800000 0 0x600000>; + no-map; + }; + + hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { + reg =3D <0 0xfce00000 0 0x2900000>; + no-map; + }; + + splash_region: splash-region@b8000000 { + reg =3D <0x0 0xb8000000 0x0 0x2b00000>; + no-map; + }; + }; + + sound { + compatible =3D "qcom,sm8550-sndcard", "qcom,sm8450-sndcard"; + model =3D "SM8550-APS"; + + audio-routing =3D "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT"; + + wsa-dai-link { + link-name =3D "WSA Playback"; + + cpu { + sound-dai =3D <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai =3D <&spk_amp_l>, + <&spk_amp_r>, + <&swr0 0>, + <&lpass_wsamacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + va-dai-link { + link-name =3D "VA Capture"; + + cpu { + sound-dai =3D <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai =3D <&lpass_vamacro 0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + }; + + tca6424_vcc: tca6424-vcc-regulator { + compatible =3D "regulator-fixed"; + + regulator-name =3D "tca6424_vcc"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpios =3D <&tlmm 168 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + upd720201_avdd33_reg: upd720201-avdd33-regulator { + compatible =3D "regulator-fixed"; + + regulator-name =3D "upd720201_avdd33"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpios =3D <&tlmm 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vph_pwr>; + + pinctrl-0 =3D <&upd720201_avdd33>; + pinctrl-names =3D "default"; + }; + + upd720201_vdd10_reg: upd720201-vdd10-regulator { + compatible =3D "regulator-fixed"; + + regulator-name =3D "upd720201_vdd10"; + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <1050000>; + + gpios =3D <&tlmm 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vph_pwr>; + + pinctrl-0 =3D <&upd720201_vdd10>; + pinctrl-names =3D "default"; + }; + + upd720201_vdd33_reg: upd720201-vdd33-regulator { + compatible =3D "regulator-fixed"; + + regulator-name =3D "upd720201_vdd33"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpios =3D <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vph_pwr>; + + pinctrl-0 =3D <&upd720201_vdd33>; + pinctrl-names =3D "default"; + }; + + vdd_fan_5v0: vdd-fan-5v0-regulator { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vdd_fan_5v0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + + gpios =3D <&tlmm 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&fan_pwr_active>; + pinctrl-names =3D "default"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ts: vdd-ts-regulator { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vdd_ts_en"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpios =3D <&tca6408 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + wcn7850-pmu { + compatible =3D "qcom,wcn7850-pmu"; + + pinctrl-0 =3D <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>; + pinctrl-names =3D "default"; + + wlan-enable-gpios =3D <&tlmm 80 GPIO_ACTIVE_HIGH>; + bt-enable-gpios =3D <&tlmm 81 GPIO_ACTIVE_HIGH>; + + vdd-supply =3D <&vreg_s5g_0p85>; + vddio-supply =3D <&vreg_l15b_1p8>; + vddaon-supply =3D <&vreg_s2g_0p85>; + vdddig-supply =3D <&vreg_s4e_0p95>; + vddrfa1p2-supply =3D <&vreg_s4g_1p25>; + vddrfa1p8-supply =3D <&vreg_s6g_1p86>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name =3D "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name =3D "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name =3D "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name =3D "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name =3D "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name =3D "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name =3D "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name =3D "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name =3D "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name =3D "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l1-l4-l10-supply =3D <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob1>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l11-supply =3D <&vreg_s4g_1p25>; + vdd-l12-supply =3D <&vreg_s6g_1p86>; + vdd-l15-supply =3D <&vreg_s6g_1p86>; + vdd-l17-supply =3D <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2720000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name =3D "vreg_l7b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name =3D "vreg_l8b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name =3D "vreg_l10b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name =3D "vreg_l11b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name =3D "vreg_l12b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name =3D "vreg_l14b_3p2"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name =3D "vreg_l16b_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-l1-supply =3D <&vreg_s4g_1p25>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + + vreg_l3c_0p9: ldo3 { + regulator-name =3D "vreg_l3c_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + + vreg_l1d_0p88: ldo1 { + regulator-name =3D "vreg_l1d_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + + vreg_s4e_0p95: smps4 { + regulator-name =3D "vreg_s4e_0p95"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <984000>; + regulator-initial-mode =3D ; + }; + + vreg_s5e_1p08: smps5 { + regulator-name =3D "vreg_s5e_1p08"; + regulator-min-microvolt =3D <1010000>; + regulator-max-microvolt =3D <1120000>; + regulator-initial-mode =3D ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name =3D "vreg_l1e_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name =3D "vreg_l2e_0p9"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name =3D "vreg_l3e_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "f"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + vdd-s4-supply =3D <&vph_pwr>; + + vreg_s4f_0p5: smps4 { + regulator-name =3D "vreg_s4f_0p5"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <700000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name =3D "vreg_l1f_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name =3D "vreg_l2f_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name =3D "vreg_l3f_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "g"; + + vdd-l1-supply =3D <&vreg_s4g_1p25>; + vdd-l2-supply =3D <&vreg_s4g_1p25>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + vreg_s1g_1p25: smps1 { + regulator-name =3D "vreg_s1g_1p25"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + }; + + vreg_s2g_0p85: smps2 { + regulator-name =3D "vreg_s2g_0p85"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + }; + + vreg_s3g_0p8: smps3 { + regulator-name =3D "vreg_s3g_0p8"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_s4g_1p25: smps4 { + regulator-name =3D "vreg_s4g_1p25"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + + vreg_s5g_0p85: smps5 { + regulator-name =3D "vreg_s5g_0p85"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_s6g_1p86: smps6 { + regulator-name =3D "vreg_s6g_1p86"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name =3D "vreg_l1g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name =3D "vreg_l3g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpi_dma2 { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/sm8550/a740_zap.mbn"; +}; + +&i2c0 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + tca6408: gpio@20 { + compatible =3D "ti,tca6408"; + reg =3D <0x20>; + + gpio-controller; + #gpio-cells =3D <2>; + + vcc-supply =3D <&tca6424_vcc>; + }; +}; + +&i2c2 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + touchscreen@5d { + compatible =3D "goodix,gt911"; + reg =3D <0x5d>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <39 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios =3D <&tlmm 38 GPIO_ACTIVE_HIGH>; + irq-gpios =3D <&tlmm 39 GPIO_ACTIVE_HIGH>; + + VDDIO-supply =3D <&vdd_ts>; + + pinctrl-0 =3D <&ts2_reset>, <&ts2_irq>; + pinctrl-names =3D "default"; + + touchscreen-size-x =3D <768>; + touchscreen-size-y =3D <1024>; + }; +}; + +&i2c4 { + clock-frequency =3D <100000>; + + status =3D "okay"; + + touchscreen: touchscreen@38 { + compatible =3D "focaltech,ft5426"; + reg =3D <0x38>; + + interrupt-parent =3D <&tlmm>; + interrupts =3D <25 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios =3D <&tlmm 24 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l14b_3p2>; + iovcc-supply =3D <&vreg_l12b_1p8>; + + pinctrl-0 =3D <&ts_int_default &ts_rst_default>; + pinctrl-1 =3D <&ts_int_sleep &ts_rst_sleep>; + pinctrl-names =3D "default", "sleep"; + + touchscreen-size-x =3D <1080>; + touchscreen-size-y =3D <1920>; + }; +}; + +&i2c_hub_2 { + status =3D "okay"; + + typec-retimer@1c { + compatible =3D "onnn,nb7vpq904m"; + reg =3D <0x1c>; + + vcc-supply =3D <&vreg_l15b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + redriver_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + redriver_ss_in: endpoint { + data-lanes =3D <3 2 1 0>; + remote-endpoint =3D <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + redriver_sbu: endpoint { + remote-endpoint =3D <&pmic_glink_sbu>; + }; + }; + }; + }; +}; + +&i2c_master_hub_0 { + status =3D "okay"; +}; + +&iris { + status =3D "okay"; +}; + +/* DMIC 01 23 */ +&lpass_vamacro { + pinctrl-0 =3D <&dmic01_default>, <&dmic23_default>; + pinctrl-names =3D "default"; + + vdd-micb-supply =3D <&vreg_l10b_1p8>; + + qcom,dmic-sample-rate =3D <4800000>; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + data-lanes =3D <0 1 2 3>; +}; + +&pcie0 { + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + + max-link-speed =3D <2>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1e_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&pcie1 { + wake-gpios =3D <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie1_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + pcie@0 { + /* Renesas =CE=BCPD720201 PCIe USB3.0 HOST CONTROLLER */ + usb-controller@0 { + compatible =3D "pci1912,0014"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + avdd33-supply =3D <&upd720201_avdd33_reg>; + vdd10-supply =3D <&upd720201_vdd10_reg>; + vdd33-supply =3D <&upd720201_vdd33_reg>; + + pinctrl-0 =3D <&gamepad_pwr_en>; + pinctrl-names =3D "default"; + }; + }; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l3c_0p9>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + vdda-qref-supply =3D <&vreg_l1e_0p88>; + + status =3D "okay"; +}; + +&pcieport0 { + wifi@0 { + compatible =3D "pci17cb,1107"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply =3D <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply =3D <&vreg_pmu_pcie_1p8>; + }; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&pm8550_gpios { + sdc2_card_det_n: sdc2-card-det-n-state { + pins =3D "gpio12"; + function =3D "normal"; + input-enable; + output-disable; + bias-pull-up; + power-source =3D <1>; + }; + + volume_up_n: volume-up-n-state { + pins =3D "gpio6"; + function =3D "normal"; + power-source =3D <1>; + bias-pull-up; + input-enable; + }; + + fan_pwm_active: fan-pwm-active-state { + pins =3D "gpio9"; + function =3D "func1"; + output-low; + bias-disable; + power-source =3D <0>; + qcom,drive-strength =3D <3>; /* PMIC_GPIO_STRENGTH_LOW */ + }; + + fan_pwm_sleep: fan-pwm-sleep-state { + pins =3D "gpio9"; + function =3D "normal"; + output-high; + bias-disable; + power-source =3D <0>; + qcom,drive-strength =3D <3>; /* PMIC_GPIO_STRENGTH_LOW */ + }; +}; + +&pm8550_pwm { + status =3D "okay"; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply =3D <&vreg_l15b_1p8>; + vdd3-supply =3D <&vreg_l5b_3p1>; +}; + +&pmk8550_gpios { + pmk8550_sleep_clk: sleep-clk-state { + pins =3D "gpio3"; + function =3D "func1"; + input-disable; + output-enable; + bias-disable; + power-source =3D <0>; + }; +}; + +&pmk8550_rtc { + nvmem-cells =3D <&rtc_offset>; + nvmem-cell-names =3D "offset"; +}; + +&pmk8550_sdam_2 { + rtc_offset: rtc-offset@bc { + reg =3D <0xbc 0x4>; + }; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sm8550/ayaneo/adsp.mbn", + "qcom/sm8550/ayaneo/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + /delete-property/ memory-region; +}; + +&remoteproc_mpss { + /delete-property/ memory-region; +}; + +&sdhc_2 { + cd-gpios =3D <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 =3D <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names =3D "default", "sleep"; + + vmmc-supply =3D <&vreg_l9b_2p9>; + vqmmc-supply =3D <&vreg_l8b_1p8>; + + no-sdio; + no-mmc; + + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; + + qcom,dll-config =3D <0x0007442c>; + + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32764>; +}; + +&swr0 { + status =3D "okay"; + + spk_amp_l: speaker@0,0 { + compatible =3D "sdw20217020400"; + reg =3D <0 0>; + + pinctrl-0 =3D <&spkr_1_sd_n_active>; + pinctrl-names =3D "default"; + + powerdown-gpios =3D <&tlmm 7 GPIO_ACTIVE_LOW>; + + vdd-1p8-supply =3D <&vreg_l10b_1p8>; + vdd-io-supply =3D <&vreg_l10b_1p8>; + + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrLeft"; + qcom,port-mapping =3D <1 2 3 7 10 13>; + }; + + spk_amp_r: speaker@0,1 { + compatible =3D "sdw20217020400"; + reg =3D <0 1>; + + pinctrl-0 =3D <&spkr_2_sd_n_active>; + pinctrl-names =3D "default"; + + powerdown-gpios =3D <&tlmm 12 GPIO_ACTIVE_LOW>; + + vdd-1p8-supply =3D <&vreg_l10b_1p8>; + vdd-io-supply =3D <&vreg_l10b_1p8>; + + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrRight"; + qcom,port-mapping =3D <4 5 6 7 11 13>; + }; +}; + +&thermal_cpu7_top { + trips { + cpu7_active: cpu7-active { + temperature =3D <50000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&cpu7_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_cpuss0 { + trips { + cpuss0_active: cpuss0-active { + temperature =3D <50000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&cpuss0_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_cpuss1 { + trips { + cpuss1_active: cpuss1-active { + temperature =3D <50000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&cpuss1_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_cpuss2 { + trips { + cpuss2_active: cpuss2-active { + temperature =3D <50000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&cpuss2_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_cpuss3 { + trips { + cpuss3_active: cpuss3-active { + temperature =3D <50000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&cpuss3_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_gpuss0 { + trips { + gpuss0_active: gpuss0-active { + temperature =3D <55000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss0_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_gpuss1 { + trips { + gpuss1_active: gpuss1-active { + temperature =3D <55000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss1_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_gpuss2 { + trips { + gpuss2_active: gpuss2-active { + temperature =3D <55000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss2_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_gpuss3 { + trips { + gpuss3_active: gpuss3-active { + temperature =3D <55000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss3_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_gpuss4 { + trips { + gpuss4_active: gpuss4-active { + temperature =3D <55000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss4_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_gpuss5 { + trips { + gpuss5_active: gpuss5-active { + temperature =3D <55000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss5_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_gpuss6 { + trips { + gpuss6_active: gpuss6-active { + temperature =3D <55000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss6_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&thermal_gpuss7 { + trips { + gpuss7_active: gpuss7-active { + temperature =3D <55000>; + hysteresis =3D <3000>; + type =3D "active"; + }; + }; + + cooling-maps { + map { + trip =3D <&gpuss7_active>; + cooling-device =3D <&pwm_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <32 4>; + + bt_default: bt-default-state { + bt-en-pins { + pins =3D "gpio81"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins =3D "gpio82"; + function =3D "gpio"; + bias-pull-down; + }; + }; + + fan_pwr_active: fan-pwr-active-state { + pins =3D "gpio31"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-low; + }; + + fan_int: fan-int-state { + pins =3D "gpio64"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + upd720201_avdd33: upd720201-avdd33-state { + pins =3D "gpio10"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + upd720201_vdd10: upd720201-vdd10-state { + pins =3D "gpio13"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + upd720201_vdd33: upd720201-vdd33-state { + pins =3D "gpio18"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + gamepad_pwr_en: gamepad-pwr-en-active-state { + pins =3D "gpio52"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + wlan_en: wlan-en-state { + pins =3D "gpio80"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; + + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins =3D "gpio7"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins =3D "gpio12"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + ts_rst_default: ts-rst-default-state { + pins =3D "gpio24"; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <8>; + }; + + ts_rst_sleep: ts-rst-sleep-state { + pins =3D "gpio24"; + function =3D "gpio"; + bias-pull-down; + drive-strength =3D <2>; + }; + + ts_int_default: ts-int-default-state { + pins =3D "gpio25"; + function =3D "gpio"; + bias-pull-up; + drive-strength =3D <8>; + }; + + ts_int_sleep: ts-int-sleep-state { + pins =3D "gpio25"; + function =3D "gpio"; + bias-pull-down; + drive-strength =3D <2>; + }; + + ts2_irq: ts2-irq-state { + pins =3D "gpio39"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + ts2_reset: ts2-reset-state { + pins =3D "gpio38"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; +}; + +&uart7 { + status =3D "okay"; +}; + +/* AYANEO Controller serial interface */ +&uart11 { + status =3D "okay"; +}; + +&uart14 { + status =3D "okay"; + + bluetooth { + compatible =3D "qcom,wcn7850-bt"; + + vddrfacmn-supply =3D <&vreg_pmu_rfa_cmn>; + vddaon-supply =3D <&vreg_pmu_aon_0p59>; + vddwlcx-supply =3D <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply =3D <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply =3D <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply =3D <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply =3D <&vreg_pmu_rfa_1p8>; + + max-speed =3D <3200000>; + }; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l1g_1p2>; + vccq-max-microamp =3D <1200000>; + vdd-hba-supply =3D <&vreg_l3g_1p2>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1d_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&usb_1 { + status =3D "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l1e_0p88>; + vdda12-supply =3D <&vreg_l3e_1p2>; + + phys =3D <&pm8550b_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3e_1p2>; + vdda-pll-supply =3D <&vreg_l3f_0p88>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint =3D <&redriver_ss_in>; +}; + +&xo_board { + clock-frequency =3D <76800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 165c0248da53..26797e9668f2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -5790,7 +5790,7 @@ reset-mon-config { }; }; =20 - cpuss0-thermal { + thermal_cpuss0: cpuss0-thermal { thermal-sensors =3D <&tsens0 1>; =20 trips { @@ -5808,7 +5808,7 @@ reset-mon-config { }; }; =20 - cpuss1-thermal { + thermal_cpuss1: cpuss1-thermal { thermal-sensors =3D <&tsens0 2>; =20 trips { @@ -5826,7 +5826,7 @@ reset-mon-config { }; }; =20 - cpuss2-thermal { + thermal_cpuss2: cpuss2-thermal { thermal-sensors =3D <&tsens0 3>; =20 trips { @@ -5844,7 +5844,7 @@ reset-mon-config { }; }; =20 - cpuss3-thermal { + thermal_cpuss3: cpuss3-thermal { thermal-sensors =3D <&tsens0 4>; =20 trips { @@ -6054,7 +6054,7 @@ cpu6_bottom_crit: cpu-critical { }; }; =20 - cpu7-top-thermal { + thermal_cpu7_top: cpu7-top-thermal { thermal-sensors =3D <&tsens0 13>; =20 trips { @@ -6562,7 +6562,7 @@ reset-mon-config { }; }; =20 - gpuss-0-thermal { + thermal_gpuss0: gpuss-0-thermal { polling-delay-passive =3D <10>; =20 thermal-sensors =3D <&tsens2 1>; @@ -6595,7 +6595,7 @@ trip-point2 { }; }; =20 - gpuss-1-thermal { + thermal_gpuss1: gpuss-1-thermal { polling-delay-passive =3D <10>; =20 thermal-sensors =3D <&tsens2 2>; @@ -6628,7 +6628,7 @@ trip-point2 { }; }; =20 - gpuss-2-thermal { + thermal_gpuss2: gpuss-2-thermal { polling-delay-passive =3D <10>; =20 thermal-sensors =3D <&tsens2 3>; @@ -6661,7 +6661,7 @@ trip-point2 { }; }; =20 - gpuss-3-thermal { + thermal_gpuss3: gpuss-3-thermal { polling-delay-passive =3D <10>; =20 thermal-sensors =3D <&tsens2 4>; @@ -6694,7 +6694,7 @@ trip-point2 { }; }; =20 - gpuss-4-thermal { + thermal_gpuss4: gpuss-4-thermal { polling-delay-passive =3D <10>; =20 thermal-sensors =3D <&tsens2 5>; @@ -6727,7 +6727,7 @@ trip-point2 { }; }; =20 - gpuss-5-thermal { + thermal_gpuss5: gpuss-5-thermal { polling-delay-passive =3D <10>; =20 thermal-sensors =3D <&tsens2 6>; @@ -6760,7 +6760,7 @@ trip-point2 { }; }; =20 - gpuss-6-thermal { + thermal_gpuss6: gpuss-6-thermal { polling-delay-passive =3D <10>; =20 thermal-sensors =3D <&tsens2 7>; @@ -6793,7 +6793,7 @@ trip-point2 { }; }; =20 - gpuss-7-thermal { + thermal_gpuss7: gpuss-7-thermal { polling-delay-passive =3D <10>; =20 thermal-sensors =3D <&tsens2 8>; --=20 2.55.0