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Acked-by: Rob Herring (Arm) Signed-off-by: William Bright --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 7b0d79ebf9bd..5c74da791c13 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -791,6 +791,8 @@ patternProperties: description: ILI Technology Corporation (ILITEK) "^imagis,.*": description: Imagis Technologies Co., Ltd. + "^imdt,.*": + description: IMD Technologies Ltd. "^img,.*": description: Imagination Technologies Ltd. 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[86.157.235.39]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957af914a9sm10799055e9.15.2026.07.23.11.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 11:18:17 -0700 (PDT) From: William Bright Date: Thu, 23 Jul 2026 19:18:08 +0100 Subject: [PATCH v5 2/4] dt-bindings: arm: qcom: Document IMDT QCS8550 SBC/SoM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-imdt-qcs8550-sbc-rfc-v5-2-2fb988854623@imd-tec.com> References: <20260723-imdt-qcs8550-sbc-rfc-v5-0-2fb988854623@imd-tec.com> In-Reply-To: <20260723-imdt-qcs8550-sbc-rfc-v5-0-2fb988854623@imd-tec.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, William Bright X-Mailer: b4 0.15.2 Document the IMDT QCS8550 SBC which consists of an IMDT QCS8550 SoM soldered onto an IMDT QCS8550 carrier board. Acked-by: Rob Herring (Arm) Signed-off-by: William Bright --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index f8c37096df46..8d01cfbef8f6 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1137,6 +1137,13 @@ properties: - sony,pdx234 - const: qcom,sm8550 =20 + - items: + - enum: + - imdt,qcs8550-sbc + - const: imdt,qcs8550-som + - const: qcom,qcs8550 + - const: qcom,sm8550 + - items: - enum: - qcom,qcs8550-aim300-aiot --=20 2.43.0 From nobody Fri Jul 24 04:55:14 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69D613BB12A for ; Thu, 23 Jul 2026 18:18:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[86.157.235.39]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957af914a9sm10799055e9.15.2026.07.23.11.18.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 11:18:18 -0700 (PDT) From: William Bright Date: Thu, 23 Jul 2026 19:18:09 +0100 Subject: [PATCH v5 3/4] arm64: dts: qcom: Add IMDT QCS8550 SoM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-imdt-qcs8550-sbc-rfc-v5-3-2fb988854623@imd-tec.com> References: <20260723-imdt-qcs8550-sbc-rfc-v5-0-2fb988854623@imd-tec.com> In-Reply-To: <20260723-imdt-qcs8550-sbc-rfc-v5-0-2fb988854623@imd-tec.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, William Bright X-Mailer: b4 0.15.2 The IMDT QCS8550 SoM is a System-on-Module from IMD Technologies Ltd built around the Qualcomm QCS8550 SoC. It is intended to be soldered onto a carrier board that supplies VPH_PWR and exposes the off-module peripherals. Add qcs8550-imdt-som.dtsi describing the SoM's PMICs (PM8550, PM8550VE, PM8550VS, PMK8550) and the apps_rsc PMIC outputs. Compared to other SM8550/QCS8550 boards, this SoM excludes the PM8550B charger PMIC. Assisted-by: Claude:claude-opus-4.7 Signed-off-by: William Bright --- arch/arm64/boot/dts/qcom/qcs8550-imdt-som.dtsi | 315 +++++++++++++++++++++= ++++ 1 file changed, 315 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-imdt-som.dtsi b/arch/arm64/bo= ot/dts/qcom/qcs8550-imdt-som.dtsi new file mode 100644 index 000000000000..3202632eef04 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-imdt-som.dtsi @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 IMD Technologies Ltd + */ + +#include +#include "qcs8550.dtsi" +#include "pm8550.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +&apps_rsc { + pm8550_rpmh_regulators: regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-l1-l4-l10-supply =3D <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob1>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l11-supply =3D <&vreg_s4g_1p25>; + vdd-l12-supply =3D <&vreg_s6g_1p86>; + vdd-l15-supply =3D <&vreg_s6g_1p86>; + vdd-l17-supply =3D <&vreg_bob2>; + + /* + * PMIC outputs whose testpoints lack capacitors are + * omitted to prevent accidental use: + * L1B_1P8, L4B_1P8, L6B_1P8, L7B_1P8, L8B_1P8, + * L13B_3P0, L14B_3P2. + * Other outputs are unused. + */ + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3296000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2720000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + pm8550vs_c_rpmh_regulators: regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-l1-supply =3D <&vreg_s4g_1p25>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + + vreg_l3c_0p9: ldo3 { + regulator-name =3D "vreg_l3c_0p9"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + pm8550vs_d_rpmh_regulators: regulators-2 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + + vreg_l1d_0p88: ldo1 { + regulator-name =3D "vreg_l1d_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + /* ldo2 supplies SM8550 VDD_LPI_MX */ + }; + + pm8550vs_e_rpmh_regulators: regulators-3 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + + vreg_s4e_0p95: smps4 { + regulator-name =3D "vreg_s4e_0p95"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <984000>; + regulator-initial-mode =3D ; + }; + + vreg_s5e_1p08: smps5 { + regulator-name =3D "vreg_s5e_1p08"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1120000>; + regulator-initial-mode =3D ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name =3D "vreg_l1e_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name =3D "vreg_l2e_0p9"; + regulator-min-microvolt =3D <904000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name =3D "vreg_l3e_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + pm8550ve_rpmh_regulators: regulators-4 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "f"; + + vdd-l1-supply =3D <&vreg_s4e_0p95>; + vdd-l2-supply =3D <&vreg_s4e_0p95>; + vdd-l3-supply =3D <&vreg_s4e_0p95>; + + vreg_s4f_0p5: smps4 { + regulator-name =3D "vreg_s4f_0p5"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <700000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name =3D "vreg_l1f_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name =3D "vreg_l2f_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name =3D "vreg_l3f_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + pm8550vs_g_rpmh_regulators: regulators-5 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id =3D "g"; + + vdd-l1-supply =3D <&vreg_s4g_1p25>; + vdd-l2-supply =3D <&vreg_s4g_1p25>; + vdd-l3-supply =3D <&vreg_s4g_1p25>; + + vreg_s1g_1p25: smps1 { + regulator-name =3D "vreg_s1g_1p25"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + }; + + vreg_s2g_0p85: smps2 { + regulator-name =3D "vreg_s2g_0p85"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + }; + + vreg_s3g_0p8: smps3 { + regulator-name =3D "vreg_s3g_0p8"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_s4g_1p25: smps4 { + regulator-name =3D "vreg_s4g_1p25"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + + vreg_s5g_0p85: smps5 { + regulator-name =3D "vreg_s5g_0p85"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1004000>; + regulator-initial-mode =3D ; + }; + + vreg_s6g_1p86: smps6 { + regulator-name =3D "vreg_s6g_1p86"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name =3D "vreg_l1g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name =3D "vreg_l3g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32764>; +}; + +&xo_board { + clock-frequency =3D <76800000>; +}; --=20 2.43.0 From nobody Fri Jul 24 04:55:14 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FA083BED4F for ; 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[86.157.235.39]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957af914a9sm10799055e9.15.2026.07.23.11.18.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 11:18:19 -0700 (PDT) From: William Bright Date: Thu, 23 Jul 2026 19:18:10 +0100 Subject: [PATCH v5 4/4] arm64: dts: qcom: Add IMDT QCS8550 SBC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-imdt-qcs8550-sbc-rfc-v5-4-2fb988854623@imd-tec.com> References: <20260723-imdt-qcs8550-sbc-rfc-v5-0-2fb988854623@imd-tec.com> In-Reply-To: <20260723-imdt-qcs8550-sbc-rfc-v5-0-2fb988854623@imd-tec.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, William Bright X-Mailer: b4 0.15.2 The IMDT QCS8550 SBC is a two-board design from IMD Technologies Ltd built around the Qualcomm QCS8550 SoC. An IMDT QCS8550 SoM is soldered onto the IMDT QCS8550 carrier board that supplies VPH_PWR and exposes the off-module peripherals. With this DTS, the board can boot to shell with a UFS rootfs with debugging through uart7. USB is also are fully functional. Features enabled are: - On-board regulators - uSD - UART - UFS - PCIe0 (M.2 Key-E) - USB - ADSP, CDSP Assisted-by: Claude:claude-opus-4.7 Signed-off-by: William Bright --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs8550-imdt-sbc.dts | 401 ++++++++++++++++++++++= ++++ 2 files changed, 402 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index e05414290d8e..d1980d3ba352 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -192,6 +192,7 @@ qcs8300-ride-el2-dtbs :=3D qcs8300-ride.dtb monaco-el2.= dtbo =20 dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8300-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-aim300-aiot.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-imdt-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs8550-rb5gen2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs9100-ride-r3.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs8550-imdt-sbc.dts b/arch/arm64/boo= t/dts/qcom/qcs8550-imdt-sbc.dts new file mode 100644 index 000000000000..fa8794868cf8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-imdt-sbc.dts @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 IMD Technologies Ltd + */ + +/dts-v1/; + +#include "qcs8550-imdt-som.dtsi" + +/ { + model =3D "IMDT QCS8550 SBC"; + compatible =3D "imdt,qcs8550-sbc", "imdt,qcs8550-som", + "qcom,qcs8550", "qcom,sm8550"; + chassis-type =3D "embedded"; + + aliases { + serial0 =3D &uart7; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + connector { + compatible =3D "pcie-m2-e-connector"; + vpcie3v3-supply =3D <&m2e_3p3>; + vpcie1v8-supply =3D <&per_pwr>; + w-disable1-gpios =3D <&tlmm 80 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&m2e_wlan_disable>; + pinctrl-names =3D "default"; + + /* SDIO datapath is disabled because the SDIO lines are + * routed through unpopulated resistors. + * UART datapath is also disabled as the UART lines are + * routed through an analogue mux which currently cannot + * be described by a device tree. + */ + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + m2e_pcie_ep: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&pcie0_port0_ep>; + }; + }; + }; + }; + + m2e_3p3: regulator-m2e-3p3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "m2e_3p3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + pinctrl-0 =3D <&m2_pd_en_default>; + pinctrl-names =3D "default"; + + gpio =3D <&tlmm 144 GPIO_ACTIVE_LOW>; + }; + + /* Enables 5V_PER, 3V3_PER and 1V8_PER rails. 5V_PER and 3V3_PER + * aren't used within the DTS but are used for on board logic + * level conversion and as rails for pull-ups. 1V8_PER is used + * for M2 Key E. + */ + per_pwr: regulator-per-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "per_pwr"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + pinctrl-0 =3D <&pwr_per_en_default>; + pinctrl-names =3D "default"; + + gpio =3D <&tlmm 142 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-always-on; + regulator-boot-on; + }; + + sdhci_2_vqmmc: regulator-sdhci-2-vqmmc { + compatible =3D "regulator-gpio"; + + regulator-name =3D "sdhci_2_vqmmc"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-type =3D "voltage"; + + pinctrl-0 =3D <&sd_vset_default>; + pinctrl-names =3D "default"; + + gpios =3D <&tlmm 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + + gpios-states =3D <0>; + states =3D <3300000 0>, + <1800000 1>; + + startup-delay-us =3D <10000>; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + usb_id: usb-id { + compatible =3D "linux,extcon-usb-gpio"; + id-gpios =3D <&tlmm 53 GPIO_ACTIVE_HIGH>; + pinctrl-0 =3D <&usb_id_default>; + pinctrl-names =3D "default"; + }; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/sm8550/a740_zap.mbn"; +}; + +&i2c_hub_2 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + ptn3222: redriver@43 { + compatible =3D "nxp,ptn3222"; + reg =3D <0x43>; + #phy-cells =3D <0>; + + vdd1v8-supply =3D <&vreg_l15b_1p8>; + vdd3v3-supply =3D <&vreg_l5b_3p1>; + + pinctrl-0 =3D <&eusb2_repeater_reset_default>; + pinctrl-names =3D "default"; + + reset-gpios =3D <&pm8550vs_d_gpios 4 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c_master_hub_0 { + status =3D "okay"; +}; + +&ipa { + qcom,gsi-loader =3D "self"; + memory-region =3D <&ipa_fw_mem>; + firmware-name =3D "qcom/sm8550/ipa_fws.mbn"; + + status =3D "okay"; +}; + +&iris { + status =3D "okay"; +}; + +&pcie0 { + wake-gpios =3D <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios =3D <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1e_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&pcie0_port0 { + /* Required for pwrctrl driver bind */ + compatible =3D "pciclass,0604"; + + port { + pcie0_port0_ep: endpoint { + remote-endpoint =3D <&m2e_pcie_ep>; + }; + }; +}; + +&pm8550_gpios { + sd_card_detect_default: sd-card-detect-default-state { + pins =3D "gpio12"; + function =3D "normal"; + input-enable; + output-disable; + bias-disable; + power-source =3D <1>; /* 1.8 V */ + }; +}; + +&pm8550_rpmh_regulators { + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; +}; + +&pm8550ve_rpmh_regulators { + vdd-s4-supply =3D <&vph_pwr>; +}; + +&pm8550vs_d_gpios { + eusb2_repeater_reset_default: eusb2-repeater-reset-default-state { + pins =3D "gpio4"; + function =3D "normal"; + + input-enable; + output-enable; + bias-disable; + + drive-push-pull; + power-source =3D <1>; /* 1.8V */ + qcom,drive-strength =3D <3>; + }; +}; + +&pm8550vs_e_rpmh_regulators { + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; +}; + +&pm8550vs_g_rpmh_regulators { + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/sm8550/cdsp.mbn", + "qcom/sm8550/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + +&sdc2_default { + clk-pins { + drive-strength =3D <16>; + }; + + cmd-pins { + /delete-property/ bias-pull-up; + bias-disable; + drive-strength =3D <16>; + }; + + data-pins { + /delete-property/ bias-pull-up; + bias-disable; + drive-strength =3D <16>; + }; +}; + +&sdhc_2 { + cd-gpios =3D <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&sdc2_default>, <&sd_card_detect_default>; + pinctrl-1 =3D <&sdc2_default>, <&sd_card_detect_default>; + pinctrl-names =3D "default", "sleep"; + + vqmmc-supply =3D <&sdhci_2_vqmmc>; + + bus-width =3D <4>; + no-sdio; + no-mmc; + + status =3D "okay"; +}; + +&tlmm { + /* Reserved I/Os for NFC */ + gpio-reserved-ranges =3D <32 8>; + + m2_pd_en_default: m2-pd-en-default-state { + pins =3D "gpio144"; + function =3D "gpio"; + drive-strength =3D <16>; + drive-open-drain; + }; + + m2e_wlan_disable: m2e-wlan-disable-default-state { + pins =3D "gpio80"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + pwr_per_en_default: pwr-per-en-default-state { + pins =3D "gpio142"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + sd_vset_default: sd-vset-default-state { + pins =3D "gpio4"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + usb_id_default: usb-id-default-state { + pins =3D "gpio53"; + function =3D "gpio"; + bias-pull-up; + }; +}; + +&uart7 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l1g_1p2>; + vccq-max-microamp =3D <1200000>; + vdd-hba-supply =3D <&vreg_l3g_1p2>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1d_0p88>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&usb_1 { + dr_mode =3D "otg"; + extcon =3D <&usb_id>; + + status =3D "okay"; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l1e_0p88>; + vdda12-supply =3D <&vreg_l3e_1p2>; + + phys =3D <&ptn3222>; + + status =3D "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3e_1p2>; + vdda-pll-supply =3D <&vreg_l3f_0p88>; + + status =3D "okay"; +}; --=20 2.43.0