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Thu, 23 Jul 2026 06:21:10 -0700 (PDT) From: Jerome Brunet Date: Thu, 23 Jul 2026 15:20:59 +0200 Subject: [PATCH] clk: clean-up simple provider misuse of the consumer API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-clk-provider-simple-clean-v1-1-0c9668240467@baylibre.com> X-B4-Tracking: v=1; b=H4sIADoVYmoC/yXM2wrCMBCE4Vcpe20gxnrAV5FexM2oqzUNu1oKp e9u1MtvYP6ZDCowOjYzKUYxGXLFetUQ32K+wkmqpuDDzu/DxnH/cEWHURLUmTxLj7ohZhcPacv MLTh4qv+iuMj0a5+6v+19voNf3yAtywfP3KrvfQAAAA== X-Change-ID: 20260723-clk-provider-simple-clean-a8d5ccc4ec20 To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Michael Turquette , Stephen Boyd , Brian Masney , Bjorn Andersson , Geert Uytterhoeven , Heiko Stuebner , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Tero Kristo Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Clock provider should not be using the consumer interface. In other words, a provider should not be dealing with struct clk. This change targets occurrences for which the provider uses the consumer interface and corresponding clk_hw interface exist: * __clk_get_name() -> clk_hw_get_name() * __clk_is_enabled() -> clk_hw_is_enabled() * clk_get_rate() -> clk_hw_get_rate() Signed-off-by: Jerome Brunet Reviewed-by: Brian Masney --- The change being very simple, I did not think it was necessary to split it into multiple changes. If you prefer it to be split, just let me know how. --- drivers/clk/mvebu/clk-cpu.c | 2 +- drivers/clk/qcom/clk-hfpll.c | 4 ++-- drivers/clk/qcom/clk-krait.c | 2 +- drivers/clk/qcom/clk-rcg.c | 4 ++-- drivers/clk/qcom/clk-rcg2.c | 2 +- drivers/clk/renesas/r9a06g032-clocks.c | 2 +- drivers/clk/rockchip/clk-pll.c | 24 ++++++++++++------------ drivers/clk/st/clkgen-pll.c | 20 ++++++++++---------- drivers/clk/tegra/clk-tegra210.c | 2 +- drivers/clk/ti/clockdomain.c | 2 +- 10 files changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c index 26d52ecaac50..24196e288fe2 100644 --- a/drivers/clk/mvebu/clk-cpu.c +++ b/drivers/clk/mvebu/clk-cpu.c @@ -153,7 +153,7 @@ static int clk_cpu_on_set_rate(struct clk_hw *hwclk, un= signed long rate, static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate, unsigned long parent_rate) { - if (__clk_is_enabled(hwclk->clk)) + if (clk_hw_is_enabled(hwclk)) return clk_cpu_on_set_rate(hwclk, rate, parent_rate); else return clk_cpu_off_set_rate(hwclk, rate, parent_rate); diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c index 705352aff067..9e9118d24df7 100644 --- a/drivers/clk/qcom/clk-hfpll.c +++ b/drivers/clk/qcom/clk-hfpll.c @@ -166,7 +166,7 @@ static int clk_hfpll_set_rate(struct clk_hw *hw, unsign= ed long rate, =20 spin_lock_irqsave(&h->lock, flags); =20 - enabled =3D __clk_is_enabled(hw->clk); + enabled =3D clk_hw_is_enabled(hw); if (enabled) __clk_hfpll_disable(h); =20 @@ -220,7 +220,7 @@ static int clk_hfpll_init(struct clk_hw *hw) regmap_read(regmap, hd->status_reg, &status); if (!(status & BIT(hd->lock_bit))) { WARN(1, "HFPLL %s is ON, but not locked!\n", - __clk_get_name(hw->clk)); + clk_hw_get_name(hw)); clk_hfpll_disable(hw); __clk_hfpll_init_once(hw); } diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c index f5ce403e1e27..5e4408b7445d 100644 --- a/drivers/clk/qcom/clk-krait.c +++ b/drivers/clk/qcom/clk-krait.c @@ -68,7 +68,7 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 ind= ex) sel =3D clk_mux_index_to_val(mux->parent_map, 0, index); mux->en_mask =3D sel; /* Don't touch mux if CPU is off as it won't work */ - if (__clk_is_enabled(hw->clk)) + if (clk_hw_is_enabled(hw)) __krait_mux_set_sel(mux, sel); =20 mux->reparent =3D true; diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c index 31f0650b48ba..1664101e8f78 100644 --- a/drivers/clk/qcom/clk-rcg.c +++ b/drivers/clk/qcom/clk-rcg.c @@ -208,7 +208,7 @@ static int configure_bank(struct clk_dyn_rcg *rcg, cons= t struct freq_tbl *f) bool banked_p =3D !!rcg->p[1].pre_div_width; struct clk_hw *hw =3D &rcg->clkr.hw; =20 - enabled =3D __clk_is_enabled(hw->clk); + enabled =3D clk_hw_is_enabled(hw); =20 ret =3D regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); if (ret) @@ -771,7 +771,7 @@ static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsi= gned long rate, regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0); ret =3D __clk_rcg_set_rate(rcg, f); /* Switch back to M/N if it's clocking */ - if (__clk_is_enabled(hw->clk)) + if (clk_hw_is_enabled(hw)) regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm); =20 return ret; diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 6064a0e17d51..d7914e59129f 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -489,7 +489,7 @@ static int clk_rcg2_determine_gp_rate(struct clk_hw *hw, u64 parent_rate; =20 parent =3D clk_hw_get_parent(hw); - parent_rate =3D clk_get_rate(parent->clk); + parent_rate =3D clk_hw_get_rate(parent); if (!parent_rate) return -EINVAL; =20 diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r= 9a06g032-clocks.c index 076f587dfd39..1da25e4fb4d7 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -1014,7 +1014,7 @@ r9a06g032_div_determine_rate(struct clk_hw *hw, struc= t clk_rate_request *req) if (clk->index =3D=3D R9A06G032_DIV_UART || clk->index =3D=3D R9A06G032_DIV_P2_PG) { pr_devel("%s div uart hack!\n", __func__); - req->rate =3D clk_get_rate(hw->clk); + req->rate =3D clk_hw_get_rate(hw); return 0; } req->rate =3D DIV_ROUND_UP(req->best_parent_rate, div); diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 6b853800cb6b..89a783204f0e 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -259,13 +259,13 @@ static int rockchip_rk3036_pll_set_rate(struct clk_hw= *hw, unsigned long drate, const struct rockchip_pll_rate_table *rate; =20 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", - __func__, __clk_get_name(hw->clk), drate, prate); + __func__, clk_hw_get_name(hw), drate, prate); =20 /* Get required rate settings from table */ rate =3D rockchip_get_pll_settings(pll, drate); if (!rate) { pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw->clk)); + drate, clk_hw_get_name(hw)); return -EINVAL; } =20 @@ -319,7 +319,7 @@ static int rockchip_rk3036_pll_init(struct clk_hw *hw) =20 rockchip_rk3036_pll_get_params(pll, &cur); =20 - pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), + pr_debug("%s: pll %s@%lu: Hz\n", __func__, clk_hw_get_name(hw), drate); pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd:= %d, frac: %d\n", cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, @@ -336,12 +336,12 @@ static int rockchip_rk3036_pll_init(struct clk_hw *hw) =20 if (!parent) { pr_warn("%s: parent of %s not available\n", - __func__, __clk_get_name(hw->clk)); + __func__, clk_hw_get_name(hw)); return 0; } =20 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", - __func__, __clk_get_name(hw->clk)); + __func__, clk_hw_get_name(hw)); rockchip_rk3036_pll_set_params(pll, rate); } =20 @@ -743,13 +743,13 @@ static int rockchip_rk3399_pll_set_rate(struct clk_hw= *hw, unsigned long drate, const struct rockchip_pll_rate_table *rate; =20 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", - __func__, __clk_get_name(hw->clk), drate, prate); + __func__, clk_hw_get_name(hw), drate, prate); =20 /* Get required rate settings from table */ rate =3D rockchip_get_pll_settings(pll, drate); if (!rate) { pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw->clk)); + drate, clk_hw_get_name(hw)); return -EINVAL; } =20 @@ -803,7 +803,7 @@ static int rockchip_rk3399_pll_init(struct clk_hw *hw) =20 rockchip_rk3399_pll_get_params(pll, &cur); =20 - pr_debug("%s: pll %s@%lu: Hz\n", __func__, __clk_get_name(hw->clk), + pr_debug("%s: pll %s@%lu: Hz\n", __func__, clk_hw_get_name(hw), drate); pr_debug("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd:= %d, frac: %d\n", cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, @@ -820,12 +820,12 @@ static int rockchip_rk3399_pll_init(struct clk_hw *hw) =20 if (!parent) { pr_warn("%s: parent of %s not available\n", - __func__, __clk_get_name(hw->clk)); + __func__, clk_hw_get_name(hw)); return 0; } =20 pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n", - __func__, __clk_get_name(hw->clk)); + __func__, clk_hw_get_name(hw)); rockchip_rk3399_pll_set_params(pll, rate); } =20 @@ -992,13 +992,13 @@ static int rockchip_rk3588_pll_set_rate(struct clk_hw= *hw, unsigned long drate, const struct rockchip_pll_rate_table *rate; =20 pr_debug("%s: changing %s to %lu with a parent rate of %lu\n", - __func__, __clk_get_name(hw->clk), drate, prate); + __func__, clk_hw_get_name(hw), drate, prate); =20 /* Get required rate settings from table */ rate =3D rockchip_get_pll_settings(pll, drate); if (!rate) { pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, - drate, __clk_get_name(hw->clk)); + drate, clk_hw_get_name(hw)); return -EINVAL; } =20 diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c index 9eb2cb83fa69..17551c6a879a 100644 --- a/drivers/clk/st/clkgen-pll.c +++ b/drivers/clk/st/clkgen-pll.c @@ -260,7 +260,7 @@ static int __clkgen_pll_enable(struct clk_hw *hw) if (pll->data->switch2pll_en) CLKGEN_WRITE(pll, switch2pll, 0); =20 - pr_debug("%s:%s enabled\n", __clk_get_name(hw->clk), __func__); + pr_debug("%s:%s enabled\n", clk_hw_get_name(hw), __func__); } =20 return ret; @@ -295,7 +295,7 @@ static void __clkgen_pll_disable(struct clk_hw *hw) =20 CLKGEN_WRITE(pll, pdn_ctrl, 1); =20 - pr_debug("%s:%s disabled\n", __clk_get_name(hw->clk), __func__); + pr_debug("%s:%s disabled\n", clk_hw_get_name(hw), __func__); } =20 static void clkgen_pll_disable(struct clk_hw *hw) @@ -405,14 +405,14 @@ static int stm_pll3200c32_determine_rate(struct clk_h= w *hw, &req->rate); else { pr_debug("%s: %s rate %ld Invalid\n", __func__, - __clk_get_name(hw->clk), req->rate); + clk_hw_get_name(hw), req->rate); req->rate =3D 0; =20 return 0; } =20 pr_debug("%s: %s new rate %ld [ndiv=3D%u] [idf=3D%u]\n", - __func__, __clk_get_name(hw->clk), + __func__, clk_hw_get_name(hw), req->rate, (unsigned int)params.ndiv, (unsigned int)params.idf); =20 @@ -434,7 +434,7 @@ static int set_rate_stm_pll3200c32(struct clk_hw *hw, u= nsigned long rate, clk_pll3200c32_get_rate(parent_rate, ¶ms, &hwrate); =20 pr_debug("%s: %s new rate %ld [ndiv=3D0x%x] [idf=3D0x%x]\n", - __func__, __clk_get_name(hw->clk), + __func__, clk_hw_get_name(hw), hwrate, (unsigned int)params.ndiv, (unsigned int)params.idf); =20 @@ -547,7 +547,7 @@ static unsigned long recalc_stm_pll4600c28(struct clk_h= w *hw, =20 clk_pll4600c28_get_rate(parent_rate, ¶ms, &rate); =20 - pr_debug("%s:%s rate %lu\n", __clk_get_name(hw->clk), __func__, rate); + pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); =20 return rate; } @@ -562,14 +562,14 @@ static int stm_pll4600c28_determine_rate(struct clk_h= w *hw, &req->rate); } else { pr_debug("%s: %s rate %ld Invalid\n", __func__, - __clk_get_name(hw->clk), req->rate); + clk_hw_get_name(hw), req->rate); req->rate =3D 0; =20 return 0; } =20 pr_debug("%s: %s new rate %ld [ndiv=3D%u] [idf=3D%u]\n", - __func__, __clk_get_name(hw->clk), + __func__, clk_hw_get_name(hw), req->rate, (unsigned int)params.ndiv, (unsigned int)params.idf); =20 @@ -591,12 +591,12 @@ static int set_rate_stm_pll4600c28(struct clk_hw *hw,= unsigned long rate, clk_pll4600c28_get_rate(parent_rate, ¶ms, &hwrate); } else { pr_debug("%s: %s rate %ld Invalid\n", __func__, - __clk_get_name(hw->clk), rate); + clk_hw_get_name(hw), rate); return -EINVAL; } =20 pr_debug("%s: %s new rate %ld [ndiv=3D0x%x] [idf=3D0x%x]\n", - __func__, __clk_get_name(hw->clk), + __func__, clk_hw_get_name(hw), hwrate, (unsigned int)params.ndiv, (unsigned int)params.idf); =20 diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra= 210.c index 0c86cff719e3..df1d7b471745 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -1460,7 +1460,7 @@ static int tegra210_pllx_dyn_ramp(struct tegra_clk_pl= l *pllx, udelay(1); =20 pr_debug("%s: dynamic ramp to m =3D %u n =3D %u p =3D %u, Fout =3D %lu kH= z\n", - __clk_get_name(pllx->hw.clk), cfg->m, cfg->n, cfg->p, + clk_hw_get_name(&pllx->hw), cfg->m, cfg->n, cfg->p, cfg->input_rate / cfg->m * cfg->n / pllx->params->pdiv_tohw[cfg->p].pdiv / 1000); =20 diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c index c897ad7e681e..aedbe78bf1e4 100644 --- a/drivers/clk/ti/clockdomain.c +++ b/drivers/clk/ti/clockdomain.c @@ -104,7 +104,7 @@ int omap2_init_clk_clkdm(struct clk_hw *hw) if (!clk->clkdm_name) return 0; =20 - clk_name =3D __clk_get_name(hw->clk); + clk_name =3D clk_hw_get_name(hw); =20 clkdm =3D ti_clk_ll_ops->clkdm_lookup(clk->clkdm_name); if (clkdm) { --- base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482 change-id: 20260723-clk-provider-simple-clean-a8d5ccc4ec20 Best regards, -- =20 Jerome