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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38ea598f67bsm1427988a91.3.2026.07.23.01.26.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 01:26:53 -0700 (PDT) From: Jie Gan Date: Thu, 23 Jul 2026 16:26:30 +0800 Subject: [PATCH v5 1/2] dt-bindings: arm: qcom,coresight-ctcu: Add Shikra Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-add-coresight-nodes-for-shikra-v5-1-fd5494471b36@oss.qualcomm.com> References: <20260723-add-coresight-nodes-for-shikra-v5-0-fd5494471b36@oss.qualcomm.com> In-Reply-To: <20260723-add-coresight-nodes-for-shikra-v5-0-fd5494471b36@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yuanfang Zhang , Mao Jinlong , Jie Gan , Bjorn Andersson , Konrad Dybcio , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784795201; l=956; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=KjZAmYYdX486FIyES0cXfj7PWztonIPwwITTJrvXDuU=; b=TxKjQwwDs9O+H09f7qetw/BCCIiqpxd6Zi5xm1od/kvdiFHVGC1fwFaeEaQIyPKjcOBLZh2gj SVWRqEX8gUADZkvODfn7si8xRXRv8/poBhJLrokRP4sd3mtdFwfS1x0 X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Authority-Analysis: v=2.4 cv=Q53iJY2a c=1 sm=1 tr=0 ts=6a61d04e cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=BZKsYnZZkaJ4N7IUUl4A:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIzMDA4NCBTYWx0ZWRfX9d+fwL0VVb8F j1sIsZmr5yGsZQxXDsLcADuzE4iKIR+bHg3glK5sx8bLztDJH99DuH+/PtaXyvUyPiznIvy5FcD 6M7d4uG4g4CkZM6Jn2mH13z3VaDlL84= X-Proofpoint-GUID: ylpGLOBYeVUJ4zPp8xpsi8MmF0w310Ya X-Proofpoint-ORIG-GUID: ylpGLOBYeVUJ4zPp8xpsi8MmF0w310Ya X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIzMDA4NCBTYWx0ZWRfXzfKK04kJvn60 09Z5KNzurKtlGjW1FakQDAlp1TTJXM8PPPiS8rk17dggSdI/rj3xCyGk3x08NF/PfZzI95VZaoh MKmk9HbhDZd77HZN8y2dqYWM26ENx4lIfbCrJ9afpM70c4GopeAlJzgBPQI2R02/QR9koJCD8Cl 4Tz2tMe9YG9caN09bOlT+zkGpqIz3GH3gdzbdZ1guWTtMDWKVUBVubbrpaNC0nxruJDVTCflEsc 6Yek/cwuvSqJAVopqRS/WNrre1hbUS5h61ZA2dPJjiTLQsQ42cUqGgv179Ouwmk4LgFySGmNNGh EQA+UmjbiuYX9lyRkVIxFiJBc84UZIrQhporO2M9unQy8aeF9EF/yPmJhIpMvbnEJtQrgJqKmq3 yO10S8gqqW7Y4aFCilGA2wz69L1xtF1LraQoIyK9qkqB4o7FGULI70B+9jUrpZFJNLRA6eoptMO EildlsS+iKXZCVrcAfQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-23_02,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 priorityscore=1501 adultscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607230084 The CTCU device for the Shikra shares the same configurations as SA8775p. Add a fallback to enable the CTCU for the Shikra to utilize the compatible of the SA8775p. Signed-off-by: Jie Gan Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index f3f3feac4ce2..335a8e1a5a9e 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -32,6 +32,7 @@ properties: - qcom,glymur-ctcu - qcom,kaanapali-ctcu - qcom,qcs8300-ctcu + - qcom,shikra-ctcu - qcom,sm8750-ctcu - qcom,x1e80100-ctcu - const: qcom,sa8775p-ctcu --=20 2.34.1 From nobody Fri Jul 24 21:54:44 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90A713F329E for ; Thu, 23 Jul 2026 08:27:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38ea598f67bsm1427988a91.3.2026.07.23.01.26.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 01:26:59 -0700 (PDT) From: Jie Gan Date: Thu, 23 Jul 2026 16:26:31 +0800 Subject: [PATCH v5 2/2] arm64: dts: qcom: shikra: Add coresight nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-add-coresight-nodes-for-shikra-v5-2-fd5494471b36@oss.qualcomm.com> References: <20260723-add-coresight-nodes-for-shikra-v5-0-fd5494471b36@oss.qualcomm.com> In-Reply-To: <20260723-add-coresight-nodes-for-shikra-v5-0-fd5494471b36@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yuanfang Zhang , Mao Jinlong , Jie Gan , Bjorn Andersson , Konrad Dybcio , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784795201; l=27710; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=cnjRfXOGCiLdO/PiqrdR1gHMAwcIDL3Y5bbe8uCeOcs=; b=D3Xi5KKEzVUCS+I7zqjE9Se8azya/2Tk+sL4bVpqd4xjyojgSvdzt+ZwlAPPojBdSBa7wY6Dm KRCXGzUx1baA/6qYAc4RoNNFCbUddr05I4MidomzPzPzpYttRcqjYra X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Authority-Analysis: v=2.4 cv=XNkAjwhE c=1 sm=1 tr=0 ts=6a61d055 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=cwPG6XMBaqf5cbKo9vYA:9 a=6PrL1bzTSInMHGBt:21 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-ORIG-GUID: CR-LsUCiBQYVnZWNbfz4POazUO_VtEEX X-Proofpoint-GUID: CR-LsUCiBQYVnZWNbfz4POazUO_VtEEX X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIzMDA4NCBTYWx0ZWRfX8+yjQWzCTgwT HG+zFU1OT6tFsO+UNakkRZKm8EkK9zPxjSBwAcs60mrAt5JWeJqNueBy5qpE/dhfW+B/KTijMtb e9dW5XCnj01L3ECx1NyucdntRJmmXm8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIzMDA4NCBTYWx0ZWRfX84DkOhtb9bYC Wkuo2Vwx1/ybHDSSvAutmniHtJX+jIG/4yt6fjZg3JZ0Lc5tbMYiTeUpvM0JKqr5+0uErJzUjKt L2ZLpcT8g3ZYvB5gz2OrmSouNPtic2SGThjVqkv2cvQ0oJuCpzp68oLmlK+VFMBF8w+PivpKzOK X2+GaMhRac4yixNA11jaXPM6B0ctSIBOh47Qzi8HI8DOVPlEnBUry9nYOjmflNKPkCHCCS7coMm KT5+h9bHUCN5Cmn6iO3QVReu8rDRf9fkAuT1EMw6aT8j3uzTe/ROtH77OyeM2NR92FDz2iGgXUA jTMMNk+FCo7oHo8hMazqNnc9povRRFB3Zy72wqo4zdiDkdrX5lzrclFuxT7aXbL48zgN+GZbgmk wrw7harJEbxthbCSZG0yuZYMIlCzTaeI7dlk0S6GI05xpVL2eyfzd0R+WsDGFPiHXAdRMm/RLjC 8UykFv/Ehlm1YaKIWZw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-23_02,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 suspectscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 priorityscore=1501 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607230084 Add DT nodes for the CoreSight debug and trace subsystem on Qualcomm Shikra SoC. Signed-off-by: Jie Gan Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/shikra.dtsi | 1295 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 1295 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index 4e5bc9e17c8e..eb0f3c36068f 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -113,6 +113,88 @@ l3: l3-cache { }; }; =20 + dummy-eud { + compatible =3D "arm,coresight-dummy-sink"; + + label =3D "eud"; + + in-ports { + port { + eud_in: endpoint { + remote-endpoint =3D <&replicator_eud_out1>; + }; + }; + }; + }; + + etm0 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu0>; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint =3D <&funnel_cpuss0_in0>; + }; + }; + }; + }; + + etm1 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu1>; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint =3D <&funnel_cpuss0_in1>; + }; + }; + }; + }; + + etm2 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu2>; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint =3D <&funnel_cpuss0_in2>; + }; + }; + }; + }; + + etm3 { + compatible =3D "arm,coresight-etm4x-sysreg"; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + cpu =3D <&cpu3>; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint =3D <&funnel_cpuss0_in3>; + }; + }; + }; + }; + firmware { scm { compatible =3D "qcom,scm-shikra", "qcom,scm"; @@ -131,6 +213,21 @@ memory@80000000 { reg =3D <0x0 0x80000000 0x0 0x0>; }; =20 + modem-etm0 { + compatible =3D "arm,coresight-dummy-source"; + + label =3D "modem_etm0"; + arm,static-trace-id =3D <36>; + + out-ports { + port { + modem_etm0_out: endpoint { + remote-endpoint =3D <&funnel_in1_in4>; + }; + }; + }; + }; + pmu-a55 { compatible =3D "arm,cortex-a55-pmu"; interrupts =3D ; @@ -640,6 +737,1189 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, }; }; =20 + ctcu@8001000 { + compatible =3D "qcom,shikra-ctcu", "qcom,sa8775p-ctcu"; + reg =3D <0x0 0x08001000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb"; + + in-ports { + port { + ctcu_in0: endpoint { + remote-endpoint =3D <&etr0_out>; + }; + }; + }; + }; + + stm@8002000 { + compatible =3D "arm,coresight-stm", "arm,primecell"; + reg =3D <0x0 0x08002000 0x0 0x1000>, + <0x0 0x0e280000 0x0 0x180000>; + reg-names =3D "stm-base", + "stm-stimulus-base"; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint =3D <&funnel_in0_in7>; + }; + }; + }; + }; + + tpdm@8003000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x08003000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_dcc"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_dcc_out: endpoint { + remote-endpoint =3D <&tpda_qdss_in0>; + }; + }; + }; + }; + + tpda@8004000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x08004000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + tpda_qdss_in0: endpoint { + remote-endpoint =3D <&tpdm_dcc_out>; + }; + }; + + port@1 { + reg =3D <1>; + + tpda_qdss_in1: endpoint { + remote-endpoint =3D <&tpdm_spdm_out>; + }; + }; + }; + + out-ports { + port { + tpda_qdss_out: endpoint { + remote-endpoint =3D <&funnel_in0_in6>; + }; + }; + }; + }; + + tpdm@800f000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x0800f000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_spdm"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_spdm_out: endpoint { + remote-endpoint =3D <&tpda_qdss_in1>; + }; + }; + }; + }; + + funnel@8041000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x08041000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@5 { + reg =3D <5>; + + funnel_in0_in5: endpoint { + remote-endpoint =3D <&snoc_out>; + }; + }; + + port@6 { + reg =3D <6>; + + funnel_in0_in6: endpoint { + remote-endpoint =3D <&tpda_qdss_out>; + }; + }; + + port@7 { + reg =3D <7>; + + funnel_in0_in7: endpoint { + remote-endpoint =3D <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint =3D <&funnel_merg_in0>; + }; + }; + }; + }; + + funnel@8042000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x08042000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + funnel_in1_in1: endpoint { + remote-endpoint =3D <&tpda_aodbg_out>; + }; + }; + + port@4 { + reg =3D <4>; + + funnel_in1_in4: endpoint { + remote-endpoint =3D <&modem_etm0_out>; + }; + }; + + port@6 { + reg =3D <6>; + + funnel_in1_in6: endpoint { + remote-endpoint =3D <&funnel_cpuss1_out>; + }; + }; + + port@7 { + reg =3D <7>; + + funnel_in1_in7: endpoint { + remote-endpoint =3D <&funnel_center_out>; + }; + }; + }; + + out-ports { + port { + funnel_in1_out: endpoint { + remote-endpoint =3D <&funnel_merg_in1>; + }; + }; + }; + }; + + funnel@8045000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x08045000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + funnel_merg_in0: endpoint { + remote-endpoint =3D <&funnel_in0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + funnel_merg_in1: endpoint { + remote-endpoint =3D <&funnel_in1_out>; + }; + }; + }; + + out-ports { + port { + funnel_merg_out: endpoint { + remote-endpoint =3D <&tmc_etf_in>; + }; + }; + }; + }; + + replicator@8046000 { + compatible =3D "arm,coresight-dynamic-replicator", "arm,primecell"; + reg =3D <0x0 0x08046000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + replicator_qdss_in: endpoint { + remote-endpoint =3D <&tmc_etf_out>; + }; + }; + }; + + out-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + replicator_qdss_out0: endpoint { + remote-endpoint =3D <&etr0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + replicator_qdss_out1: endpoint { + remote-endpoint =3D <&replicator_eud_in>; + }; + }; + }; + }; + + tmc@8047000 { + compatible =3D "arm,coresight-tmc", "arm,primecell"; + reg =3D <0x0 0x08047000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + tmc_etf_in: endpoint { + remote-endpoint =3D <&funnel_merg_out>; + }; + }; + }; + + out-ports { + port { + tmc_etf_out: endpoint { + remote-endpoint =3D <&replicator_qdss_in>; + }; + }; + }; + }; + + tmc@8048000 { + compatible =3D "arm,coresight-tmc", "arm,primecell"; + reg =3D <0x0 0x08048000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + iommus =3D <&apps_smmu 0x0160 0x0>; + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint =3D <&replicator_qdss_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint =3D <&ctcu_in0>; + }; + }; + }; + }; + + replicator@804a000 { + compatible =3D "arm,coresight-dynamic-replicator", "arm,primecell"; + reg =3D <0x0 0x0804a000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + replicator_eud_in: endpoint { + remote-endpoint =3D <&replicator_qdss_out1>; + }; + }; + }; + + out-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + replicator_eud_out1: endpoint { + remote-endpoint =3D <&eud_in>; + }; + }; + }; + }; + + tpdm@8800000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x08800000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_cdsp"; + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <4>; + + out-ports { + port { + tpdm_cdsp_out: endpoint { + remote-endpoint =3D <&funnel_cdsp_in0>; + }; + }; + }; + }; + + funnel@8801000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x08801000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + funnel_cdsp_in0: endpoint { + remote-endpoint =3D <&tpdm_cdsp_out>; + }; + }; + }; + + out-ports { + port { + funnel_cdsp_out0: endpoint { + remote-endpoint =3D <&tpda_center_in3>; + }; + }; + }; + }; + + cti@8807000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x08807000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_turing_q6"; + }; + + cti@8833000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x08833000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_mss_q6"; + }; + + tpdm@8840000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x08840000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_vsense"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_vsense_out: endpoint { + remote-endpoint =3D <&tpda_center_in6>; + }; + }; + }; + }; + + tpdm@8844000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x08844000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_dlct_1"; + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_dlct_1_out: endpoint { + remote-endpoint =3D <&tpda_center_in13>; + }; + }; + }; + }; + + tpda@8845000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x08845000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + tpda_center_in0: endpoint { + remote-endpoint =3D <&funnel_mcu_out>; + }; + }; + + port@2 { + reg =3D <2>; + + tpda_center_in2: endpoint { + remote-endpoint =3D <&tpdm_dlct_out>; + }; + }; + + port@3 { + reg =3D <3>; + + tpda_center_in3: endpoint { + remote-endpoint =3D <&funnel_cdsp_out0>; + }; + }; + + port@4 { + reg =3D <4>; + + tpda_center_in4: endpoint { + remote-endpoint =3D <&funnel_ddr_out0>; + }; + }; + + port@6 { + reg =3D <6>; + + tpda_center_in6: endpoint { + remote-endpoint =3D <&tpdm_vsense_out>; + }; + }; + + port@7 { + reg =3D <7>; + + tpda_center_in7: endpoint { + remote-endpoint =3D <&tpdm_prng_out>; + }; + }; + + port@8 { + reg =3D <8>; + + tpda_center_in8: endpoint { + remote-endpoint =3D <&tpdm_west_out>; + }; + }; + + port@9 { + reg =3D <9>; + + tpda_center_in9: endpoint { + remote-endpoint =3D <&tpdm_qm_out>; + }; + }; + + port@a { + reg =3D <0xa>; + + tpda_center_in10: endpoint { + remote-endpoint =3D <&tpdm_pimem_out>; + }; + }; + + port@d { + reg =3D <0xd>; + + tpda_center_in13: endpoint { + remote-endpoint =3D <&tpdm_dlct_1_out>; + }; + }; + }; + + out-ports { + port { + tpda_center_out: endpoint { + remote-endpoint =3D <&funnel_center_in0>; + }; + }; + }; + }; + + funnel@8846000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x08846000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + funnel_center_in0: endpoint { + remote-endpoint =3D <&tpda_center_out>; + }; + }; + }; + + out-ports { + port { + funnel_center_out: endpoint { + remote-endpoint =3D <&funnel_in1_in7>; + }; + }; + }; + }; + + tpdm@884c000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x0884c000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_prng"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + tpdm_prng_out: endpoint { + remote-endpoint =3D <&tpda_center_in7>; + }; + }; + }; + }; + + tpdm@8850000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x08850000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_pimem"; + qcom,cmb-element-bits =3D <64>; + qcom,dsb-element-bits =3D <32>; + + out-ports { + port { + tpdm_pimem_out: endpoint { + remote-endpoint =3D <&tpda_center_in10>; + }; + }; + }; + }; + + tpdm@8980000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x08980000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_mcu"; + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <16>; + + out-ports { + port { + tpdm_mcu_out: endpoint { + remote-endpoint =3D <&funnel_mcu_in0>; + }; + }; + }; + }; + + funnel@8982000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x08982000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + funnel_mcu_in0: endpoint { + remote-endpoint =3D <&tpdm_mcu_out>; + }; + }; + }; + + out-ports { + port { + funnel_mcu_out: endpoint { + remote-endpoint =3D <&tpda_center_in0>; + }; + }; + }; + }; + + tpdm@89d0000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x089d0000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_qm"; + qcom,dsb-element-bits =3D <32>; + + out-ports { + port { + tpdm_qm_out: endpoint { + remote-endpoint =3D <&tpda_center_in9>; + }; + }; + }; + }; + + tpdm@8a01000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x08a01000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_mapss"; + qcom,cmb-element-bits =3D <32>; + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <16>; + + out-ports { + port { + tpdm_mapss_out: endpoint { + remote-endpoint =3D <&tpda_aodbg_in>; + }; + }; + }; + }; + + cti@8a02000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x08a02000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_mapss"; + }; + + tpda@8a04000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x08a04000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + tpda_aodbg_in: endpoint { + remote-endpoint =3D <&tpdm_mapss_out>; + }; + }; + }; + + out-ports { + port { + tpda_aodbg_out: endpoint { + remote-endpoint =3D <&funnel_in1_in1>; + }; + }; + }; + }; + + tpdm@8a58000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x08a58000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_west"; + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <16>; + + out-ports { + port { + tpdm_west_out: endpoint { + remote-endpoint =3D <&tpda_center_in8>; + }; + }; + }; + }; + + cti@8b30000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x08b30000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_cortex_m3"; + }; + + tpdm@8b58000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x08b58000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_dlct"; + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <16>; + + out-ports { + port { + tpdm_dlct_out: endpoint { + remote-endpoint =3D <&tpda_center_in2>; + }; + }; + }; + }; + + cti@8b59000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x08b59000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_dlct_0"; + }; + + cti@8b5a000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x08b5a000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_dlct_1"; + }; + + cti@8b5b000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x08b5b000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_dlct_2"; + }; + + cti@8b5c000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x08b5c000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_dlct_3"; + }; + + tpdm@8b60000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x08b60000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_ddr"; + qcom,cmb-element-bits =3D <32>; + qcom,cmb-msrs-num =3D <1>; + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_ddr_out: endpoint { + remote-endpoint =3D <&funnel_ddr_in0>; + }; + }; + }; + }; + + cti@8b62000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x08b62000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_ddr_dl_0"; + }; + + funnel@8b65000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x08b65000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + funnel_ddr_in0: endpoint { + remote-endpoint =3D <&tpdm_ddr_out>; + }; + }; + }; + + out-ports { + port { + funnel_ddr_out0: endpoint { + remote-endpoint =3D <&tpda_center_in4>; + }; + }; + }; + }; + + cti@8b70000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x08b70000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_ddr_dl_0_1"; + }; + + cti@8b71000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x08b71000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_ddr_dl_1_1"; + }; + + cti@9020000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x09020000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_apss_pe0"; + }; + + cti@90e0000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x090e0000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_apss_cluster"; + }; + + cti@9120000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x09120000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_apss_pe1"; + }; + + cti@9220000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x09220000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_apss_pe2"; + }; + + cti@9320000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x09320000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_apss_pe3"; + }; + + funnel@9800000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x09800000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + funnel_cpuss0_in0: endpoint { + remote-endpoint =3D <&etm0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + funnel_cpuss0_in1: endpoint { + remote-endpoint =3D <&etm1_out>; + }; + }; + + port@2 { + reg =3D <2>; + + funnel_cpuss0_in2: endpoint { + remote-endpoint =3D <&etm2_out>; + }; + }; + + port@3 { + reg =3D <3>; + + funnel_cpuss0_in3: endpoint { + remote-endpoint =3D <&etm3_out>; + }; + }; + }; + + out-ports { + port { + funnel_cpuss0_out: endpoint { + remote-endpoint =3D <&funnel_cpuss1_in0>; + }; + }; + }; + }; + + funnel@9810000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x09810000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + funnel_cpuss1_in0: endpoint { + remote-endpoint =3D <&funnel_cpuss0_out>; + }; + }; + + port@3 { + reg =3D <3>; + + funnel_cpuss1_in3: endpoint { + remote-endpoint =3D <&tpda_apss_out>; + }; + }; + }; + + out-ports { + port { + funnel_cpuss1_out: endpoint { + remote-endpoint =3D <&funnel_in1_in6>; + }; + }; + }; + }; + + cti@982b000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x0982b000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_riscv"; + }; + + tpdm@9860000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x09860000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_actpm"; + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <1>; + + out-ports { + port { + tpdm_actpm_out: endpoint { + remote-endpoint =3D <&tpda_apss_in2>; + }; + }; + }; + }; + + tpdm@9861000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x09861000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_hwe"; + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + tpdm_hwe_out: endpoint { + remote-endpoint =3D <&tpda_apss_in3>; + }; + }; + }; + }; + + tpda@9863000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x09863000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + tpda_apss_in0: endpoint { + remote-endpoint =3D <&tpdm_llm_silver_out>; + }; + }; + + port@2 { + reg =3D <2>; + + tpda_apss_in2: endpoint { + remote-endpoint =3D <&tpdm_actpm_out>; + }; + }; + + port@3 { + reg =3D <3>; + + tpda_apss_in3: endpoint { + remote-endpoint =3D <&tpdm_hwe_out>; + }; + }; + }; + + out-ports { + port { + tpda_apss_out: endpoint { + remote-endpoint =3D <&funnel_cpuss1_in3>; + }; + }; + }; + }; + + tpdm@98a0000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x098a0000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + + label =3D "tpdm_llm_silver"; + qcom,cmb-element-bits =3D <32>; + qcom,cmb-msrs-num =3D <12>; + + out-ports { + port { + tpdm_llm_silver_out: endpoint { + remote-endpoint =3D <&tpda_apss_in0>; + }; + }; + }; + }; + + cti@98e0000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x098e0000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_apss_0"; + }; + + cti@98f0000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x098f0000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_apss_1"; + }; + + cti@9900000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x09900000 0x0 0x1000>; + + clocks =3D <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names =3D "apb_pclk"; + label =3D "cti_apss_2"; + }; + sram@c11e000 { compatible =3D "qcom,shikra-imem", "mmio-sram"; reg =3D <0x0 0x0c11e000 0x0 0x1000>; @@ -831,6 +2111,21 @@ frame@f42d000 { }; }; =20 + snoc { + compatible =3D "arm,coresight-dummy-source"; + + label =3D "snoc"; + arm,static-trace-id =3D <18>; + + out-ports { + port { + snoc_out: endpoint { + remote-endpoint =3D <&funnel_in0_in5>; + }; + }; + }; + }; + timer { compatible =3D "arm,armv8-timer"; =20 --=20 2.34.1