From nobody Fri Jul 24 05:22:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A4223CAE84; Thu, 23 Jul 2026 06:43:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784789035; cv=none; b=PhbIBHJ4euofgdoy44lgKLiP4f3noz2kYYs3boLmLiVBkMkO2jNqHY7whruuimM7+OYho7yYqjFEyyBzJyRzsUjPx45vSCNWmw9DQ+Mq0nz0zFLBWJsmbkmAHAg5X15gGSx7lx/6rJeMeZyuEE+JQ4lDiTsvKoL1KALegTqD6H8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784789035; c=relaxed/simple; bh=XQltrhhdDEOv3aEgBjYadnzuNlFB/71hwbYn4rzhXMQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MzF6Oa8IGWsj1doSL2ILIBMklUbg5oLKnI2fmd+EnOkW2M3ceEPyC+k7G/2NZSLv+HEyKoZX4lGXE2XK/m2yMFEf2CemBefhUyMT6xftbVxVgbBga4JzVgFOC0AvkSLH+6Cn9zikJ0fEEBhP1qQ+GHTi0Z12SSjSB8jr8y/wlf4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gFry3Qcn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gFry3Qcn" Received: by smtp.kernel.org (Postfix) with ESMTPS id 445A3C2BCC7; Thu, 23 Jul 2026 06:43:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784789035; bh=XQltrhhdDEOv3aEgBjYadnzuNlFB/71hwbYn4rzhXMQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=gFry3QcnCwvkdi2qBzBIFjd9Ql3ATFJHpLatDTvAYduApTDBQi3/dimZ1FdZ+31EO NcYcAqsGCpe8rvQuifUmrjK+4izhm/6xMOEvln+uX302ZwfKl4jUO5oX5xvxD+T2ii ZmLyMLK1fHgcAcs5qiMBpRz9VpX0z2FAj/BMnvADAlr3A5lPe+75hp4nhiPTRyaNbN ISWkNYUjo1VJKhcPpbXI7IcSWg+ZhyiyER/UX82UMrFLExRGMO4Tydt/0KsSrrJQX8 yuuXn9N3W8h+cz5eureSZO7JD9aBOfAVMVtPsPhMQDdkiTUPfiHqB8nX1c2hRXvHEn YsK61Kr/KvJwA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 232A0C531CB; Thu, 23 Jul 2026 06:43:55 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Thu, 23 Jul 2026 06:43:42 +0000 Subject: [PATCH v2 1/4] spi: dt-bindings: amlogic: spisg: Document A9-specific properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-a9-spisg-v2-1-9fc39106b7e2@amlogic.com> References: <20260723-a9-spisg-v2-0-9fc39106b7e2@amlogic.com> In-Reply-To: <20260723-a9-spisg-v2-0-9fc39106b7e2@amlogic.com> To: Sunny Luo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784789030; l=2195; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=A2bVyZIU8ueKZKzfA2QNoWvbKtTJ6W1aJGMG6E4FE54=; b=AIm5d9oRD0BkkfTz9T/TtZ41z3rKMtlDTNoDIeikQwndF6WXhphmeCUBUwXVK5utHWQKPliUH jp/KjYz1l3rDk9TdKThZa8f7XhTRxxVVvfEHmI7Fx7BAd63WOpw/ZAn X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Document the Amlogic A9 SPISG controller and its additional Device Tree properties. Add the "amlogic,a9-spisg" compatible string and define the A9-specific "amlogic,mo-idle-output" and "amlogic,word-gap" properties, which configure the MOSI idle output level and the inter-word gap, respectively. Signed-off-by: Xianwei Zhao --- .../devicetree/bindings/spi/amlogic,a4-spisg.yaml | 38 ++++++++++++++++++= +--- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml b/= Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml index 9bfb8089f7ea..ddef92f3f3b6 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml @@ -11,12 +11,11 @@ maintainers: - Xianwei Zhao - Sunny Luo =20 -allOf: - - $ref: spi-controller.yaml# - properties: compatible: - const: amlogic,a4-spisg + enum: + - amlogic,a4-spisg + - amlogic,a9-spisg =20 reg: maxItems: 1 @@ -35,6 +34,23 @@ properties: resets: maxItems: 1 =20 + amlogic,mo-idle-output: + description: | + Controls the MOSI output level when the controller is idle. + 0 - Drive MOSI low + 1 - Drive MOSI high + 2 - Follow the last transmitted bit + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 0 + + amlogic,word-gap: + description: | + Number of idle clock cycles inserted between consecutive SPI words. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 1 + required: - compatible - reg @@ -42,6 +58,20 @@ required: - clocks - clock-names =20 +allOf: + - $ref: spi-controller.yaml# + - if: + not: + properties: + compatible: + contains: + enum: + - amlogic,a9-spisg + then: + properties: + amlogic,mo-idle-output: false + amlogic,word-gap: false + unevaluatedProperties: false =20 examples: --=20 2.52.0 From nobody Fri Jul 24 05:22:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A2DA3CAA55; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XbYL4BSG" Received: by smtp.kernel.org (Postfix) with ESMTPS id 58C4EC2BCFB; Thu, 23 Jul 2026 06:43:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784789035; bh=rq/tb46DP924L/FjVCUkL1FIttRHuK8j2ySAzVvIQZM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XbYL4BSGZAv0WxaCtL8jmrjVRgzC0CFAE9Ab1JbksIpmQyf0ciXvgt/KkwPfqGsqO KWe1O+xA3Q+TzUGlZtKuTRO06vuHMiGiwPqSNZh7UzANxWHzxzFQfg1ND7JyM0RFlU gqst3UuxImXzGRzxqtOB7WKv2/piiyqlR+7pLB9N9cw0XaGmJiiKfstFac+ikguCua sh+di3XtXZDvnC6G9sIzivoXbzgq2E34noVl0T0VnZC/F/2+hR63oC9A630iRqlcJ2 Gqz54e9VIEy7Zw2ar6Qbcq30Okdup7ixrobCDZ6HyPv+BUd6N+CVxz4wFVT4JkAbBS v6l077mDNEYDA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E053C531CC; Thu, 23 Jul 2026 06:43:55 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Thu, 23 Jul 2026 06:43:43 +0000 Subject: [PATCH v2 2/4] spi: amlogic: spisg: Fix transfer size limit and timeout handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-a9-spisg-v2-2-9fc39106b7e2@amlogic.com> References: <20260723-a9-spisg-v2-0-9fc39106b7e2@amlogic.com> In-Reply-To: <20260723-a9-spisg-v2-0-9fc39106b7e2@amlogic.com> To: Sunny Luo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784789030; l=1947; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=BRq2nLOiEjtiR+0vj/uM6L8HPr1w32uaAGwS/r33K78=; b=PgCQZw3mX0UQF39rzre8XLicz8qQXc+g7Wvu8j+DV8pNFDId2rQQuwKINbqgS1PSUnglS1j7Y rUOXJreyVG8Aj2RH0Hk9o4kRGLtkgtqyt+v3Unci8I/MoDGBXl26Svo X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao The CFG_BLOCK_NUM field can encode at most 20 bits, so reduce SPISG_BLOCK_MAX to 0xfffff to avoid programming a zero-length transfer. Perform the delay calculation in 64-bit arithmetic to avoid overflow when converting nanoseconds to SPI clock cycles. Stop the controller on transfer timeout by clearing the descriptor list register before returning an error. Fixes: cef9991e04ae ("spi: Add Amlogic SPISG driver") Signed-off-by: Xianwei Zhao --- drivers/spi/spi-amlogic-spisg.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-amlogic-spisg.c b/drivers/spi/spi-amlogic-spis= g.c index afc8af04638d..a6123975a37c 100644 --- a/drivers/spi/spi-amlogic-spisg.c +++ b/drivers/spi/spi-amlogic-spisg.c @@ -95,7 +95,7 @@ =20 #define SPISG_MAX_REG 0x40 =20 -#define SPISG_BLOCK_MAX 0x100000 +#define SPISG_BLOCK_MAX 0xFFFFF =20 #define SPISG_OP_MODE_WRITE_CMD 0 #define SPISG_OP_MODE_READ_STS 1 @@ -175,7 +175,7 @@ static int spi_delay_to_sclk(u32 slck_speed_hz, struct = spi_delay *delay) if (ns < 0) return 0; =20 - return DIV_ROUND_UP_ULL(slck_speed_hz * ns, NSEC_PER_SEC); + return DIV_ROUND_UP_ULL((u64)slck_speed_hz * ns, NSEC_PER_SEC); } =20 static inline u32 aml_spisg_sem_down_read(struct spisg_device *spisg) @@ -565,10 +565,13 @@ static int aml_spisg_transfer_one_message(struct spi_= controller *ctlr, aml_spisg_pending(spisg, descs_paddr, false, true); if (wait_for_completion_timeout(&spisg->completion, spi_controller_is_target(spisg->controller) ? - MAX_SCHEDULE_TIMEOUT : msecs_to_jiffies(ms))) + MAX_SCHEDULE_TIMEOUT : msecs_to_jiffies(ms))) { ret =3D spisg->status ? -EIO : 0; - else + } else { + /* stop transfer */ + regmap_write(spisg->map, SPISG_REG_DESC_LIST_H, 0); ret =3D -ETIMEDOUT; + } =20 dma_unmap_single(dev, descs_paddr, descs_len, DMA_TO_DEVICE); end: --=20 2.52.0 From nobody Fri Jul 24 05:22:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A391A3CBE6E; Thu, 23 Jul 2026 06:43:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784789035; cv=none; b=EBGcqc79nzUfqxOFInJ0QOFbbYinUdIjlhTiUE/2sVw8sQFNLnKyHnkaelXSy21a31ZXqF3qrnQoDf9et8ptsSa8oaG1flE1QBM7a3pfaPbz3u/plyJDF8WoYZsApsMjUxBDp1f8yokk9e2hmSlKYT43aHfmcviEXDzhvdfdXpg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784789035; c=relaxed/simple; bh=3M0OnshwTVK0UfKz0PIBYXEPXb40nt8Uug0ad6cJ1QQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tK76l2hTKrUr2IrEk9woRkoxsUpB+JqXJYaFQPFg7dvVGv1cEK0rQH1qwfoY6A0hL1V+a32zzvlLCI9hu/UijjLr42dZTGQyfsmmaOmjpZZY/pq7mrgHz6y4QicZKGf7cDy4PulCY5uRFxaqSEpM/hBVYhYyT1uRreSx3tdKYbE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lIADCJSw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lIADCJSw" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6D02FC2BCFA; Thu, 23 Jul 2026 06:43:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784789035; bh=3M0OnshwTVK0UfKz0PIBYXEPXb40nt8Uug0ad6cJ1QQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lIADCJSwav7DYdpcWivV1Dg/XPEDiN5pi2yJW7lIKgA21mhJnLPmbUgeU8J1HMoOI sppOwplMU3MRVwrihcyqXfLJKGbwbmuoIRPBzOjt1pQ+wu4WwDfJrDmd8j0W7OUPXC 4pugB8A8wHwcLeVCfirAloViNJ0Jkm2DTREzz6tybNoz8IW04XsVp6xggtMTmPhu3i X9Kp3Mm0sI1Z5YDi36CtCKnQMfa2rOyIUb83cTWfVlt/vKzaDt6si+98+zw40yZ4/y h41qpu1AlOG8Y28cRPyF0vRW5b07oW9CRLUkn9X2Aj0XHiFoMiPYzNKjyAFUliyfsi fUR7i8T1nno/Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55C4AC531C7; Thu, 23 Jul 2026 06:43:55 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Thu, 23 Jul 2026 06:43:44 +0000 Subject: [PATCH v2 3/4] spi: amlogic: spisg: Fix the incorrect keep_ss of the last descriptor Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-a9-spisg-v2-3-9fc39106b7e2@amlogic.com> References: <20260723-a9-spisg-v2-0-9fc39106b7e2@amlogic.com> In-Reply-To: <20260723-a9-spisg-v2-0-9fc39106b7e2@amlogic.com> To: Sunny Luo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784789030; l=2503; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=GYCmSYjNwUITh84G97V/SeftRuFlV+MEyMTKnf7GhHw=; b=GkR8HB8K1/PECYh7EuOrs6MPtpCN5QXiQFktK4qOkKRr/LKpLJqc1a5JrBW22QjHi87Vefd/y zNFBqbugbMQAjC3YXxBrkGEO2zthU2go/HYM7SMI+0Fr9nm0vw8V06W X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Sunny Luo The driver currently unconditionally clears CFG_KEEP_SS on the last descriptor, causing the last transfer's cs_change setting to be ignored. Record the cs_change value of the last SPI transfer and use it to program CFG_KEEP_SS on the final descriptor. When a null descriptor is inserted to implement the cs-hold delay, keep CFG_KEEP_SS set on the preceding transfer descriptor and apply the recorded value to the final descriptor instead. This ensures the controller handles chip select correctly for the last transfer regardless of whether a cs-hold delay is required. Fixes: cef9991e04ae ("spi: Add Amlogic SPISG driver") Signed-off-by: Sunny Luo Signed-off-by: Xianwei Zhao --- drivers/spi/spi-amlogic-spisg.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-amlogic-spisg.c b/drivers/spi/spi-amlogic-spis= g.c index a6123975a37c..2d66f00dccd4 100644 --- a/drivers/spi/spi-amlogic-spisg.c +++ b/drivers/spi/spi-amlogic-spisg.c @@ -489,6 +489,7 @@ static int aml_spisg_transfer_one_message(struct spi_co= ntroller *ctlr, struct spisg_descriptor_extra *exdescs, *exdesc; dma_addr_t descs_paddr; int desc_num =3D 1, descs_len; + bool last_xfer_keep_ss =3D false; u32 cs_hold_in_sclk =3D 0; int ret =3D -EIO; =20 @@ -529,9 +530,11 @@ static int aml_spisg_transfer_one_message(struct spi_c= ontroller *ctlr, spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_setup)); =20 /* calculate cs-hold delay with the last xfer speed */ - if (list_is_last(&xfer->transfer_list, &msg->transfers)) + if (list_is_last(&xfer->transfer_list, &msg->transfers)) { cs_hold_in_sclk =3D spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_hold); + last_xfer_keep_ss =3D xfer->cs_change; + } =20 desc++; exdesc++; @@ -539,13 +542,17 @@ static int aml_spisg_transfer_one_message(struct spi_= controller *ctlr, xfer->effective_speed_hz); } =20 - if (cs_hold_in_sclk) + if (cs_hold_in_sclk) { /* additional null-descriptor to achieve the cs-hold delay */ aml_spisg_setup_null_desc(spisg, desc, cs_hold_in_sclk); - else desc--; + desc->cfg_bus |=3D FIELD_PREP(CFG_KEEP_SS, 1); + desc++; + } else { + desc--; + } =20 - desc->cfg_bus |=3D FIELD_PREP(CFG_KEEP_SS, 0); + FIELD_MODIFY(CFG_KEEP_SS, &desc->cfg_bus, last_xfer_keep_ss); desc->cfg_start |=3D FIELD_PREP(CFG_EOC, 1); =20 /* some tolerances */ --=20 2.52.0 From nobody Fri Jul 24 05:22:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3C173CC33F; Thu, 23 Jul 2026 06:43:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260723-a9-spisg-v2-4-9fc39106b7e2@amlogic.com> References: <20260723-a9-spisg-v2-0-9fc39106b7e2@amlogic.com> In-Reply-To: <20260723-a9-spisg-v2-0-9fc39106b7e2@amlogic.com> To: Sunny Luo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784789030; l=6028; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=+sHLM5KHnFgal4bJsOQhyDzBnE2r1DLRam3LKrrD878=; b=647ZoW8TN4KgZ4LDFaWGL3ZKtVNtDGU4Tqp+2IwTa3zNaIBLOd9J1n71J3IRvBtfnIO9ijVxY p90XV/UsiQdCwT28FSO0gxhQ0+6csNSpLxGHoZvfUZUQZockStSUEHd X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao The Amlogic A9 SPISG controller extends the A4 controller with additional configuration options, including: - Extended CS setup timing - Hardware-controlled CS hold timing - MOSI idle output configuration - Configurable word gap Add SoC-specific capability data and configure these features when they are supported by the underlying hardware while keeping compatibility with existing A4 controllers. Signed-off-by: Xianwei Zhao --- drivers/spi/spi-amlogic-spisg.c | 66 +++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 62 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-amlogic-spisg.c b/drivers/spi/spi-amlogic-spis= g.c index 2d66f00dccd4..bc9564aef245 100644 --- a/drivers/spi/spi-amlogic-spisg.c +++ b/drivers/spi/spi-amlogic-spisg.c @@ -37,6 +37,12 @@ #define CFG_HW_POS BIT(6) /* start on vsync falling */ #define CFG_HW_NEG BIT(7) +#define CFG_WORD_GAP GENMASK(9, 8) +#define CFG_MO_IDLE_OUTPUT GENMASK(11, 10) +/* cs hold time in pclk */ +#define CFG_CS_HOLD GENMASK(26, 12) +/* high 4 bits of cs setup time in sclk */ +#define CFG_CS_SETUP_EXTEND GENMASK(30, 27) =20 #define SPISG_REG_CFG_START 0x08 #define CFG_BLOCK_NUM GENMASK(19, 0) @@ -143,6 +149,13 @@ struct spisg_descriptor_extra { int rx_ccsg_len; }; =20 +struct aml_spisg_data { + bool mo_idle_output_ctrl; + bool word_gap_ctrl; + bool cs_hold_ctrl; + bool cs_setup_extend_ctrl; +}; + struct spisg_device { struct spi_controller *controller; struct platform_device *pdev; @@ -152,6 +165,7 @@ struct spisg_device { struct clk *sclk; struct clk_div_table *tbl; struct completion completion; + const struct aml_spisg_data *data; u32 status; u32 speed_hz; u32 effective_speed_hz; @@ -483,6 +497,7 @@ static int aml_spisg_transfer_one_message(struct spi_co= ntroller *ctlr, { struct spisg_device *spisg =3D spi_controller_get_devdata(ctlr); struct device *dev =3D &spisg->pdev->dev; + const struct aml_spisg_data *data =3D spisg->data; unsigned long long ms =3D 0; struct spi_transfer *xfer; struct spisg_descriptor *descs, *desc; @@ -491,6 +506,7 @@ static int aml_spisg_transfer_one_message(struct spi_co= ntroller *ctlr, int desc_num =3D 1, descs_len; bool last_xfer_keep_ss =3D false; u32 cs_hold_in_sclk =3D 0; + u32 val; int ret =3D -EIO; =20 if (!aml_spisg_sem_down_read(spisg)) { @@ -525,9 +541,17 @@ static int aml_spisg_transfer_one_message(struct spi_c= ontroller *ctlr, } =20 /* calculate cs-setup delay with the first xfer speed */ - if (list_is_first(&xfer->transfer_list, &msg->transfers)) - desc->cfg_bus |=3D FIELD_PREP(CFG_CS_SETUP, - spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_setup)); + if (list_is_first(&xfer->transfer_list, &msg->transfers)) { + val =3D spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_setup= ); + if (data && data->cs_setup_extend_ctrl) { + val =3D min_t(u32, 0xFF, val); + desc->cfg_bus |=3D FIELD_PREP(CFG_CS_SETUP, val & 0xF); + FIELD_MODIFY(CFG_CS_SETUP_EXTEND, &spisg->cfg_spi, val >> 4); + } else { + val =3D min_t(u32, 0xF, val); + desc->cfg_bus |=3D FIELD_PREP(CFG_CS_SETUP, val); + } + } =20 /* calculate cs-hold delay with the last xfer speed */ if (list_is_last(&xfer->transfer_list, &msg->transfers)) { @@ -542,7 +566,13 @@ static int aml_spisg_transfer_one_message(struct spi_c= ontroller *ctlr, xfer->effective_speed_hz); } =20 - if (cs_hold_in_sclk) { + if (data && data->cs_hold_ctrl) { + cs_hold_in_sclk =3D cs_hold_in_sclk ? : 1; + val =3D cs_hold_in_sclk * (FIELD_GET(CFG_CLK_DIV, spisg->cfg_bus) + 1); + val =3D min_t(u32, 0x7FFF, val); + FIELD_MODIFY(CFG_CS_HOLD, &spisg->cfg_spi, val); + desc--; + } else if (cs_hold_in_sclk) { /* additional null-descriptor to achieve the cs-hold delay */ aml_spisg_setup_null_desc(spisg, desc, cs_hold_in_sclk); desc--; @@ -725,6 +755,7 @@ static int aml_spisg_probe(struct platform_device *pdev) struct spisg_device *spisg; struct device *dev =3D &pdev->dev; void __iomem *base; + u32 val =3D 0; int ret, irq; =20 const struct regmap_config aml_regmap_config =3D { @@ -743,6 +774,7 @@ static int aml_spisg_probe(struct platform_device *pdev) =20 spisg =3D spi_controller_get_devdata(ctlr); spisg->controller =3D ctlr; + spisg->data =3D (struct aml_spisg_data *)of_device_get_match_data(dev); =20 spisg->pdev =3D pdev; platform_set_drvdata(pdev, spisg); @@ -773,6 +805,21 @@ static int aml_spisg_probe(struct platform_device *pde= v) =20 spisg->cfg_spi =3D FIELD_PREP(CFG_SFLASH_WP, 1) | FIELD_PREP(CFG_SFLASH_HD, 1); + + if (spisg->data && spisg->data->mo_idle_output_ctrl) { + if (!of_property_read_u32(dev->of_node, "amlogic,mo-idle-output", &val)) + spisg->cfg_spi |=3D FIELD_PREP(CFG_MO_IDLE_OUTPUT, val); + else + spisg->cfg_spi |=3D FIELD_PREP(CFG_MO_IDLE_OUTPUT, 0); + } + + if (spisg->data && spisg->data->word_gap_ctrl) { + if (!of_property_read_u32(dev->of_node, "amlogic,word-gap", &val)) + spisg->cfg_spi |=3D FIELD_PREP(CFG_WORD_GAP, val); + else + spisg->cfg_spi |=3D FIELD_PREP(CFG_WORD_GAP, 1); + } + if (spi_controller_is_target(ctlr)) { spisg->cfg_spi |=3D FIELD_PREP(CFG_SLAVE_EN, 1); spisg->cfg_bus =3D FIELD_PREP(CFG_TX_TUNING, 0xf); @@ -859,6 +906,13 @@ static int spisg_resume_runtime(struct device *dev) return 0; } =20 +static const struct aml_spisg_data a9_spisg_data =3D { + .mo_idle_output_ctrl =3D true, + .word_gap_ctrl =3D true, + .cs_hold_ctrl =3D true, + .cs_setup_extend_ctrl =3D true, +}; + static const struct dev_pm_ops amlogic_spisg_pm_ops =3D { .runtime_suspend =3D spisg_suspend_runtime, .runtime_resume =3D spisg_resume_runtime, @@ -868,6 +922,10 @@ static const struct of_device_id amlogic_spisg_of_matc= h[] =3D { { .compatible =3D "amlogic,a4-spisg", }, + { + .compatible =3D "amlogic,a9-spisg", + .data =3D &a9_spisg_data, + }, =20 { /* sentinel */ } }; --=20 2.52.0