From nobody Fri Jul 24 22:18:42 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0951F439F62 for ; Wed, 22 Jul 2026 20:34:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784752443; cv=none; b=aVKbRwm3xZK36K2TtAVhu5O6GW3iHTM+w0EdOPPMAY7XWEMLfRM6KMYKME4yiVoTQSakjQmNtS79g9uCx7zEOAg2JNPLftg3jBUb+XUGdNh3pS6YEI/m8DJYo5lmYJH93zFKWm6HdEuPmjUVR6Box9UxtJmTUY+4oKNJnQhlpX4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784752443; c=relaxed/simple; bh=H7gc8EHhrE54TIGFPE01knw9jDcZnFRii3hzkCBNdj4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l+L7xwEnGAR5LpWYrXx1i5p3wuwg9T7Lv/rWHfYgKNAztvO+0xy6Ij9Ko0L5L6wjMFELEIrRs9Y/FXwbHYHD78crfaWY4ILSSoXZEjvPMFC7nFnVUrmc1jPhflIr9PC1YKy9hgje7e2ZVG0pWWSggiwSqnxiqigIOi7fTBrZCdE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=T8J+vOW1; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="T8J+vOW1" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4954f5e8020so23675885e9.2 for ; Wed, 22 Jul 2026 13:34:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784752439; x=1785357239; darn=vger.kernel.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=xSx084TFnzGFnpguxyZxDPEBlEGv6khf3RChBzg4a7A=; b=T8J+vOW1WnvBTMuGrEM/5Z18gXbjghjBtLBxp+ynT0rH7LAt5xaG/LxBczsd8/4tuA 8IGt225FXOk+A76Osekdn/rTWIzX9eq3ix++pygsuk20qJIGl1QVhFIU/YFIpkhtpjrW ybn9OC42ivb+m43IpuntDgDhPl8vOyZ0t5jP/Eta5at6xGfsY87szQVOnp09P3XEo/BQ GuRjmQWSzH1cUVSrluA0rbQGGDDLB3b0L0Kxt6mrxYO8fEEhgKX5d6AtOtTZ85BZImrK yFpCpD/rjUWhTaNPpbXZPsD5OofHKO8unM9ChwPuiXO94PXgRpzNhRyMVPLzJ+TYkWps H7UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784752439; x=1785357239; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=xSx084TFnzGFnpguxyZxDPEBlEGv6khf3RChBzg4a7A=; b=tUl8mfz1sJbfz/3NxJeoaSm+GLwcV00kklE0TdXNT4b4o2oidzRlnRUTkwqC9PMGKG 3AawwKufgJxA7YXHfE0V4JJVLugnnwG1r9qeG9W6m4NRD0f3UonWiwfMtZBF7lWSz6EU cPvF+H9coaEOXPsE/X+RBUIbX5k08vSnkO7FpRtuNZJxok+xW0e5aQoKG4Q8pwORx/mi 3Y1FjfWcQtDUNDXni5baRIwlocVgoruT2N0Eoqf0u5tWIJLXf1HAvtwqOmGKhv0YzRzM O4D41RNyUsl4edkNUwlluQv1R+q8CCEmgO2jNmDQs1dJevYLiEJrEF+4qpqjp5FmuGh1 9oCQ== X-Forwarded-Encrypted: i=1; AHgh+Rot7TRM3kMMiJb86jpf/SjQ9ScJrA0u4/XQxdsYuMKarTU46ordZ6OSEKntxDSsolcshxjpCbkiXpgHHWE=@vger.kernel.org X-Gm-Message-State: AOJu0YzDYhbPBAKyLMOuaIeKFY+PCLPsRAuHGMv/4xLRXvgQ9Ra19yZ6 TdetyRSDbfikvR8KXahlt1R/gipcSC4qGhNm2fozxg/Dmviv7jqo47B0 X-Gm-Gg: AR+sD10HFIchNAg7t5StvjP6/TzcFY3fYsyH3Nfbz9cSRK6i06G+nSK0jwO1bU3sM4a 3vaYppkgPvpsZCjed7SGhGJKJM9P8xb3F8/uD0/ePjnHXfEqH1nLB0dyDT6CAMb1kTA50HGaaHV qgoDdjKl2Q2c8qbY5efx+a9u8GkiV4RMnb2mgHdKMPhpqGkyAYPA94beTnzxVRoAjJ7nG3spjcJ CHiIsYjE3s8zeeJgh/4J5AXsYcX11WU/7gJEHNX2fqRRW7XCVML26qgPH5Tylvi5dpztzTMYtUe BNdK/8Yzdl/QaDFzyWPSeIcOH2tFZZqT5kWWggimf0YIejVSFQnESbV2wxtFvxKlqmqXA/O80GS S8qas0YBy0qG28d6FAUpf8PNOKDXD0s7XqhxIEDh4uu0aSa9DUqGvIXZNAmUkzlso5s07QQ4NAX rcKeBJ3Y/De7emfbYj/YU9GBxk X-Received: by 2002:a05:600c:3152:b0:495:3fe1:4ce4 with SMTP id 5b1f17b1804b1-49573ce8ef3mr3009655e9.26.1784752438954; Wed, 22 Jul 2026 13:33:58 -0700 (PDT) Received: from coolemuke.fritz.box ([2a00:6020:b320:1a00:c256:1463:a40b:d8c6]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4956ab2f0a2sm63134945e9.1.2026.07.22.13.33.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 13:33:58 -0700 (PDT) From: "=?UTF-8?q?S=C3=B6ren=20Hantel?=" X-Google-Original-From: =?UTF-8?q?S=C3=B6ren=20Hantel?= To: linux-pm@vger.kernel.org Cc: Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Rossak , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, =?UTF-8?q?S=C3=B6ren=20Hantel?= , Claude Fable 5 Subject: [PATCH 1/3] dt-bindings: thermal: sun8i: Add binding for the A80 THS controller Date: Wed, 22 Jul 2026 22:33:39 +0200 Message-ID: <20260722203341.2917852-2-fugininsane@googlemail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260722203341.2917852-1-fugininsane@googlemail.com> References: <20260722203341.2917852-1-fugininsane@googlemail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The Allwinner A80 has a thermal sensor with four channels which shares its MMIO block, bus gate, module clock and reset line with the GPADC. Register-wise it is an early version of the THS found in the A83T and later SoCs, with the THS registers starting at offset 0x40 of the shared block. Add the compatible to the sun8i THS binding. The A80 takes a bus and a module clock plus a reset line, so the existing conditionals already describe it correctly. Co-authored-by: Claude Fable 5 Signed-off-by: S=C3=B6ren Hantel --- .../devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t= -ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-= ths.yaml index 3e61689..718c44d 100644 --- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.ya= ml +++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.ya= ml @@ -18,6 +18,7 @@ properties: - allwinner,sun8i-a83t-ths - allwinner,sun8i-h3-ths - allwinner,sun8i-r40-ths + - allwinner,sun9i-a80-ths - allwinner,sun20i-d1-ths - allwinner,sun50i-a64-ths - allwinner,sun50i-a100-ths --=20 2.43.0 From nobody Fri Jul 24 22:18:42 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3421543B6EC for ; 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Wed, 22 Jul 2026 13:34:00 -0700 (PDT) Received: from coolemuke.fritz.box ([2a00:6020:b320:1a00:c256:1463:a40b:d8c6]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4956ab2f0a2sm63134945e9.1.2026.07.22.13.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 13:33:59 -0700 (PDT) From: "=?UTF-8?q?S=C3=B6ren=20Hantel?=" X-Google-Original-From: =?UTF-8?q?S=C3=B6ren=20Hantel?= To: linux-pm@vger.kernel.org Cc: Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Rossak , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, =?UTF-8?q?S=C3=B6ren=20Hantel?= , Claude Fable 5 Subject: [PATCH 2/3] thermal/drivers/sun8i: Add support for the A80 THS Date: Wed, 22 Jul 2026 22:33:40 +0200 Message-ID: <20260722203341.2917852-3-fugininsane@googlemail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260722203341.2917852-1-fugininsane@googlemail.com> References: <20260722203341.2917852-1-fugininsane@googlemail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The Allwinner A80 thermal sensor is an early relative of the THS found in the A83T and later SoCs. It shares its register block, bus gate, 4 MHz module clock and reset line with the GPADC; the THS registers live at offset 0x40 of the shared block, with four data registers for the four sensors (0: big cluster, 1: DRAM, 2: GPU, 3: little cluster). Register layout, initialization values and the temperature formula (T =3D 190 - raw * 1000 / 14543, i.e. offset 190000 / scale 688 in this driver's convention) are taken from the vendor BSP kernel. The init sequence also programs the hardware alarm (~90 degC) and emergency shutdown (~105 degC) thresholds the BSP uses, since their reset defaults are undefined. Unlike on later SoCs the data-ready interrupt fires at the conversion rate (tens of kHz), so it is left disabled and the thermal core polls the sensors; the interrupt line only serves the alarm and shutdown events, matching the vendor BSP behaviour. The A80 SID is not yet supported by the sunxi nvmem driver, so calibration data is currently unavailable and the driver falls back to the defaults, which yield plausible results (idle temperatures around 40 degC, full-load peaks in the mid 50s on a Cubieboard4). Tested on a Cubietech Cubieboard4: all four zones report load-reactive temperatures via polling. Co-authored-by: Claude Fable 5 Signed-off-by: S=C3=B6ren Hantel --- drivers/thermal/sun8i_thermal.c | 93 ++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_therma= l.c index 2267479..3e7bfda 100644 --- a/drivers/thermal/sun8i_thermal.c +++ b/drivers/thermal/sun8i_thermal.c @@ -65,8 +65,27 @@ struct tsensor { int id; }; =20 +/* + * The A80 thermal sensor shares its register block with the GPADC. + * The THS registers start at offset 0x40 within that block. + */ +#define SUN9I_THS_CTRL 0x40 +#define SUN9I_THS_IC 0x44 +#define SUN9I_THS_IS 0x48 +#define SUN9I_THS_ALARM_TH(x) (0x50 + (x) * 0x4) +#define SUN9I_THS_SHUT_TH(x) (0x60 + (x) * 0x4) +#define SUN9I_THS_MFC 0x70 +#define SUN9I_THS_TEMP_DATA 0x80 +#define SUN9I_THS_CTRL_ACQ(x) ((x) << 16) +#define SUN9I_THS_CTRL_SENSOR_EN GENMASK(3, 0) +#define SUN9I_THS_ALARM_IRQ_EN GENMASK(3, 0) +#define SUN9I_THS_SHUT_IRQ_EN GENMASK(7, 4) +#define SUN9I_THS_ALARM_IRQ_STS(x) BIT(x) +#define SUN9I_THS_SHUT_IRQ_STS(x) BIT(4 + (x)) + struct ths_thermal_chip { bool has_mod_clk; + unsigned long mod_clk_rate; bool has_bus_clk_reset; bool needs_sram; int sensor_num; @@ -413,7 +432,8 @@ static int sun8i_ths_resource_init(struct ths_device *t= mdev) return PTR_ERR(tmdev->mod_clk); } =20 - ret =3D clk_set_rate(tmdev->mod_clk, 24000000); + ret =3D clk_set_rate(tmdev->mod_clk, tmdev->chip->mod_clk_rate ?: + 24000000); if (ret) return ret; =20 @@ -596,6 +616,76 @@ static int sun8i_ths_probe(struct platform_device *pde= v) return 0; } =20 +static int sun9i_a80_thermal_init(struct ths_device *tmdev) +{ + int i; + + /* clear any pending interrupt status */ + regmap_write(tmdev->regmap, SUN9I_THS_IS, 0xfff); + /* set up the median filter, average over 8 samples */ + regmap_write(tmdev->regmap, SUN9I_THS_MFC, 0x5); + + /* + * Program the protection thresholds with the values the vendor + * BSP uses (thresholds are in raw sensor units, which decrease + * with rising temperature): an alarm interrupt at ~90 degC and + * an emergency hardware shutdown at ~105 degC. + */ + for (i =3D 0; i < tmdev->chip->sensor_num; i++) { + regmap_write(tmdev->regmap, SUN9I_THS_ALARM_TH(i), + (1454 << 16) | 0xfff); + regmap_write(tmdev->regmap, SUN9I_THS_SHUT_TH(i), + (1231 << 16) | 0xfff); + } + + /* + * Unlike on later SoCs, the data-ready interrupt fires at the + * conversion rate (tens of kHz), so leave it disabled and let the + * thermal core poll the data registers; the interrupt line only + * serves the alarm and shutdown events, like in the vendor BSP. + */ + regmap_write(tmdev->regmap, SUN9I_THS_IC, + SUN9I_THS_ALARM_IRQ_EN | SUN9I_THS_SHUT_IRQ_EN); + /* acquire time 0x2f, enable all four sensors */ + regmap_write(tmdev->regmap, SUN9I_THS_CTRL, + SUN9I_THS_CTRL_ACQ(0x2f) | SUN9I_THS_CTRL_SENSOR_EN); + + return 0; +} + +static unsigned long sun9i_a80_irq_ack(struct ths_device *tmdev) +{ + unsigned long irq_bitmap =3D 0; + int i, state; + + regmap_read(tmdev->regmap, SUN9I_THS_IS, &state); + + for (i =3D 0; i < MAX_SENSOR_NUM; i++) { + if (state & (SUN9I_THS_ALARM_IRQ_STS(i) | + SUN9I_THS_SHUT_IRQ_STS(i))) { + regmap_write(tmdev->regmap, SUN9I_THS_IS, + state & (SUN9I_THS_ALARM_IRQ_STS(i) | + SUN9I_THS_SHUT_IRQ_STS(i))); + set_bit(i, &irq_bitmap); + } + } + + return irq_bitmap; +} + +static const struct ths_thermal_chip sun9i_a80_ths =3D { + .sensor_num =3D 4, + .has_mod_clk =3D true, + .mod_clk_rate =3D 4000000, + .has_bus_clk_reset =3D true, + .scale =3D 688, + .offset =3D 190000, + .temp_data_base =3D SUN9I_THS_TEMP_DATA, + .init =3D sun9i_a80_thermal_init, + .irq_ack =3D sun9i_a80_irq_ack, + .calc_temp =3D sun8i_ths_calc_temp, +}; + static const struct ths_thermal_chip sun8i_a83t_ths =3D { .sensor_num =3D 3, .scale =3D 705, @@ -711,6 +801,7 @@ static const struct ths_thermal_chip sun50i_h616_ths = =3D { =20 static const struct of_device_id of_ths_match[] =3D { { .compatible =3D "allwinner,sun8i-a83t-ths", .data =3D &sun8i_a83t_ths }, + { .compatible =3D "allwinner,sun9i-a80-ths", .data =3D &sun9i_a80_ths }, { .compatible =3D "allwinner,sun8i-h3-ths", .data =3D &sun8i_h3_ths }, { .compatible =3D "allwinner,sun8i-r40-ths", .data =3D &sun8i_r40_ths }, { .compatible =3D "allwinner,sun50i-a64-ths", .data =3D &sun50i_a64_ths }, --=20 2.43.0 From nobody Fri Jul 24 22:18:42 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 572E73E7BA9 for ; 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Wed, 22 Jul 2026 13:34:02 -0700 (PDT) Received: from coolemuke.fritz.box ([2a00:6020:b320:1a00:c256:1463:a40b:d8c6]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4956ab2f0a2sm63134945e9.1.2026.07.22.13.34.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 13:34:00 -0700 (PDT) From: "=?UTF-8?q?S=C3=B6ren=20Hantel?=" X-Google-Original-From: =?UTF-8?q?S=C3=B6ren=20Hantel?= To: linux-pm@vger.kernel.org Cc: Vasily Khoruzhick , Yangtao Li , "Rafael J . Wysocki" , Daniel Lezcano , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Rossak , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Claude Fable 5 , =?UTF-8?q?S=C3=B6ren=20Hantel?= Subject: [PATCH 3/3] ARM: dts: sun9i-a80: Add thermal sensor and thermal zones Date: Wed, 22 Jul 2026 22:33:41 +0200 Message-ID: <20260722203341.2917852-4-fugininsane@googlemail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260722203341.2917852-1-fugininsane@googlemail.com> References: <20260722203341.2917852-1-fugininsane@googlemail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Philipp Rossak Now that the A80 thermal sensor is supported, add its device node and the thermal zones to the device tree. The clocks and the resets are shared between the GPADC and the THS sensor. Sensor 0 is located beside the big CPU cluster, sensor 1 beside the DRAM controller, sensor 2 beside the GPU and sensor 3 beside the little CPU cluster. Signed-off-by: Philipp Rossak [soeren: rebased from the 2018 series, fixed the interrupt number (SPI 115 as in the vendor BSP; verified on hardware - SPI 31 stays silent), added critical trip points matching the driver's emergency shutdown threshold] Co-authored-by: Claude Fable 5 Signed-off-by: S=C3=B6ren Hantel --- arch/arm/boot/dts/allwinner/sun9i-a80.dtsi | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi b/arch/arm/boot/dts= /allwinner/sun9i-a80.dtsi index a1ae092..8e7f8cd 100644 --- a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi @@ -941,6 +941,16 @@ #reset-cells =3D <1>; }; =20 + ths: thermal-sensor@6004c00 { + compatible =3D "allwinner,sun9i-a80-ths"; + reg =3D <0x06004c00 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_GPADC>, <&ccu CLK_GPADC>; + clock-names =3D "bus", "mod"; + resets =3D <&ccu RST_BUS_GPADC>; + #thermal-sensor-cells =3D <1>; + }; + timer@6000c00 { compatible =3D "allwinner,sun4i-a10-timer"; reg =3D <0x06000c00 0xa0>; @@ -1250,4 +1260,62 @@ #size-cells =3D <0>; }; }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <5000>; + thermal-sensors =3D <&ths 0>; + + trips { + cpu0_crit: cpu0-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + dram_thermal: dram-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <5000>; + thermal-sensors =3D <&ths 1>; + + trips { + dram_crit: dram-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <5000>; + thermal-sensors =3D <&ths 2>; + + trips { + gpu_crit: gpu-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cpu2_thermal: cpu2-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <5000>; + thermal-sensors =3D <&ths 3>; + + trips { + cpu2_crit: cpu2-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + }; }; --=20 2.43.0