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charset="utf-8" Xilinx specific macros for MDB device can be reused for the Xilinx supported other similar IP such as CPM6. Renamed the Xilinx specific macros in a way that can be reused for Xilinx supported upcoming IP, CPM6. Naming is in accordance with the naming done for Synopsys macros. Signed-off-by: Devendra K Verma --- drivers/dma/dw-edma/dw-edma-pcie.c | 58 +++++++++++++++--------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 791c46e8ae4c..ec5e057a0f11 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -29,21 +29,21 @@ #define PCI_DEVICE_ID_XILINX_B054 0xb054 #define PCI_DEVICE_ID_XILINX_B00F 0xb00f =20 -#define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6 -#define DW_PCIE_XILINX_MDB_VSEC_ID 0x20 -#define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8) -#define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP GENMASK(2, 0) -#define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH GENMASK(9, 0) -#define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH GENMASK(25, 16) - -#define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH 0xc -#define DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW 0x8 -#define DW_PCIE_XILINX_MDB_INVALID_ADDR (~0ULL) - -#define DW_PCIE_XILINX_MDB_LL_OFF_GAP 0x200000 -#define DW_PCIE_XILINX_MDB_LL_SIZE 0x800 -#define DW_PCIE_XILINX_MDB_DT_OFF_GAP 0x100000 -#define DW_PCIE_XILINX_MDB_DT_SIZE 0x800 +#define DW_PCIE_XILINX_VSEC_DMA_ID 0x6 +#define DW_PCIE_XILINX_VSEC_ID 0x20 +#define DW_PCIE_XILINX_VSEC_DMA_BAR GENMASK(10, 8) +#define DW_PCIE_XILINX_VSEC_DMA_MAP GENMASK(2, 0) +#define DW_PCIE_XILINX_VSEC_DMA_WR_CH GENMASK(9, 0) +#define DW_PCIE_XILINX_VSEC_DMA_RD_CH GENMASK(25, 16) + +#define DW_PCIE_XILINX_DEVMEM_OFF_REG_HIGH 0xc +#define DW_PCIE_XILINX_DEVMEM_OFF_REG_LOW 0x8 +#define DW_PCIE_XILINX_INVALID_ADDR (~0ULL) + +#define DW_PCIE_XILINX_LL_OFF_GAP 0x200000 +#define DW_PCIE_XILINX_LL_SIZE 0x800 +#define DW_PCIE_XILINX_DT_OFF_GAP 0x100000 +#define DW_PCIE_XILINX_DT_SIZE 0x800 =20 #define DW_BLOCK(a, b, c) \ { \ @@ -258,10 +258,10 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct p= ci_dev *pdev, u16 vsec; u64 off; =20 - pdata->devmem_phys_off =3D DW_PCIE_XILINX_MDB_INVALID_ADDR; + pdata->devmem_phys_off =3D DW_PCIE_XILINX_INVALID_ADDR; =20 vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX, - DW_PCIE_XILINX_MDB_VSEC_DMA_ID); + DW_PCIE_XILINX_VSEC_DMA_ID); if (!vsec) return; =20 @@ -272,18 +272,18 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct p= ci_dev *pdev, =20 pci_dbg(pdev, "Detected Xilinx PCIe Vendor-Specific Extended Capability D= MA\n"); pci_read_config_dword(pdev, vsec + 0x8, &val); - map =3D FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_MAP, val); + map =3D FIELD_GET(DW_PCIE_XILINX_VSEC_DMA_MAP, val); if (map !=3D EDMA_MF_HDMA_NATIVE) return; =20 pdata->mf =3D map; - pdata->rg.bar =3D FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_BAR, val); + pdata->rg.bar =3D FIELD_GET(DW_PCIE_XILINX_VSEC_DMA_BAR, val); =20 pci_read_config_dword(pdev, vsec + 0xc, &val); pdata->wr_ch_cnt =3D min(pdata->wr_ch_cnt, - FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH, val)); + FIELD_GET(DW_PCIE_XILINX_VSEC_DMA_WR_CH, val)); pdata->rd_ch_cnt =3D min(pdata->rd_ch_cnt, - FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH, val)); + FIELD_GET(DW_PCIE_XILINX_VSEC_DMA_RD_CH, val)); =20 pci_read_config_dword(pdev, vsec + 0x14, &val); off =3D val; @@ -293,16 +293,16 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct p= ci_dev *pdev, pdata->rg.off =3D off; =20 vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_XILINX, - DW_PCIE_XILINX_MDB_VSEC_ID); + DW_PCIE_XILINX_VSEC_ID); if (!vsec) return; =20 pci_read_config_dword(pdev, - vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_HIGH, + vsec + DW_PCIE_XILINX_DEVMEM_OFF_REG_HIGH, &val); off =3D val; pci_read_config_dword(pdev, - vsec + DW_PCIE_XILINX_MDB_DEVMEM_OFF_REG_LOW, + vsec + DW_PCIE_XILINX_DEVMEM_OFF_REG_LOW, &val); off <<=3D 32; off |=3D val; @@ -360,7 +360,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, * address use the non-LL mode or simple mode supported by * the HDMA IP. */ - if (vsec_data->devmem_phys_off =3D=3D DW_PCIE_XILINX_MDB_INVALID_ADDR) + if (vsec_data->devmem_phys_off =3D=3D DW_PCIE_XILINX_INVALID_ADDR) non_ll =3D true; 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charset="utf-8" As per, 'Designware Cores PCI Express DM Controller - Reference Manual', section 3.2.34.3, VSEC for DEVICE INFORMATION supports the channel separation mechanisms. Basically, the HDMA IP allows the user to configure the separation between DMA channel registers and retrieve it via the VSEC capability mentioned above. HDMA IP supports the channel separation up to 32K but for the simplicity channel separation support has been added till 4K. As and when required the function can be expanded to include the higher sizes for channel separation. Supported and missed out sizes are: 8K (0x5), 16K (0x6), 32K (0x7) Signed-off-by: Devendra K Verma --- drivers/dma/dw-edma/dw-edma-pcie.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index ec5e057a0f11..6295d01ba2f7 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -33,6 +33,7 @@ #define DW_PCIE_XILINX_VSEC_ID 0x20 #define DW_PCIE_XILINX_VSEC_DMA_BAR GENMASK(10, 8) #define DW_PCIE_XILINX_VSEC_DMA_MAP GENMASK(2, 0) +#define DW_PCIE_XILINX_VSEC_CH_SEP GENMASK(18, 16) #define DW_PCIE_XILINX_VSEC_DMA_WR_CH GENMASK(9, 0) #define DW_PCIE_XILINX_VSEC_DMA_RD_CH GENMASK(25, 16) =20 @@ -73,6 +74,7 @@ struct dw_edma_pcie_data { u16 wr_ch_cnt; u16 rd_ch_cnt; u64 devmem_phys_off; + u32 ch_sep_sz; }; =20 static const struct dw_edma_pcie_data snps_edda_data =3D { @@ -127,7 +129,7 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = =3D { }; =20 static const struct dw_edma_pcie_data xilinx_cpm6_dma_data =3D { - /* MDB registers location */ + /* CPM6 registers location */ .rg.bar =3D BAR_0, .rg.off =3D SZ_4K, /* 4 Kbytes */ .rg.sz =3D SZ_8K, /* 8 Kbytes */ @@ -189,6 +191,23 @@ static int dw_edma_pcie_irq_vector(struct device *dev,= unsigned int nr) return pci_irq_vector(to_pci_dev(dev), nr); } =20 +static u32 dw_edma_get_ch_sep_sz(u32 ch_sep_val) +{ + switch (ch_sep_val) { + default: + case 0: + return 256; + case 1: + return 512; + case 2: + return 1024; + case 3: + return 2048; + case 4: + return 4096; + } +} + static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr) { struct pci_dev *pdev =3D to_pci_dev(dev); @@ -278,6 +297,8 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pci= _dev *pdev, =20 pdata->mf =3D map; pdata->rg.bar =3D FIELD_GET(DW_PCIE_XILINX_VSEC_DMA_BAR, val); + pdata->ch_sep_sz =3D dw_edma_get_ch_sep_sz(FIELD_GET(DW_PCIE_XILINX_VSEC_= CH_SEP, + val)); =20 pci_read_config_dword(pdev, vsec + 0xc, &val); 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charset="utf-8" Following changes are made: o In 'struct dw_hdma_v0_ch_regs', it is assumed the channel separation as 256-bytes which is default, but if an IP is configured for a different size of channel separation then user can retrieve it using the supported VSEC (0x6). Modified the struct to work with the channel separation supported by IP. CPM6 supports channel separation, default is 512. o Changes in macros / functions where address of the channel is accessed based on channel index and direction. It enables the calculation of the channel reg base address based on the selected channel separation. o Struct removed - dw_hdma_v0_ch, dw_hdma_v0_regs o Functions removed - __dw_regs() Signed-off-by: Devendra K Verma --- drivers/dma/dw-edma/dw-edma-pcie.c | 4 ++++ drivers/dma/dw-edma/dw-hdma-v0-core.c | 23 ++++++++++++++--------- drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 17 ++++++----------- drivers/dma/dw-edma/dw-hdma-v0-regs.h | 10 ---------- include/linux/dma/edma.h | 1 + 5 files changed, 25 insertions(+), 30 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 6295d01ba2f7..ca2a4be2f3a5 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -113,6 +113,7 @@ static const struct dw_edma_pcie_data snps_edda_data = =3D { .irqs =3D 1, .wr_ch_cnt =3D 2, .rd_ch_cnt =3D 2, + .ch_sep_sz =3D 256, }; =20 static const struct dw_edma_pcie_data xilinx_mdb_data =3D { @@ -126,6 +127,7 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = =3D { .irqs =3D 1, .wr_ch_cnt =3D 8, .rd_ch_cnt =3D 8, + .ch_sep_sz =3D 256, }; =20 static const struct dw_edma_pcie_data xilinx_cpm6_dma_data =3D { @@ -139,6 +141,7 @@ static const struct dw_edma_pcie_data xilinx_cpm6_dma_d= ata =3D { .irqs =3D 1, .wr_ch_cnt =3D 8, .rd_ch_cnt =3D 8, + .ch_sep_sz =3D 512, }; =20 static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata, @@ -443,6 +446,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->nr_irqs =3D nr_irqs; chip->ops =3D &dw_edma_pcie_plat_ops; chip->cfg_non_ll =3D non_ll; + chip->ch_sep_sz =3D vsec_data->ch_sep_sz; =20 chip->ll_wr_cnt =3D vsec_data->wr_ch_cnt; chip->ll_rd_cnt =3D vsec_data->rd_ch_cnt; diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index 632abb8b481c..3f27a93c4d8c 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -23,18 +23,23 @@ enum dw_hdma_control { DW_HDMA_V0_LLE =3D BIT(9), }; =20 -static inline struct dw_hdma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) -{ - return dw->chip->reg_base; -} - static inline struct dw_hdma_v0_ch_regs __iomem * __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch) { - if (dir =3D=3D EDMA_DIR_WRITE) - return &(__dw_regs(dw)->ch[ch].wr); - else - return &(__dw_regs(dw)->ch[ch].rd); + u32 ch_base; + + /* + * For Write, the channel register index starts at + * wr_base(ch_idx) =3D (2 * ch_idx) * ch_sep_sz + * + * For Read channel, + * rd_base(ch_idx) =3D (2 * ch_idx + 1) * ch_sep_sz + */ + ch_base =3D 2 * ch; + if (dir =3D=3D EDMA_DIR_READ) + ch_base +=3D 1; + + return dw->chip->reg_base + (ch_base * dw->chip->ch_sep_sz); } =20 #define SET_CH_32(dw, dir, ch, name, value) \ diff --git a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c b/drivers/dma/dw-edma= /dw-hdma-v0-debugfs.c index dcdc57fe976c..33128685bbd9 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c @@ -13,22 +13,17 @@ #include "dw-hdma-v0-regs.h" #include "dw-edma-core.h" =20 -#define REGS_ADDR(dw, name) \ - ({ \ - struct dw_hdma_v0_regs __iomem *__regs =3D (dw)->chip->reg_base; \ - \ - (void __iomem *)&__regs->name; \ - }) - #define REGS_CH_ADDR(dw, name, _dir, _ch) \ ({ \ - struct dw_hdma_v0_ch_regs __iomem *__ch_regs; \ + struct dw_hdma_v0_ch_regs __iomem *__ch_regs; \ + off_t __off =3D (dw)->chip->ch_sep_sz; \ \ - if (_dir =3D=3D EDMA_DIR_READ) \ - __ch_regs =3D REGS_ADDR(dw, ch[_ch].rd); \ + if ((_dir) =3D=3D EDMA_DIR_READ) \ + __off *=3D (2 * (_ch) + 1); \ else \ - __ch_regs =3D REGS_ADDR(dw, ch[_ch].wr); \ + __off *=3D (2 * (_ch)); \ \ + __ch_regs =3D ((dw)->chip->reg_base + __off); \ (void __iomem *)&__ch_regs->name; \ }) =20 diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw= -hdma-v0-regs.h index 7759ba9b4850..2475b8d96133 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h @@ -84,16 +84,6 @@ struct dw_hdma_v0_ch_regs { }; } msi_abort; u32 msi_msgdata; /* 0x00a8 */ - u32 padding_2[21]; /* 0x00ac..0x00fc */ -} __packed; - -struct dw_hdma_v0_ch { - struct dw_hdma_v0_ch_regs wr; /* 0x0000 */ - struct dw_hdma_v0_ch_regs rd; /* 0x0100 */ -} __packed; - -struct dw_hdma_v0_regs { - struct dw_hdma_v0_ch ch[HDMA_V0_MAX_NR_CH]; /* 0x0000..0x0fa8 */ } __packed; =20 struct dw_hdma_v0_lli { diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 1fafd5b0e315..a6c5728f03d3 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -104,6 +104,7 @@ struct dw_edma_chip { =20 struct dw_edma *dw; bool cfg_non_ll; + u32 ch_sep_sz; }; =20 /* Export to the platform drivers */ --=20 2.43.0