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Wed, 22 Jul 2026 09:46:18 -0700 (PDT) From: Bhargav Joshi Date: Wed, 22 Jul 2026 22:15:54 +0530 Subject: [PATCH v2] dt-bindings: pinctrl: ti,dra7-iodelay: Convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260722-ti-iodelay-v2-1-995f55f605bf@gmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/03MQQqDMBCF4avIrJuSRDvSrrxHcRGSiQ6oKYlIR XL3ptJFl/+D9x2QKDIleFQHRNo4cVhK6EsFdjTLQIJdadBSo2wlipUFB0eT2YVG397R28ajh3J 4RfL8PrFnX3rktIa4n/amvuuPUfU/symhxM1LdDXaxhjbDbPh6WrDDH3O+QNXsZBzpAAAAA== X-Change-ID: 20260706-ti-iodelay-26f796fc4f6f To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, goledhruva@gmail.com, m-chawdhry@ti.com, daniel.baluta@gmail.com, simona.toaca@nxp.com, j.bhargav.u@gmail.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784738769; l=5450; i=j.bhargav.u@gmail.com; h=from:subject:message-id; bh=vbUaQgLr8MujYHQ5b5L4HHRWyH6HlD6i/56H/NwdBJw=; b=rEU0i1BziL3CY0uUPYI8Q4A7fXhen3llw9rlXnVMuf5jobLvgA1LKrAKEhRW/j4d1pDbPTsxN ARQAzRBuqfIBuhpgREizy1wY8EY12fvT+WKr/JdFsQh8IupSn6DJdte X-Developer-Key: i=j.bhargav.u@gmail.com; a=ed25519; pk=IqNDwUZKECEA+n8wXctFLBbYL9NhFstZNbOznm/nX1k= Convert TI IODELAY controller from text to DT schema. Document child properties missing from text bindings for proper validation. Signed-off-by: Bhargav Joshi --- Changes in v2: - Add pinctrl-pin-array as required for child node - Support generic child node that ends with _conf - Link to v1: https://lore.kernel.org/r/20260713-ti-iodelay-v1-1-5f06d36c4a= ac@gmail.com --- .../bindings/pinctrl/ti,dra7-iodelay.yaml | 83 ++++++++++++++++++= ++++ .../devicetree/bindings/pinctrl/ti,iodelay.txt | 47 ------------ 2 files changed, 83 insertions(+), 47 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ti,dra7-iodelay.yaml= b/Documentation/devicetree/bindings/pinctrl/ti,dra7-iodelay.yaml new file mode 100644 index 000000000000..a798552c1ac2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,dra7-iodelay.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ti,dra7-iodelay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pin configuration for TI IODELAY controller + +maintainers: + - Nishanth Menon + - Bhargav Joshi + +description: + TI dra7 based SoCs such as am57xx have a controller for setting the IO d= elay + for each pin. For most part the IO delay values are programmed by the + bootloader, but some pins need to be configured dynamically by the kerne= l such + as the MMC pins. + +properties: + compatible: + const: ti,dra7-iodelay + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#pinctrl-cells': + const: 2 + +patternProperties: + ^.*_conf$: + type: object + additionalProperties: false + + properties: + pinctrl-pin-array: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of 32-bit integers defining the pin delay configuration. + + required: + - pinctrl-pin-array + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - '#pinctrl-cells' + +additionalProperties: false + +examples: + - | + #include + + padconf@4844a000 { + compatible =3D "ti,dra7-iodelay"; + reg =3D <0x4844a000 0x0d1c>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #pinctrl-cells =3D <2>; + + mmc2_iodelay_3v3_conf { + pinctrl-pin-array =3D < + 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ + 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ + 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ + 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ + 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ + 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ + 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ + 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ + 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ + 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ + >; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt b/Doc= umentation/devicetree/bindings/pinctrl/ti,iodelay.txt deleted file mode 100644 index c3ed1232b6a3..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Pin configuration for TI IODELAY controller - -TI dra7 based SoCs such as am57xx have a controller for setting the IO del= ay -for each pin. For most part the IO delay values are programmed by the boot= loader, -but some pins need to be configured dynamically by the kernel such as the -MMC pins. - -Required Properties: - - - compatible: Must be "ti,dra7-iodelay" - - reg: Base address and length of the memory resource used - - #address-cells: Number of address cells - - #size-cells: Size of cells - - #pinctrl-cells: Number of pinctrl cells, must be 2. See also - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example -------- - -In the SoC specific dtsi file: - - dra7_iodelay_core: padconf@4844a000 { - compatible =3D "ti,dra7-iodelay"; - reg =3D <0x4844a000 0x0d1c>; - #address-cells =3D <1>; - #size-cells =3D <0>; - #pinctrl-cells =3D <2>; - }; - -In board-specific file: - -&dra7_iodelay_core { - mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf { - pinctrl-pin-array =3D < - 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ - 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ - 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ - 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ - 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ - 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ - 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ - 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ - 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ - 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ - >; - }; -}; --- base-commit: 1e9cdc2ea15adf4a821eefedabf6c0c8cf0b6a55 change-id: 20260706-ti-iodelay-26f796fc4f6f Best regards, --=20 Bhargav