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Wed, 22 Jul 2026 08:27:32 -0700 (PDT) From: Bhargav Joshi Date: Wed, 22 Jul 2026 20:57:13 +0530 Subject: [PATCH v2] dt-bindings: clock: ti,dm816-fapll-clock: Convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260722-ti-fapll-clock-v2-1-085054acf2dc@gmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/13MQQ6CMBCF4auQWVvTjtCqK+9hWJQ6wMRCSUuIh nB3K+7MrP5J3rdCosiU4FqsEGnhxGHMgYcCXG/HjgQ/cgNK1FLjRcwsWjt5L5wP7ikqYyU61CV pCXk0RWr5tYP3OnfPaQ7xvfuL+n5/lFHmn1qUyNfoc+karMpTc+sGy/7owgD1tm0f8eidXKwAA AA= X-Change-ID: 20260629-ti-fapll-clock-57a02c264e60 To: Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tony Lindgren , Tero Kristo Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, goledhruva@gmail.com, m-chawdhry@ti.com, daniel.baluta@gmail.com, simona.toaca@nxp.com, j.bhargav.u@gmail.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784734044; l=4594; i=j.bhargav.u@gmail.com; h=from:subject:message-id; bh=dn5uLR2398NEbNSJsJqfsFbz7HOVMX/WBpzKD1Jjnc4=; b=2U2yfC+iWv+nAWF0jjAqMtw6ecpcwGQomW5H8E0QwMCuRGWlUAW4QTDMfpRTIFB7ahCD7BhK9 zddAGR06GRcBFs9uduoJo9LImpx5SP/DlMdBJ4pJcVBxb9OCYMbxxYU X-Developer-Key: i=j.bhargav.u@gmail.com; a=ed25519; pk=IqNDwUZKECEA+n8wXctFLBbYL9NhFstZNbOznm/nX1k= Convert the Texas Instruments DM816 FAPLL clock binding from plain text to YAML DT schema. The text documented #clock-cells to be set as 0, while the example and existing dt and driver require it to be 1. The schema now strictly enforces #clock-cells =3D <1>. Properties clock-indices and clock-output-names are documented in the binding and added as required as driver strictly requires it and existing dt already use this property. Signed-off-by: Bhargav Joshi --- Changes in v2: - Cleaned up binding descriptions by dropping the redundant common clock sentence and removing "phandle for" from the clock items - Link to v1: https://lore.kernel.org/r/20260717-ti-fapll-clock-v1-1-1b684c= b2543b@gmail.com --- .../devicetree/bindings/clock/ti/fapll.txt | 31 ---------- .../bindings/clock/ti/ti,dm816-fapll-clock.yaml | 71 ++++++++++++++++++= ++++ 2 files changed, 71 insertions(+), 31 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/ti/fapll.txt b/Documen= tation/devicetree/bindings/clock/ti/fapll.txt deleted file mode 100644 index 88986ef39ddd..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/fapll.txt +++ /dev/null @@ -1,31 +0,0 @@ -Binding for Texas Instruments FAPLL clock. - -This binding uses the common clock binding[1]. It assumes a -register-mapped FAPLL with usually two selectable input clocks -(reference clock and bypass clock), and one or more child -syntesizers. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "ti,dm816-fapll-clock" -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : link phandles of parent clocks (clk-ref and clk-bypass) -- reg : address and length of the register set for controlling the FAPLL. - -Examples: - main_fapll: main_fapll { - #clock-cells =3D <1>; - compatible =3D "ti,dm816-fapll-clock"; - reg =3D <0x400 0x40>; - clocks =3D <&sys_clkin_ck &sys_clkin_ck>; - clock-indices =3D <1>, <2>, <3>, <4>, <5>, - <6>, <7>; - clock-output-names =3D "main_pll_clk1", - "main_pll_clk2", - "main_pll_clk3", - "main_pll_clk4", - "main_pll_clk5", - "main_pll_clk6", - "main_pll_clk7"; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/ti,dm816-fapll-cloc= k.yaml b/Documentation/devicetree/bindings/clock/ti/ti,dm816-fapll-clock.ya= ml new file mode 100644 index 000000000000..423b7405e398 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/ti,dm816-fapll-clock.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,dm816-fapll-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments FAPLL clock + +maintainers: + - Tony Lindgren + - Tero Kristo + +description: + FAPLL is register-mapped with usually two selectable input clocks + (reference clock and bypass clock), and one or more child synthesizers. + +properties: + compatible: + const: ti,dm816-fapll-clock + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + + clocks: + items: + - description: parent clock clk-ref + - description: parent clock clk-bypass + + clock-indices: + description: + Maps child synthesizers to physical indices 1-7. Index 0 is physical= ly + reserved for the Master PLL. + minItems: 1 + maxItems: 7 + items: + minimum: 1 + maximum: 7 + + clock-output-names: + description: + Names of the child synthesizer outputs. The length of this array must + match clock-indices. + minItems: 1 + maxItems: 7 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + - clock-indices + - clock-output-names + +additionalProperties: false + +examples: + - | + clock-controller@400 { + #clock-cells =3D <1>; + compatible =3D "ti,dm816-fapll-clock"; + reg =3D <0x400 0x40>; + clocks =3D <&sys_clkin_ck &sys_clkin_ck>; + clock-indices =3D <1>, <2>, <3>, <4>, <5>, <6>, <7>; + clock-output-names =3D "main_pll_clk1", "main_pll_clk2", "main_pll= _clk3", + "main_pll_clk4", "main_pll_clk5", "main_pll_c= lk6", + "main_pll_clk7"; + + }; --- base-commit: 0716f9b9338a86dd27796e00ed0fd560c653323a change-id: 20260629-ti-fapll-clock-57a02c264e60 Best regards, --=20 Bhargav