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It provides: - Real-time voltage and current monitoring - Configurable thresholds per channel - Hardware interrupts when thresholds are violated Add a DeviceTree binding to describe the BCL on Qualcomm's PMICs. Add sensor type to SPMI device list for BCL device. Signed-off-by: Manaf Meethalavalappu Pallikunhi --- .../bindings/hwmon/qcom,pm7250b-bcl.yaml | 64 ++++++++++++++++++= ++++ .../devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 4 ++ MAINTAINERS | 7 +++ 3 files changed, 75 insertions(+) diff --git a/Documentation/devicetree/bindings/hwmon/qcom,pm7250b-bcl.yaml = b/Documentation/devicetree/bindings/hwmon/qcom,pm7250b-bcl.yaml new file mode 100644 index 000000000000..3c069e94a34e --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/qcom,pm7250b-bcl.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/qcom,pm7250b-bcl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SPMI PMIC Battery Current Limiting (BCL) Hardware Monitor + +maintainers: + - Manaf Meethalavalappu Pallikunhi + +description: + SPMI PMIC Battery Current Limiting (BCL) hardware provides monitoring and + alarm functionality for battery overcurrent and battery or system under + voltage conditions. It monitors battery voltage and current, and + can trigger interrupts when configurable thresholds are exceeded. + +properties: + compatible: + enum: + - qcom,pm7250b-bcl + - qcom,pm8350c-bcl + - qcom,pm8550-bcl + - qcom,pmh0101-bcl + - qcom,pmih0108-bcl + - qcom,smb2360-bcl + - qcom,smb2370-bcl + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: max-min + - const: critical + +required: + - compatible + - reg + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include + + pmic { + #address-cells =3D <1>; + #size-cells =3D <0>; + + sensor@1d00 { + compatible =3D "qcom,pm7250b-bcl"; + reg =3D <0x1d00>; + interrupts =3D <0x2 0x1d 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x1d 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "max-min", + "critical"; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Do= cumentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index 809be2756a0c..3caee21a02ad 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -190,6 +190,10 @@ patternProperties: type: object $ref: /schemas/rtc/qcom-pm8xxx-rtc.yaml# =20 + "^sensor@[0-9a-f]+$": + type: object + $ref: /schemas/hwmon/qcom,pm7250b-bcl.yaml# + "^temp-alarm@[0-9a-f]+$": type: object $ref: /schemas/thermal/qcom,spmi-temp-alarm.yaml# diff --git a/MAINTAINERS b/MAINTAINERS index 16b73f5825d6..1b178d3a91ad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22176,6 +22176,13 @@ S: Maintained F: Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml F: drivers/net/wwan/qcom_bam_dmux.c =20 +QUALCOMM BCL HARDWARE MONITOR DRIVER +M: Manaf Meethalavalappu Pallikunhi +L: linux-hwmon@vger.kernel.org +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/hwmon/qcom,pm7250b-bcl.yaml + QUALCOMM BLUETOOTH DRIVER M: Bartosz Golaszewski L: linux-arm-msm@vger.kernel.org --=20 2.43.0 From nobody Sat Jul 25 00:15:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9D86399369 for ; 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Tue, 21 Jul 2026 11:30:29 -0700 (PDT) Received: from hu-manafm-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3147e1ca3efsm1185298eec.30.2026.07.21.11.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2026 11:30:28 -0700 (PDT) From: Manaf Meethalavalappu Pallikunhi Date: Wed, 22 Jul 2026 00:00:07 +0530 Subject: [PATCH v2 02/10] hwmon: Add Qualcomm PMIC BCL driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260722-qcom-bcl-hwmon-v2-2-febe2805e17b@oss.qualcomm.com> References: <20260722-qcom-bcl-hwmon-v2-0-febe2805e17b@oss.qualcomm.com> In-Reply-To: <20260722-qcom-bcl-hwmon-v2-0-febe2805e17b@oss.qualcomm.com> To: Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Stephen Boyd , Bjorn Andersson , Konrad Dybcio , Daniel Lezcano Cc: linux-hwmon@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mfd@lists.linux.dev, Gaurav Kohli , Manaf Meethalavalappu Pallikunhi X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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The driver exposes battery voltage and current monitoring through hwmon interface. The BCL driver provides - Real-time voltage and current readings - Configurable threshold-based alarms - Interrupt-driven notifications when thresholds are exceeded - Automatic threshold management with polling-based recovery - Hardware-specific scaling factors and threshold representations Signed-off-by: Manaf Meethalavalappu Pallikunhi --- MAINTAINERS | 1 + drivers/hwmon/Kconfig | 11 + drivers/hwmon/Makefile | 1 + drivers/hwmon/qcom-bcl-hwmon.c | 1443 ++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 1456 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1b178d3a91ad..8b7d3c3c6252 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22182,6 +22182,7 @@ L: linux-hwmon@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/hwmon/qcom,pm7250b-bcl.yaml +F: drivers/hwmon/qcom-bcl-hwmon.c =20 QUALCOMM BLUETOOTH DRIVER M: Bartosz Golaszewski diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 50d744db3045..8618c88932c3 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1955,6 +1955,17 @@ config SENSORS_PWM_FAN This driver can also be built as a module. If so, the module will be called pwm-fan. =20 +config SENSORS_QCOM_SPMI_BCL + tristate "Qualcomm SPMI BCL hardware monitoring" + depends on SPMI + select REGMAP_SPMI + help + Say yes here to enable support for Qualcomm battery over current + and under voltage alarms monitor. + + This driver can also be built as a module. If so, the module + will be called qcom-bcl-hwmon. + config SENSORS_QNAP_MCU_HWMON tristate "QNAP MCU hardware monitoring" depends on MFD_QNAP_MCU diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 63809eeec2f4..cb61983d437c 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -204,6 +204,7 @@ obj-$(CONFIG_SENSORS_POWR1220) +=3D powr1220.o obj-$(CONFIG_SENSORS_PROM21_XHCI) +=3D prom21-xhci.o obj-$(CONFIG_SENSORS_PT5161L) +=3D pt5161l.o obj-$(CONFIG_SENSORS_PWM_FAN) +=3D pwm-fan.o +obj-$(CONFIG_SENSORS_QCOM_SPMI_BCL) +=3D qcom-bcl-hwmon.o obj-$(CONFIG_SENSORS_QNAP_MCU_HWMON) +=3D qnap-mcu-hwmon.o obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON) +=3D raspberrypi-hwmon.o obj-$(CONFIG_SENSORS_SBTSI) +=3D sbtsi_temp.o diff --git a/drivers/hwmon/qcom-bcl-hwmon.c b/drivers/hwmon/qcom-bcl-hwmon.c new file mode 100644 index 000000000000..a21433b45482 --- /dev/null +++ b/drivers/hwmon/qcom-bcl-hwmon.c @@ -0,0 +1,1443 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Qualcomm pmic BCL driver for battery overcurrent and + * battery or system under voltage monitor + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* BCL common regmap offset */ +#define REVISION1 0x0 +#define REVISION2 0x1 +#define STATUS 0x8 +#define INT_RT_STS 0x10 +#define EN_CTL1 0x46 + +/* BCL GEN1 regmap offsets */ +#define MODE_CTL1 0x41 +#define VADC_L0_THR 0x48 +#define VCMP_L1_THR 0x49 +#define IADC_H0_THR 0x4b +#define IADC_H1_THR 0x4c +#define VADC_CONV_REQ 0x72 +#define IADC_CONV_REQ 0x82 +#define VADC_DATA1 0x76 +#define IADC_DATA1 0x86 + +/* BCL GEN3 regmap offsets */ +#define VCMP_CTL 0x44 +#define VCMP_L0_THR 0x47 +#define PARAM_1 0x0e +#define IADC_H1_THR_GEN3 0x4d + +#define BCL_IN_INC_MV 25 +#define BCL_ALARM_POLLING_MS 50 + +/** + * enum bcl_limit_alarm - BCL alarm threshold levels + * @BCL_LIMIT_ALARM_LVL0: Level 0 alarm threshold + * @BCL_LIMIT_ALARM_LVL1: Level 1 alarm threshold + * @BCL_LIMIT_ALARM_MAX: sentinel value + * + * Defines the two threshold levels for BCL monitoring. Each level corresp= onds + * to different severity of in or curr conditions. + */ +enum bcl_limit_alarm { + BCL_LIMIT_ALARM_LVL0, + BCL_LIMIT_ALARM_LVL1, + + BCL_LIMIT_ALARM_MAX, +}; + +/** + * enum bcl_channel - BCL supported sensor channel type + * @CHANNEL_IN: in (voltage) channel + * @CHANNEL_CURR: curr (current) channel + * @CHANNEL_MAX: sentinel value + * + * Defines the supported channel types for bcl. + */ +enum bcl_channel { + CHANNEL_IN, + CHANNEL_CURR, + + CHANNEL_MAX, +}; + +/** + * enum bcl_thresh_type - voltage or current threshold representation type + * @THRESH_TYPE_ADC: Raw ADC value representation + * @THRESH_TYPE_INDEX: Index-based voltage or current representation + * + * Specifies how voltage or current thresholds are stored and interpreted = in + * registers. Some PMICs use raw ADC values while others use indexed value= s. + */ +enum bcl_thresh_type { + THRESH_TYPE_ADC, + THRESH_TYPE_INDEX, +}; + +/** + * enum bcl_battery_config - Battery configuration types + * @BCL_BATT_1S: Single cell battery + * @BCL_BATT_2S: Two cells in series + * @BCL_BATT_3S: Three cells in series + * @BCL_BATT_UNKNOWN: Unknown or not applicable + */ +enum bcl_battery_config { + BCL_BATT_1S, + BCL_BATT_2S, + BCL_BATT_3S, + BCL_BATT_UNKNOWN, +}; + +/** + * enum bcl_fields - BCL register field identifiers + * @F_V_MAJOR: Major revision info field + * @F_V_MINOR: Minor revision info field + * @F_CTL_EN: Monitor enable control field + * @F_LVL0_ALARM: Level 0 alarm status field + * @F_LVL1_ALARM: Level 1 alarm status field + * @F_IN_MON_EN: voltage monitor enable control field + * @F_IN_L0_THR: voltage level 0 threshold field + * @F_IN_L1_THR: voltage level 1 threshold field + * @F_IN_INPUT_EN: voltage input enable control field + * @F_IN_INPUT: voltage input data field (LSB for 16-bit data) + * @F_IN_INPUT1: voltage input data MSB for 16-bit voltage data + * @F_CURR_MON_EN: current monitor enable control field + * @F_CURR_H0_THR: current level 0 threshold field + * @F_CURR_H1_THR: current level 1 threshold field + * @F_CURR_INPUT: current input data field (LSB for 16-bit data) + * @F_CURR_INPUT1: current input data MSB for 16-bit current data + * @F_MAX_FIELDS: sentinel value + * + * Enumeration of all register fields used by the BCL driver for accessing + * registers through regmap fields. + */ +enum bcl_fields { + /* Common fields - present in all BCL variants */ + F_V_MAJOR, + F_V_MINOR, + F_CTL_EN, + F_LVL0_ALARM, + F_LVL1_ALARM, + + /* Voltage monitoring fields */ + F_IN_MON_EN, + F_IN_L0_THR, + F_IN_L1_THR, + F_IN_INPUT_EN, + F_IN_INPUT, + F_IN_INPUT1, /* MSB for 16-bit voltage data */ + + /* Current monitoring fields */ + F_CURR_MON_EN, + F_CURR_H0_THR, + F_CURR_H1_THR, + F_CURR_INPUT, + F_CURR_INPUT1, /* MSB for 16-bit current data */ + + F_MAX_FIELDS +}; + +/** + * struct bcl_channel_cfg - BCL channel related configuration + * @default_scale_nu: Default scaling factor in nano unit + * @base: Base threshold value in milli unit + * @max: Maximum threshold value in milli unit + * @step: step increment value between two indexed threshold value + * @thresh_type: Array specifying threshold representation type for each a= larm level + * + * Contains hardware-specific configuration and scaling parameters for dif= ferent + * channel(voltage and current).. + */ +struct bcl_channel_cfg { + u32 default_scale_nu; + u32 base; + u32 max; + u32 step; + u8 thresh_type[BCL_LIMIT_ALARM_MAX]; +}; + +/** + * struct bcl_desc - BCL device descriptor + * @reg_fields: Array of register field definitions for this device variant + * @channel_cfg: Array of channel configurations indexed by battery config + * PMICs without battery detection: only [BCL_BATT_1S] is de= fined + * PMICs with battery detection: [BCL_BATT_2S], [BCL_BATT_3S] + * @battery_config_field: Register field for battery configuration detecti= on + * NOTE: This is an ABSOLUTE address, not relative = to BCL base + * Set to REG_FIELD(0, 0, 0) if not used + * @num_reg_fields: Number of register field definitions for this device v= ariant + * @data_field_bits_size: data read register bit size + * @thresh_field_bits_size: lsb bit size those are not included in thresho= ld register + * + * Contains hardware-specific configuration and scaling parameters for dif= ferent + * BCL variants. Each PMIC model may have different register layouts and + * conversion factors. + */ +struct bcl_desc { + const struct reg_field *reg_fields; + struct bcl_channel_cfg channel_cfg[BCL_BATT_3S + 1][CHANNEL_MAX]; + const struct reg_field battery_config_field; + u8 num_reg_fields; + u8 data_field_bits_size; + u8 thresh_field_bits_size; +}; + +/** + * struct bcl_alarm_data - BCL alarm interrupt data + * @irq: IRQ number assigned to this alarm + * @irq_enabled: Flag indicating if IRQ is enabled + * @irq_wake_enabled: Flag indicating if IRQ wake is enabled + * @shutting_down: Flag preventing work from re-enabling IRQ during teardo= wn + * @type: Alarm level type (LVL0, or LVL1) + * @device: Pointer to parent BCL device structure + * @a_lock: Mutex for protecting alarm state + * @alarm_poll_work: delayed_work to poll alarm status + * + * Stores interrupt-related information for each alarm threshold level. + * Used by the IRQ handler to identify which alarm triggered. + */ +struct bcl_alarm_data { + int irq; + bool irq_enabled; + bool irq_wake_enabled; + bool shutting_down; + enum bcl_limit_alarm type; + void *device; + /* Protects alarm IRQ enable/disable state */ + struct mutex a_lock; + struct delayed_work alarm_poll_work; +}; + +/** + * struct bcl_device - Main BCL device structure + * @dev: Pointer to device structure + * @regmap: Regmap for accessing PMIC registers + * @fields: Array of regmap fields for register access + * @bcl_alarms: Array of alarm data structures for each threshold level + * @lock: Mutex for protecting concurrent hardware access + * @base: the BCL regbase offset from regmap + * @last_in_input: Last valid voltage input reading in millivolts + * @last_curr_input: Last valid current input reading in milliamps + * @last_in_updated: Timestamp of last voltage input update + * @last_curr_updated: Timestamp of last current input update + * @desc: Pointer to device descriptor with hardware-specific parameters + * @hwmon_dev: Pointer to registered hwmon device + * @hwmon_info: Dynamically built hwmon channel info array + * @hwmon_chip_info: Dynamically built hwmon chip info structure + * @hwmon_name: Sanitized name for hwmon device + * @batt_config: Detected battery configuration (only for SMB2360/2370) + * @batt_config_regfield: Regmap field for battery configuration register + * @in_attrs: Voltage channel attributes mask + * @curr_attrs: Current channel attributes mask + * + * Main driver structure containing all state and configuration for a BCL + * monitoring instance. Manages voltage and current monitoring, thresholds, + * and alarm handling. + */ +struct bcl_device { + struct device *dev; + struct regmap *regmap; + u16 base; + struct regmap_field *fields[F_MAX_FIELDS]; + struct bcl_alarm_data bcl_alarms[BCL_LIMIT_ALARM_MAX]; + /* Protects hardware register access and device state */ + struct mutex lock; + u32 last_in_input; + s32 last_curr_input; + unsigned long last_in_updated; + unsigned long last_curr_updated; + const struct bcl_desc *desc; + struct device *hwmon_dev; + const struct hwmon_channel_info **hwmon_info; + struct hwmon_chip_info hwmon_chip_info; + char *hwmon_name; + enum bcl_battery_config batt_config; + struct regmap_field *batt_config_regfield; + u32 in_attrs; + u32 curr_attrs; +}; + +static const u8 in_attr_to_lvl_map[] =3D { + [hwmon_in_min] =3D BCL_LIMIT_ALARM_LVL0, + [hwmon_in_lcrit] =3D BCL_LIMIT_ALARM_LVL1, + [hwmon_in_min_alarm] =3D BCL_LIMIT_ALARM_LVL0, + [hwmon_in_lcrit_alarm] =3D BCL_LIMIT_ALARM_LVL1, +}; + +static const u8 in_lvl_to_attr_map[BCL_LIMIT_ALARM_MAX] =3D { + [BCL_LIMIT_ALARM_LVL0] =3D hwmon_in_min_alarm, + [BCL_LIMIT_ALARM_LVL1] =3D hwmon_in_lcrit_alarm, +}; + +static const u8 curr_attr_to_lvl_map[] =3D { + [hwmon_curr_max] =3D BCL_LIMIT_ALARM_LVL0, + [hwmon_curr_crit] =3D BCL_LIMIT_ALARM_LVL1, + [hwmon_curr_max_alarm] =3D BCL_LIMIT_ALARM_LVL0, + [hwmon_curr_crit_alarm] =3D BCL_LIMIT_ALARM_LVL1, +}; + +static const u8 curr_lvl_to_attr_map[BCL_LIMIT_ALARM_MAX] =3D { + [BCL_LIMIT_ALARM_LVL0] =3D hwmon_curr_max_alarm, + [BCL_LIMIT_ALARM_LVL1] =3D hwmon_curr_crit_alarm, +}; + +/* Interrupt names for each alarm level */ +static const char * const bcl_int_names[BCL_LIMIT_ALARM_MAX] =3D { + [BCL_LIMIT_ALARM_LVL0] =3D "max-min", + [BCL_LIMIT_ALARM_LVL1] =3D "critical", +}; + +static const struct reg_field bcl_pm7250b_reg_fields[] =3D { + [F_V_MAJOR] =3D REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] =3D REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] =3D REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] =3D REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] =3D REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] =3D REG_FIELD(MODE_CTL1, 0, 2), + [F_IN_L0_THR] =3D REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] =3D REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] =3D REG_FIELD(VADC_CONV_REQ, 0, 0), + [F_IN_INPUT] =3D REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] =3D REG_FIELD(IADC_CONV_REQ, 0, 0), + [F_CURR_H0_THR] =3D REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] =3D REG_FIELD(IADC_H1_THR, 0, 7), + [F_CURR_INPUT] =3D REG_FIELD(IADC_DATA1, 0, 7), +}; + +static const struct reg_field bcl_pm8350c_reg_fields[] =3D { + [F_V_MAJOR] =3D REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] =3D REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] =3D REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] =3D REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] =3D REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] =3D REG_FIELD(VCMP_CTL, 0, 1), + [F_IN_L0_THR] =3D REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] =3D REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] =3D REG_FIELD(VADC_CONV_REQ, 0, 0), + [F_IN_INPUT] =3D REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] =3D REG_FIELD(IADC_CONV_REQ, 0, 0), + [F_CURR_H0_THR] =3D REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] =3D REG_FIELD(IADC_H1_THR, 0, 7), + [F_CURR_INPUT] =3D REG_FIELD(IADC_DATA1, 0, 7), +}; + +static const struct reg_field bcl_pm8550_reg_fields[] =3D { + [F_V_MAJOR] =3D REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] =3D REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] =3D REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] =3D REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] =3D REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] =3D REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] =3D REG_FIELD(VCMP_L0_THR, 0, 5), + [F_IN_L1_THR] =3D REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] =3D REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] =3D REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] =3D REG_FIELD(PARAM_1, 1, 1), +}; + +static const struct reg_field bcl_pmh0101_reg_fields[] =3D { + [F_V_MAJOR] =3D REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] =3D REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] =3D REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] =3D REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] =3D REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] =3D REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] =3D REG_FIELD(VCMP_L0_THR, 0, 6), + [F_IN_L1_THR] =3D REG_FIELD(VCMP_L1_THR, 0, 6), + [F_IN_INPUT_EN] =3D REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] =3D REG_FIELD(VADC_DATA1, 0, 7), + [F_IN_INPUT1] =3D REG_FIELD(VADC_DATA1 + 1, 0, 7), + [F_CURR_MON_EN] =3D REG_FIELD(PARAM_1, 1, 1), +}; + +static const struct reg_field bcl_pmih0108_reg_fields[] =3D { + [F_V_MAJOR] =3D REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] =3D REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] =3D REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] =3D REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] =3D REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] =3D REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] =3D REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] =3D REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] =3D REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] =3D REG_FIELD(VADC_DATA1, 0, 7), + [F_IN_INPUT1] =3D REG_FIELD(VADC_DATA1 + 1, 0, 7), + [F_CURR_MON_EN] =3D REG_FIELD(PARAM_1, 1, 1), + [F_CURR_H0_THR] =3D REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] =3D REG_FIELD(IADC_H1_THR_GEN3, 0, 7), + [F_CURR_INPUT] =3D REG_FIELD(IADC_DATA1, 0, 7), + [F_CURR_INPUT1] =3D REG_FIELD(IADC_DATA1 + 1, 0, 7), +}; + +static const struct reg_field bcl_smb2360_reg_fields[] =3D { + [F_V_MAJOR] =3D REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] =3D REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] =3D REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] =3D REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] =3D REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] =3D REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] =3D REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] =3D REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] =3D REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] =3D REG_FIELD(VADC_DATA1, 0, 7), + [F_CURR_MON_EN] =3D REG_FIELD(PARAM_1, 1, 1), + [F_CURR_H0_THR] =3D REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] =3D REG_FIELD(IADC_H1_THR_GEN3, 0, 7), + [F_CURR_INPUT] =3D REG_FIELD(IADC_DATA1, 0, 7), +}; + +static const struct reg_field bcl_smb2370_reg_fields[] =3D { + [F_V_MAJOR] =3D REG_FIELD(REVISION2, 0, 7), + [F_V_MINOR] =3D REG_FIELD(REVISION1, 0, 7), + [F_CTL_EN] =3D REG_FIELD(EN_CTL1, 7, 7), + [F_LVL0_ALARM] =3D REG_FIELD(STATUS, 0, 0), + [F_LVL1_ALARM] =3D REG_FIELD(STATUS, 1, 1), + [F_IN_MON_EN] =3D REG_FIELD(VCMP_CTL, 0, 2), + [F_IN_L0_THR] =3D REG_FIELD(VADC_L0_THR, 0, 7), + [F_IN_L1_THR] =3D REG_FIELD(VCMP_L1_THR, 0, 5), + [F_IN_INPUT_EN] =3D REG_FIELD(PARAM_1, 0, 0), + [F_IN_INPUT] =3D REG_FIELD(VADC_DATA1, 0, 7), + [F_IN_INPUT1] =3D REG_FIELD(VADC_DATA1 + 1, 0, 7), + [F_CURR_MON_EN] =3D REG_FIELD(PARAM_1, 1, 1), + [F_CURR_H0_THR] =3D REG_FIELD(IADC_H0_THR, 0, 7), + [F_CURR_H1_THR] =3D REG_FIELD(IADC_H1_THR_GEN3, 0, 7), + [F_CURR_INPUT] =3D REG_FIELD(IADC_DATA1, 0, 7), + [F_CURR_INPUT1] =3D REG_FIELD(IADC_DATA1 + 1, 0, 7), +}; + +static const struct bcl_desc pm7250b_data =3D { + .reg_fields =3D bcl_pm7250b_reg_fields, + .num_reg_fields =3D F_CURR_INPUT + 1, + .data_field_bits_size =3D 8, + .thresh_field_bits_size =3D 7, + .battery_config_field =3D REG_FIELD(0, 0, 0), + .channel_cfg[BCL_BATT_1S][CHANNEL_IN] =3D { + .base =3D 2250, + .max =3D 3600, + .step =3D 25, + .default_scale_nu =3D 194637, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_1S][CHANNEL_CURR] =3D { + .max =3D 10000, + .default_scale_nu =3D 305180, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, +}; + +static const struct bcl_desc pm8350c_data =3D { + .reg_fields =3D bcl_pm8350c_reg_fields, + .num_reg_fields =3D F_CURR_INPUT + 1, + .data_field_bits_size =3D 8, + .thresh_field_bits_size =3D 8, + .battery_config_field =3D REG_FIELD(0, 0, 0), + .channel_cfg[BCL_BATT_1S][CHANNEL_IN] =3D { + .base =3D 2250, + .max =3D 3600, + .step =3D 25, + .default_scale_nu =3D 194637, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_1S][CHANNEL_CURR] =3D { + .max =3D 10000, + .default_scale_nu =3D 305180, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, +}; + +static const struct bcl_desc pm8550_data =3D { + .reg_fields =3D bcl_pm8550_reg_fields, + .num_reg_fields =3D F_CURR_MON_EN + 1, + .data_field_bits_size =3D 0, + .thresh_field_bits_size =3D 8, + .battery_config_field =3D REG_FIELD(0, 0, 0), + .channel_cfg[BCL_BATT_1S][CHANNEL_IN] =3D { + .base =3D 2250, + .max =3D 3600, + .step =3D 25, + .thresh_type =3D {THRESH_TYPE_INDEX, THRESH_TYPE_INDEX}, + }, +}; + +static const struct bcl_desc pmih0108_data =3D { + .reg_fields =3D bcl_pmih0108_reg_fields, + .num_reg_fields =3D F_MAX_FIELDS, + .data_field_bits_size =3D 16, + .thresh_field_bits_size =3D 8, + .battery_config_field =3D REG_FIELD(0, 0, 0), + .channel_cfg[BCL_BATT_1S][CHANNEL_IN] =3D { + .base =3D 2250, + .max =3D 3600, + .step =3D 25, + .default_scale_nu =3D 194637, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_1S][CHANNEL_CURR] =3D { + .max =3D 20000, + .default_scale_nu =3D 610370, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, +}; + +static const struct bcl_desc pmh0101_data =3D { + .reg_fields =3D bcl_pmh0101_reg_fields, + .num_reg_fields =3D F_CURR_MON_EN + 1, + .thresh_field_bits_size =3D 8, + .battery_config_field =3D REG_FIELD(0, 0, 0), + .channel_cfg[BCL_BATT_1S][CHANNEL_IN] =3D { + .base =3D 1500, + .max =3D 4000, + .step =3D 25, + .thresh_type =3D {THRESH_TYPE_INDEX, THRESH_TYPE_INDEX}, + }, +}; + +/* Register 0x2a50 mapping: 0 -> 2S, 1 -> 3S */ +static const struct bcl_desc smb2360_data =3D { + .reg_fields =3D bcl_smb2360_reg_fields, + .num_reg_fields =3D F_CURR_INPUT + 1, + .data_field_bits_size =3D 8, + .thresh_field_bits_size =3D 8, + .battery_config_field =3D REG_FIELD(0x2a50, 0, 1), + .channel_cfg[BCL_BATT_2S][CHANNEL_IN] =3D { + .base =3D 4500, + .max =3D 8400, + .step =3D 50, + .default_scale_nu =3D 432918, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_2S][CHANNEL_CURR] =3D { + .max =3D 20000, + .default_scale_nu =3D 540679, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, + .channel_cfg[BCL_BATT_3S][CHANNEL_IN] =3D { + .base =3D 6750, + .max =3D 12600, + .step =3D 75, + .default_scale_nu =3D 648790, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_3S][CHANNEL_CURR] =3D { + .max =3D 20000, + .default_scale_nu =3D 540679, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, +}; + +static const struct bcl_desc smb2370_data =3D { + .reg_fields =3D bcl_smb2370_reg_fields, + .num_reg_fields =3D F_MAX_FIELDS, + .data_field_bits_size =3D 16, + .thresh_field_bits_size =3D 8, + .battery_config_field =3D REG_FIELD(0x2a50, 0, 1), + .channel_cfg[BCL_BATT_2S][CHANNEL_IN] =3D { + .base =3D 4500, + .max =3D 8400, + .step =3D 50, + .default_scale_nu =3D 432918, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_2S][CHANNEL_CURR] =3D { + .max =3D 20000, + .default_scale_nu =3D 1441603, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, + .channel_cfg[BCL_BATT_3S][CHANNEL_IN] =3D { + .base =3D 6750, + .max =3D 12600, + .step =3D 75, + .default_scale_nu =3D 648790, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_INDEX}, + }, + .channel_cfg[BCL_BATT_3S][CHANNEL_CURR] =3D { + .max =3D 20000, + .default_scale_nu =3D 1441603, + .thresh_type =3D {THRESH_TYPE_ADC, THRESH_TYPE_ADC}, + }, +}; + +/** + * bcl_convert_raw_to_milliunit - Convert raw value to milli unit + * @bcl: BCL device structure + * @raw_val: Raw ADC value from hardware (signed for current, unsigned for= voltage) + * @type: type of the channel, in or curr + * @field_width: bits size for data or threshold field + * + * Return: value in milli unit + */ +static int bcl_convert_raw_to_milliunit(const struct bcl_device *bcl, + s32 raw_val, + enum bcl_channel type, + u8 field_width) +{ + const struct bcl_desc *desc =3D bcl->desc; + u32 def_scale =3D desc->channel_cfg[bcl->batt_config][type].default_scale= _nu; + u32 scaling_factor =3D (field_width > 8) ? def_scale : (def_scale << fiel= d_width); + + return DIV_ROUND_CLOSEST((s64)raw_val * scaling_factor, 1000000); +} + +/** + * bcl_convert_milliunit_to_raw - Convert milli unit to raw value + * @bcl: BCL device structure + * @mval: threshold value in milli unit + * @type: type of the channel, in or curr + * @field_width: bits size for data or threshold field + * + * Return: Raw ADC value for hardware + */ +static unsigned int bcl_convert_milliunit_to_raw(const struct bcl_device *= bcl, + int mval, + enum bcl_channel type, + u8 field_width) +{ + const struct bcl_desc *desc =3D bcl->desc; + u32 def_scale =3D desc->channel_cfg[bcl->batt_config][type].default_scale= _nu; + u32 scaling_factor =3D (field_width > 8) ? def_scale : (def_scale << fiel= d_width); + + return DIV_ROUND_CLOSEST_ULL((u64)mval * 1000000, scaling_factor); +} + +/** + * bcl_convert_milliunit_to_index - Convert milliunit to in or curr index + * @bcl: BCL device structure + * @val: in or curr value in milli unit + * @type: type of the channel, in or curr + * + * Converts a value in milli unit to an index for BCL that use indexed thr= esholds. + * + * Return: Index value + */ +static unsigned int bcl_convert_milliunit_to_index(const struct bcl_device= *bcl, + int val, + enum bcl_channel type) +{ + const struct bcl_desc *desc =3D bcl->desc; + const struct bcl_channel_cfg *cfg =3D &desc->channel_cfg[bcl->batt_config= ][type]; + u64 diff =3D (u64)val - cfg->base; + + return DIV_ROUND_CLOSEST_ULL(diff, cfg->step); +} + +/** + * bcl_convert_index_to_milliunit - Convert in or curr index to milli unit + * @bcl: BCL device structure + * @val: index value + * @type: type of the channel, in or curr + * + * Converts an index value to milli unit for BCL that use indexed threshol= ds. + * + * Return: Value in millivolts or milliamps + */ +static unsigned int bcl_convert_index_to_milliunit(const struct bcl_device= *bcl, + int val, + enum bcl_channel type) +{ + const struct bcl_desc *desc =3D bcl->desc; + const struct bcl_channel_cfg *cfg =3D &desc->channel_cfg[bcl->batt_config= ][type]; + + return cfg->base + val * cfg->step; +} + +static int bcl_in_thresh_write(struct bcl_device *bcl, long value, enum bc= l_limit_alarm lvl) +{ + const struct bcl_desc *desc =3D bcl->desc; + u32 raw_val; + + int thresh =3D clamp_val(value, desc->channel_cfg[bcl->batt_config][CHANN= EL_IN].base, + desc->channel_cfg[bcl->batt_config][CHANNEL_IN].max); + + if (desc->channel_cfg[bcl->batt_config][CHANNEL_IN].thresh_type[lvl] =3D= =3D THRESH_TYPE_ADC) + raw_val =3D bcl_convert_milliunit_to_raw(bcl, thresh, CHANNEL_IN, + desc->thresh_field_bits_size); + else + raw_val =3D bcl_convert_milliunit_to_index(bcl, thresh, CHANNEL_IN); + + return regmap_field_write(bcl->fields[F_IN_L0_THR + lvl], raw_val); +} + +static int bcl_curr_thresh_write(struct bcl_device *bcl, long value, enum = bcl_limit_alarm lvl) +{ + const struct bcl_desc *desc =3D bcl->desc; + u32 raw_val; + + int thresh =3D clamp_val(value, 0, desc->channel_cfg[bcl->batt_config][CH= ANNEL_CURR].max); + + if (desc->channel_cfg[bcl->batt_config][CHANNEL_CURR].thresh_type[lvl] = =3D=3D THRESH_TYPE_ADC) + raw_val =3D bcl_convert_milliunit_to_raw(bcl, thresh, CHANNEL_CURR, + desc->thresh_field_bits_size); + else + raw_val =3D bcl_convert_milliunit_to_index(bcl, thresh, CHANNEL_CURR); + + return regmap_field_write(bcl->fields[F_CURR_H0_THR + lvl], raw_val); +} + +static int bcl_in_thresh_read(struct bcl_device *bcl, enum bcl_limit_alarm= lvl, long *out) +{ + int ret, thresh; + u32 raw_val =3D 0; + const struct bcl_desc *desc =3D bcl->desc; + + ret =3D regmap_field_read(bcl->fields[F_IN_L0_THR + lvl], &raw_val); + if (ret) + return ret; + + if (desc->channel_cfg[bcl->batt_config][CHANNEL_IN].thresh_type[lvl] =3D= =3D THRESH_TYPE_ADC) + thresh =3D bcl_convert_raw_to_milliunit(bcl, raw_val, CHANNEL_IN, + desc->thresh_field_bits_size); + else + thresh =3D bcl_convert_index_to_milliunit(bcl, raw_val, CHANNEL_IN); + + *out =3D thresh; + + return 0; +} + +static int bcl_curr_thresh_read(struct bcl_device *bcl, enum bcl_limit_ala= rm lvl, long *out) +{ + int ret, thresh; + u32 raw_val =3D 0; + const struct bcl_desc *desc =3D bcl->desc; + + ret =3D regmap_field_read(bcl->fields[F_CURR_H0_THR + lvl], &raw_val); + if (ret) + return ret; + + if (desc->channel_cfg[bcl->batt_config][CHANNEL_CURR].thresh_type[lvl] = =3D=3D THRESH_TYPE_ADC) + thresh =3D bcl_convert_raw_to_milliunit(bcl, raw_val, CHANNEL_CURR, + desc->thresh_field_bits_size); + else + thresh =3D bcl_convert_index_to_milliunit(bcl, raw_val, CHANNEL_CURR); + + *out =3D thresh; + + return 0; +} + +static int bcl_curr_input_read(struct bcl_device *bcl, long *out) +{ + int ret; + u32 raw_val =3D 0, msb =3D 0; + s32 signed_val; + const struct bcl_desc *desc =3D bcl->desc; + + /* Return cached value if read too soon after last update */ + if (time_before(jiffies, bcl->last_curr_updated + HZ)) { + *out =3D bcl->last_curr_input; + return 0; + } + + ret =3D regmap_field_read(bcl->fields[F_CURR_INPUT], &raw_val); + if (ret) + return ret; + + /* For 16-bit data, read MSB and combine with LSB */ + if (desc->data_field_bits_size =3D=3D 16) { + ret =3D regmap_field_read(bcl->fields[F_CURR_INPUT1], &msb); + if (ret) + return ret; + raw_val |=3D FIELD_PREP(GENMASK(15, 8), msb); + } + + /* + * Current ADC reading is in 2's complement form. + * Sign extend the value based on data field bit size. + */ + signed_val =3D sign_extend32(raw_val, desc->data_field_bits_size - 1); + + bcl->last_curr_input =3D + bcl_convert_raw_to_milliunit(bcl, signed_val, CHANNEL_CURR, + desc->data_field_bits_size); + bcl->last_curr_updated =3D jiffies; + + *out =3D bcl->last_curr_input; + + return 0; +} + +static int bcl_in_input_read(struct bcl_device *bcl, long *out) +{ + int ret; + u32 raw_val =3D 0, msb =3D 0; + const struct bcl_desc *desc =3D bcl->desc; + + /* Return cached value if read too soon after last update */ + if (time_before(jiffies, bcl->last_in_updated + HZ)) { + *out =3D bcl->last_in_input; + return 0; + } + + ret =3D regmap_field_read(bcl->fields[F_IN_INPUT], &raw_val); + if (ret) + return ret; + + /* For 16-bit data, read MSB and combine with LSB */ + if (desc->data_field_bits_size =3D=3D 16) { + ret =3D regmap_field_read(bcl->fields[F_IN_INPUT1], &msb); + if (ret) + return ret; + raw_val |=3D FIELD_PREP(GENMASK(15, 8), msb); + } + + bcl->last_in_input =3D + bcl_convert_raw_to_milliunit(bcl, raw_val, CHANNEL_IN, + desc->data_field_bits_size); + bcl->last_in_updated =3D jiffies; + + *out =3D bcl->last_in_input; + + return 0; +} + +static int bcl_read_alarm_status(struct bcl_device *bcl, + enum bcl_limit_alarm lvl, long *status) +{ + int ret; + u32 raw_val =3D 0; + + ret =3D regmap_field_read(bcl->fields[F_LVL0_ALARM + lvl], &raw_val); + if (ret) + return ret; + + *status =3D raw_val; + + return 0; +} + +static unsigned int bcl_get_version_major(const struct bcl_device *bcl) +{ + u32 raw_val =3D 0; + + regmap_field_read(bcl->fields[F_V_MAJOR], &raw_val); + + return raw_val; +} + +static unsigned int bcl_get_version_minor(const struct bcl_device *bcl) +{ + u32 raw_val =3D 0; + + regmap_field_read(bcl->fields[F_V_MINOR], &raw_val); + + return raw_val; +} + +static void bcl_hwmon_notify_event(struct bcl_device *bcl, enum bcl_limit_= alarm alarm) +{ + if (bcl->in_attrs) + hwmon_notify_event(bcl->hwmon_dev, hwmon_in, + in_lvl_to_attr_map[alarm], 0); + + if (bcl->curr_attrs) + hwmon_notify_event(bcl->hwmon_dev, hwmon_curr, + curr_lvl_to_attr_map[alarm], 0); +} + +static void bcl_alarm_enable_poll(struct work_struct *work) +{ + struct bcl_alarm_data *alarm =3D container_of(work, struct bcl_alarm_data, + alarm_poll_work.work); + struct bcl_device *bcl =3D (struct bcl_device *)alarm->device; + long status; + int ret; + + scoped_guard(mutex, &bcl->lock) + ret =3D bcl_read_alarm_status(bcl, alarm->type, &status); + + /* If read failed or shutting down, reschedule */ + if (ret || READ_ONCE(alarm->shutting_down)) { + if (!READ_ONCE(alarm->shutting_down)) + schedule_delayed_work(&alarm->alarm_poll_work, + msecs_to_jiffies(BCL_ALARM_POLLING_MS)); + return; + } + + /* Check if alarm cleared and IRQ needs re-enabling */ + scoped_guard(mutex, &alarm->a_lock) { + if (!status && !alarm->irq_enabled) { + alarm->irq_enabled =3D true; + enable_irq(alarm->irq); + + if (!alarm->irq_wake_enabled && !enable_irq_wake(alarm->irq)) + alarm->irq_wake_enabled =3D true; + + bcl_hwmon_notify_event(bcl, alarm->type); + return; + } + } + + /* Alarm still active, reschedule polling */ + if (!READ_ONCE(alarm->shutting_down)) + schedule_delayed_work(&alarm->alarm_poll_work, + msecs_to_jiffies(BCL_ALARM_POLLING_MS)); +} + +static irqreturn_t bcl_handle_alarm(int irq, void *data) +{ + struct bcl_alarm_data *alarm =3D data; + struct bcl_device *bcl =3D (struct bcl_device *)alarm->device; + long status; + + if (READ_ONCE(alarm->shutting_down)) + return IRQ_HANDLED; + + guard(mutex)(&bcl->lock); + + if (bcl_read_alarm_status(bcl, alarm->type, &status) || !status) + return IRQ_HANDLED; + + bcl_hwmon_notify_event(bcl, alarm->type); + + guard(mutex)(&alarm->a_lock); + if (alarm->shutting_down) + return IRQ_HANDLED; + + if (alarm->irq_enabled) { + alarm->irq_enabled =3D false; + disable_irq_nosync(alarm->irq); + } + + if (alarm->irq_wake_enabled) { + disable_irq_wake(alarm->irq); + alarm->irq_wake_enabled =3D false; + } + + schedule_delayed_work(&alarm->alarm_poll_work, + msecs_to_jiffies(BCL_ALARM_POLLING_MS)); + + return IRQ_HANDLED; +} + +static umode_t bcl_hwmon_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_input: + case hwmon_in_label: + case hwmon_in_min_alarm: + case hwmon_in_lcrit_alarm: + return 0444; + case hwmon_in_min: + case hwmon_in_lcrit: + return 0644; + default: + return 0; + } + case hwmon_curr: + switch (attr) { + case hwmon_curr_input: + case hwmon_curr_label: + case hwmon_curr_max_alarm: + case hwmon_curr_crit_alarm: + return 0444; + case hwmon_curr_max: + case hwmon_curr_crit: + return 0644; + default: + return 0; + } + default: + return 0; + } +} + +static int bcl_hwmon_write(struct device *dev, enum hwmon_sensor_types typ= e, + u32 attr, int channel, long val) +{ + struct bcl_device *bcl =3D dev_get_drvdata(dev); + + guard(mutex)(&bcl->lock); + + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_min: + case hwmon_in_lcrit: + return bcl_in_thresh_write(bcl, val, in_attr_to_lvl_map[attr]); + default: + return -EOPNOTSUPP; + } + case hwmon_curr: + switch (attr) { + case hwmon_curr_max: + case hwmon_curr_crit: + return bcl_curr_thresh_write(bcl, val, curr_attr_to_lvl_map[attr]); + default: + return -EOPNOTSUPP; + } + default: + return -EOPNOTSUPP; + } +} + +static int bcl_in_read(struct bcl_device *bcl, u32 attr, long *value) +{ + guard(mutex)(&bcl->lock); + + switch (attr) { + case hwmon_in_input: + return bcl_in_input_read(bcl, value); + case hwmon_in_min: + case hwmon_in_lcrit: + return bcl_in_thresh_read(bcl, in_attr_to_lvl_map[attr], value); + case hwmon_in_min_alarm: + case hwmon_in_lcrit_alarm: + return bcl_read_alarm_status(bcl, in_attr_to_lvl_map[attr], value); + default: + return -EOPNOTSUPP; + } +} + +static int bcl_curr_read(struct bcl_device *bcl, u32 attr, long *value) +{ + guard(mutex)(&bcl->lock); + + switch (attr) { + case hwmon_curr_input: + return bcl_curr_input_read(bcl, value); + case hwmon_curr_max: + case hwmon_curr_crit: + return bcl_curr_thresh_read(bcl, curr_attr_to_lvl_map[attr], value); + case hwmon_curr_max_alarm: + case hwmon_curr_crit_alarm: + return bcl_read_alarm_status(bcl, curr_attr_to_lvl_map[attr], value); + default: + return -EOPNOTSUPP; + } +} + +static int bcl_hwmon_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *value) +{ + struct bcl_device *bcl =3D dev_get_drvdata(dev); + + switch (type) { + case hwmon_in: + return bcl_in_read(bcl, attr, value); + case hwmon_curr: + return bcl_curr_read(bcl, attr, value); + default: + return -EOPNOTSUPP; + } +} + +static int bcl_hwmon_read_string(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + if (type =3D=3D hwmon_in && attr =3D=3D hwmon_in_label) + *str =3D "Voltage"; + else if (type =3D=3D hwmon_curr && attr =3D=3D hwmon_curr_label) + *str =3D "Current"; + else + *str =3D NULL; + + return *str ? 0 : -EOPNOTSUPP; +} + +static const struct hwmon_ops bcl_hwmon_ops =3D { + .is_visible =3D bcl_hwmon_is_visible, + .read =3D bcl_hwmon_read, + .read_string =3D bcl_hwmon_read_string, + .write =3D bcl_hwmon_write, +}; + +static int bcl_detect_battery_config(struct bcl_device *bcl) +{ + u32 reg_val =3D 0; + int ret; + + ret =3D regmap_field_read(bcl->batt_config_regfield, ®_val); + if (ret) { + dev_err(bcl->dev, "Failed to read battery config register: %d\n", ret); + return ret; + } + + /* + * Map register value to battery configuration. + * As per hardware documentation: + * 0 -> 2S, 1 -> 3S, 2 -> 4S (unsupported) + */ + switch (reg_val) { + case 0: + bcl->batt_config =3D BCL_BATT_2S; + return 0; + case 1: + bcl->batt_config =3D BCL_BATT_3S; + return 0; + default: + dev_err(bcl->dev, "Unsupported battery configuration: 0x%x\n", + reg_val); + return -EINVAL; + } +} + +static int bcl_update_scaling_factors(struct bcl_device *bcl) +{ + const struct bcl_desc *desc =3D bcl->desc; + int ret; + + /* Check if battery detection is supported */ + if (desc->battery_config_field.reg =3D=3D 0) { + /* No battery detection - use BCL_BATT_1S */ + bcl->batt_config =3D BCL_BATT_1S; + dev_dbg(bcl->dev, "Using default 1S battery configuration\n"); + return 0; + } + + bcl->batt_config_regfield =3D devm_regmap_field_alloc(bcl->dev, + bcl->regmap, + desc->battery_config_field); + if (IS_ERR(bcl->batt_config_regfield)) { + dev_err(bcl->dev, "Failed to allocate battery config regmap field\n"); + return PTR_ERR(bcl->batt_config_regfield); + } + + ret =3D bcl_detect_battery_config(bcl); + if (ret < 0) + return ret; + + dev_dbg(bcl->dev, + "%dS battery: BASE=3D%u mV,MAX=3D%u mV,STEP=3D%u mV,V_SCALE=3D%u nV, I_= SCALE=3D%u nA\n", + bcl->batt_config + 1, + desc->channel_cfg[bcl->batt_config][CHANNEL_IN].base, + desc->channel_cfg[bcl->batt_config][CHANNEL_IN].max, + desc->channel_cfg[bcl->batt_config][CHANNEL_IN].step, + desc->channel_cfg[bcl->batt_config][CHANNEL_IN].default_scale_nu, + desc->channel_cfg[bcl->batt_config][CHANNEL_CURR].default_scale_nu); + + return 0; +} + +static int bcl_build_hwmon_info(struct bcl_device *bcl) +{ + const struct bcl_desc *desc =3D bcl->desc; + struct hwmon_channel_info *in_info =3D NULL, *curr_info =3D NULL; + const struct hwmon_channel_info **info_array; + int num_channels =3D 0; + u32 val =3D 0; + bool in_mon_enabled =3D false; + bool in_input_enabled =3D false; + bool curr_mon_enabled =3D false; + int ret; + + /* Check if voltage monitoring is enabled */ + ret =3D regmap_field_read(bcl->fields[F_IN_MON_EN], &val); + if (ret) + return ret; + in_mon_enabled =3D !!val; + + /* Check if voltage input reading is enabled */ + if (desc->data_field_bits_size !=3D 0) { + ret =3D regmap_field_read(bcl->fields[F_IN_INPUT_EN], &val); + if (ret) + return ret; + in_input_enabled =3D !!val; + } + + /* Check if current monitoring is enabled */ + if (desc->num_reg_fields > F_CURR_H0_THR) { + ret =3D regmap_field_read(bcl->fields[F_CURR_MON_EN], &val); + if (ret) + return ret; + curr_mon_enabled =3D !!val; + } + + /* Ensure at least one channel is enabled */ + if (!in_mon_enabled && !curr_mon_enabled) { + dev_err(bcl->dev, "No BCL channels enabled in hardware\n"); + return -ENODEV; + } + + if (in_mon_enabled) { + u32 *in_config; + + bcl->in_attrs =3D HWMON_I_LABEL | HWMON_I_MIN | HWMON_I_LCRIT | + HWMON_I_MIN_ALARM | HWMON_I_LCRIT_ALARM; + + if (in_input_enabled) + bcl->in_attrs |=3D HWMON_I_INPUT; + + in_info =3D devm_kzalloc(bcl->dev, sizeof(*in_info), GFP_KERNEL); + if (!in_info) + return -ENOMEM; + + in_config =3D devm_kzalloc(bcl->dev, 2 * sizeof(u32), GFP_KERNEL); + if (!in_config) + return -ENOMEM; + + in_config[0] =3D bcl->in_attrs; + in_info->type =3D hwmon_in; + in_info->config =3D in_config; + num_channels++; + } + + if (curr_mon_enabled) { + u32 *curr_config; + + bcl->curr_attrs =3D HWMON_C_INPUT | HWMON_C_LABEL | HWMON_C_MAX | + HWMON_C_CRIT | HWMON_C_MAX_ALARM | HWMON_C_CRIT_ALARM; + + curr_info =3D devm_kzalloc(bcl->dev, sizeof(*curr_info), GFP_KERNEL); + if (!curr_info) + return -ENOMEM; + + curr_config =3D devm_kzalloc(bcl->dev, 2 * sizeof(u32), GFP_KERNEL); + if (!curr_config) + return -ENOMEM; + + curr_config[0] =3D bcl->curr_attrs; + curr_info->type =3D hwmon_curr; + curr_info->config =3D curr_config; + num_channels++; + } + + /* Allocate info array (num_channels + 1 for NULL terminator) */ + info_array =3D devm_kcalloc(bcl->dev, num_channels + 1, + sizeof(*info_array), GFP_KERNEL); + if (!info_array) + return -ENOMEM; + + num_channels =3D 0; + if (in_info) + info_array[num_channels++] =3D in_info; + if (curr_info) + info_array[num_channels++] =3D curr_info; + + bcl->hwmon_info =3D info_array; + + bcl->hwmon_chip_info.ops =3D &bcl_hwmon_ops; + bcl->hwmon_chip_info.info =3D bcl->hwmon_info; + + return 0; +} + +static void bcl_alarm_work_cleanup_action(void *data) +{ + struct bcl_alarm_data *alarm =3D data; + + /* Set shutting_down flag to prevent work from being rescheduled */ + scoped_guard(mutex, &alarm->a_lock) + WRITE_ONCE(alarm->shutting_down, true); + + cancel_delayed_work_sync(&alarm->alarm_poll_work); +} + +static void bcl_alarm_wake_cleanup_action(void *data) +{ + struct bcl_alarm_data *alarm =3D data; + + guard(mutex)(&alarm->a_lock); + if (alarm->irq_wake_enabled) { + disable_irq_wake(alarm->irq); + alarm->irq_wake_enabled =3D false; + } +} + +static int bcl_alarm_irq_init(struct platform_device *pdev, + struct bcl_device *bcl) +{ + int ret, irq_num, i; + struct bcl_alarm_data *alarm; + + for (i =3D 0; i < ARRAY_SIZE(bcl->bcl_alarms); i++) { + alarm =3D &bcl->bcl_alarms[i]; + alarm->type =3D i; + alarm->device =3D bcl; + ret =3D devm_mutex_init(bcl->dev, &alarm->a_lock); + if (ret) + return ret; + + /* Initialize work before IRQ request */ + INIT_DELAYED_WORK(&alarm->alarm_poll_work, bcl_alarm_enable_poll); + + irq_num =3D platform_get_irq_byname(pdev, bcl_int_names[i]); + if (irq_num < 0) + return irq_num; + + alarm->irq =3D irq_num; + alarm->irq_enabled =3D true; + + ret =3D devm_request_threaded_irq(&pdev->dev, irq_num, NULL, + bcl_handle_alarm, IRQF_ONESHOT, + bcl_int_names[i], alarm); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(&pdev->dev, bcl_alarm_work_cleanup_acti= on, + alarm); + if (ret) + return ret; + + if (!enable_irq_wake(irq_num)) + alarm->irq_wake_enabled =3D true; + + ret =3D devm_add_action_or_reset(&pdev->dev, bcl_alarm_wake_cleanup_acti= on, + alarm); + if (ret) + return ret; + } + + return 0; +} + +static int bcl_regmap_field_init(struct device *dev, struct bcl_device *bc= l, + const struct bcl_desc *data) +{ + int i; + + /* + * Note: We use a mutable local copy of struct reg_field (not const) + * because we need to modify the .reg field to add the BCL base offset. + */ + for (i =3D 0; i < data->num_reg_fields; i++) { + struct reg_field field =3D data->reg_fields[i]; + + /* Skip uninitialized fields */ + if (field.reg =3D=3D 0 && field.lsb =3D=3D 0 && field.msb =3D=3D 0) + continue; + + field.reg +=3D bcl->base; + + bcl->fields[i] =3D devm_regmap_field_alloc(dev, bcl->regmap, field); + if (IS_ERR(bcl->fields[i])) + return PTR_ERR(bcl->fields[i]); + } + + return 0; +} + +static int bcl_probe(struct platform_device *pdev) +{ + struct bcl_device *bcl; + int ret; + u32 reg; + + bcl =3D devm_kzalloc(&pdev->dev, sizeof(*bcl), GFP_KERNEL); + if (!bcl) + return -ENOMEM; + + bcl->dev =3D &pdev->dev; + bcl->desc =3D device_get_match_data(&pdev->dev); + if (!bcl->desc) + return dev_err_probe(&pdev->dev, -EINVAL, "Failed to get device match da= ta\n"); + + ret =3D devm_mutex_init(bcl->dev, &bcl->lock); + if (ret) + return ret; + + bcl->regmap =3D dev_get_regmap(pdev->dev.parent, NULL); + if (!bcl->regmap) + return dev_err_probe(&pdev->dev, -EINVAL, "Couldn't get parent's regmap\= n"); + + ret =3D device_property_read_u32(&pdev->dev, "reg", ®); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to read 'reg' property\n"); + + bcl->base =3D reg; + + ret =3D bcl_regmap_field_init(bcl->dev, bcl, bcl->desc); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Unable to allocate regmap fields\= n"); + + ret =3D regmap_field_read(bcl->fields[F_CTL_EN], ®); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to read BCL enable status\= n"); + + if (!reg) + return dev_err_probe(&pdev->dev, -ENODEV, "BCL is not enabled by bootloa= der\n"); + + ret =3D bcl_update_scaling_factors(bcl); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to update scaling factors\= n"); + + ret =3D bcl_build_hwmon_info(bcl); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to build hwmon info\n"); + + dev_set_drvdata(&pdev->dev, bcl); + + bcl->hwmon_name =3D devm_hwmon_sanitize_name(&pdev->dev, + dev_name(bcl->dev)); + if (IS_ERR(bcl->hwmon_name)) + return PTR_ERR(bcl->hwmon_name); + + bcl->hwmon_dev =3D devm_hwmon_device_register_with_info(&pdev->dev, + bcl->hwmon_name, + bcl, + &bcl->hwmon_chip_info, + NULL); + if (IS_ERR(bcl->hwmon_dev)) + return dev_err_probe(&pdev->dev, PTR_ERR(bcl->hwmon_dev), + "Failed to register hwmon device\n"); + + ret =3D bcl_alarm_irq_init(pdev, bcl); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to initialize alarm IRQs\n= "); + + dev_dbg(&pdev->dev, "BCL hwmon device with version: %u.%u registered\n", + bcl_get_version_major(bcl), bcl_get_version_minor(bcl)); + + return 0; +} + +static const struct of_device_id bcl_match[] =3D { + { + .compatible =3D "qcom,pm7250b-bcl", + .data =3D &pm7250b_data, + }, { + .compatible =3D "qcom,pm8350c-bcl", + .data =3D &pm8350c_data, + }, { + .compatible =3D "qcom,pm8550-bcl", + .data =3D &pm8550_data, + }, { + .compatible =3D "qcom,pmh0101-bcl", + .data =3D &pmh0101_data, + }, { + .compatible =3D "qcom,pmih0108-bcl", + .data =3D &pmih0108_data, + }, { + .compatible =3D "qcom,smb2360-bcl", + .data =3D &smb2360_data, + }, { + .compatible =3D "qcom,smb2370-bcl", + .data =3D &smb2370_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, bcl_match); + +static struct platform_driver bcl_driver =3D { + .probe =3D bcl_probe, + .driver =3D { + .name =3D "qcom-bcl-hwmon", + .of_match_table =3D bcl_match, + }, +}; + +module_platform_driver(bcl_driver); + +MODULE_DESCRIPTION("Qualcomm SPMI BCL HWMON driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Sat Jul 25 00:15:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAE48407CCF for ; Tue, 21 Jul 2026 18:30:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784658638; cv=none; b=kGA9V77YoZspjik6IJy231oWa1W1IVXoK71cJO7ndmcHrKC8BNxvpR9HXlELzAs47ksADRYgnwx9bJq7j/7YJ8hZTYwMcrckOqK+X2oALQ+vHAPMCjOkWzuiMsV4DqgsSV9vepfJL37pcIxs3nf1CvFlC+OZBq4a0PABtwJfRLc= ARC-Message-Signature: i=1; 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The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/pm7250b.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qc= om/pm7250b.dtsi index 43cab07126c5..1d358aeda9b2 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -89,6 +89,15 @@ pm7250b_typec: typec@1500 { status =3D "disabled"; }; =20 + sensor@1d00 { + compatible =3D "qcom,pm7250b-bcl"; + reg =3D <0x1d00>; + interrupts =3D , + ; + interrupt-names =3D "max-min", + "critical"; + }; + pm7250b_temp: temp-alarm@2400 { compatible =3D "qcom,spmi-temp-alarm"; reg =3D <0x2400>; --=20 2.43.0 From nobody Sat Jul 25 00:15:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C55546EF7D for ; Tue, 21 Jul 2026 18:30:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dt= s/qcom/hamoa-pmics.dtsi index 6a31a0adf8be..dbc4257c64ce 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi @@ -515,6 +515,15 @@ smb2360_0: pmic@7 { =20 status =3D "disabled"; =20 + sensor@4700 { + compatible =3D "qcom,smb2360-bcl"; + reg =3D <0x4700>; + interrupts =3D <0x7 0x47 0x0 IRQ_TYPE_EDGE_RISING>, + <0x7 0x47 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "max-min", + "critical"; + }; + smb2360_0_eusb2_repeater: phy@fd00 { compatible =3D "qcom,smb2360-eusb2-repeater"; reg =3D <0xfd00>; --=20 2.43.0 From nobody Sat Jul 25 00:15:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E6E240860E for ; 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Tue, 21 Jul 2026 11:30:44 -0700 (PDT) Received: from hu-manafm-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3147e1ca3efsm1185298eec.30.2026.07.21.11.30.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2026 11:30:44 -0700 (PDT) From: Manaf Meethalavalappu Pallikunhi Date: Wed, 22 Jul 2026 00:00:10 +0530 Subject: [PATCH v2 05/10] arm64: dts: qcom: pm8350c: Enable BCL sensor node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260722-qcom-bcl-hwmon-v2-5-febe2805e17b@oss.qualcomm.com> References: <20260722-qcom-bcl-hwmon-v2-0-febe2805e17b@oss.qualcomm.com> In-Reply-To: <20260722-qcom-bcl-hwmon-v2-0-febe2805e17b@oss.qualcomm.com> To: Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Stephen Boyd , Bjorn Andersson , Konrad Dybcio , Daniel Lezcano Cc: linux-hwmon@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mfd@lists.linux.dev, Gaurav Kohli , Manaf Meethalavalappu Pallikunhi X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/pm8350c.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qc= om/pm8350c.dtsi index 1a24e6439e36..8815868f9ad6 100644 --- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi @@ -20,6 +20,15 @@ pm8350c_temp_alarm: temp-alarm@a00 { #thermal-sensor-cells =3D <0>; }; =20 + sensor@4700 { + compatible =3D "qcom,pm8350c-bcl"; + reg =3D <0x4700>; + interrupts =3D <0x2 0x47 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x47 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "max-min", + "critical"; + }; + pm8350c_gpios: gpio@8800 { compatible =3D "qcom,pm8350c-gpio", "qcom,spmi-gpio"; reg =3D <0x8800>; @@ -41,6 +50,7 @@ pm8350c_pwm: pwm { #pwm-cells =3D <2>; status =3D "disabled"; }; + }; }; =20 --=20 2.43.0 From nobody Sat Jul 25 00:15:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACE1546F4BA for ; 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The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/pmh0101.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmh0101.dtsi b/arch/arm64/boot/dts/qc= om/pmh0101.dtsi index b1ec41325958..fd632b592d2e 100644 --- a/arch/arm64/boot/dts/qcom/pmh0101.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0101.dtsi @@ -43,6 +43,15 @@ pmh0101_temp_alarm: temp-alarm@a00 { #thermal-sensor-cells =3D <0>; }; =20 + sensor@4700 { + compatible =3D "qcom,pmh0101-bcl"; + reg =3D <0x4700>; + interrupts =3D <0x1 0x47 0x0 IRQ_TYPE_EDGE_RISING>, + <0x1 0x47 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "max-min", + "critical"; + }; + pmh0101_gpios: gpio@8800 { compatible =3D "qcom,pmh0101-gpio", "qcom,spmi-gpio"; reg =3D <0x8800>; --=20 2.43.0 From nobody Sat Jul 25 00:15:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82F63470449 for ; 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The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/pm8550.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qco= m/pm8550.dtsi index 896bcacb6490..fde76da37bac 100644 --- a/arch/arm64/boot/dts/qcom/pm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi @@ -45,6 +45,15 @@ pm8550_temp_alarm: temp-alarm@a00 { #thermal-sensor-cells =3D <0>; }; =20 + sensor@4700 { + compatible =3D "qcom,pm8550-bcl"; + reg =3D <0x4700>; + interrupts =3D <0x1 0x47 0x0 IRQ_TYPE_EDGE_RISING>, + <0x1 0x47 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "max-min", + "critical"; + }; + pm8550_gpios: gpio@8800 { compatible =3D "qcom,pm8550-gpio", "qcom,spmi-gpio"; reg =3D <0x8800>; --=20 2.43.0 From nobody Sat Jul 25 00:15:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB6A4471435 for ; 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The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi b/arch/arm64/= boot/dts/qcom/pmih0108-kaanapali.dtsi index b73b0e82c3d3..67b77272b0cf 100644 --- a/arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi @@ -49,6 +49,15 @@ pmih0108_e1_temp_alarm: temp-alarm@a00 { #thermal-sensor-cells =3D <0>; }; =20 + sensor@4700 { + compatible =3D "qcom,pmih0108-bcl"; + reg =3D <0x4700>; + interrupts =3D <0x7 0x47 0x0 IRQ_TYPE_EDGE_RISING>, + <0x7 0x47 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "max-min", + "critical"; + }; + pmih0108_e1_gpios: gpio@8800 { compatible =3D "qcom,pmih0108-gpio", "qcom,spmi-gpio"; reg =3D <0x8800>; --=20 2.43.0 From nobody Sat Jul 25 00:15:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A56746E017 for ; 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The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/pmih0108.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmih0108.dtsi b/arch/arm64/boot/dts/q= com/pmih0108.dtsi index 1c875995d881..1f91e788010b 100644 --- a/arch/arm64/boot/dts/qcom/pmih0108.dtsi +++ b/arch/arm64/boot/dts/qcom/pmih0108.dtsi @@ -49,6 +49,15 @@ pmih0108_temp_alarm: temp-alarm@a00 { #thermal-sensor-cells =3D <0>; }; =20 + sensor@4700 { + compatible =3D "qcom,pmih0108-bcl"; + reg =3D <0x4700>; + interrupts =3D <0x7 0x47 0x0 IRQ_TYPE_EDGE_RISING>, + <0x7 0x47 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "max-min", + "critical"; + }; + pmih0108_gpios: gpio@8800 { compatible =3D "qcom,pmih0108-gpio", "qcom,spmi-gpio"; reg =3D <0x8800>; --=20 2.43.0 From nobody Sat Jul 25 00:15:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F13C2472557 for ; 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The BCL monitors battery voltage and current, providing hardware interrupts when configurable thresholds are violated. Signed-off-by: Manaf Meethalavalappu Pallikunhi --- arch/arm64/boot/dts/qcom/smb2370.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/smb2370.dtsi b/arch/arm64/boot/dts/qc= om/smb2370.dtsi index 80f3fdae5705..79b013fa2c11 100644 --- a/arch/arm64/boot/dts/qcom/smb2370.dtsi +++ b/arch/arm64/boot/dts/qcom/smb2370.dtsi @@ -10,6 +10,15 @@ smb2370_j_e2: pmic@9 { #address-cells =3D <1>; #size-cells =3D <0>; =20 + sensor@4700 { + compatible =3D "qcom,smb2370-bcl"; + reg =3D <0x4700>; + interrupts =3D <0x9 0x47 0x0 IRQ_TYPE_EDGE_RISING>, + <0x9 0x47 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "max-min", + "critical"; + }; + smb2370_j_e2_eusb2_repeater: phy@fd00 { compatible =3D "qcom,smb2370-eusb2-repeater"; reg =3D <0xfd00>; --=20 2.43.0