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Wed, 22 Jul 2026 02:56:09 -0700 (PDT) From: Peter Griffin Date: Wed, 22 Jul 2026 10:55:52 +0100 Subject: [PATCH v2 1/5] dt-bindings: arm: google: Add dt bindings for frankel/blazer/mustang Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260722-contrib-pg-pixel10-initial-dts-v2-1-3abae9717feb@linaro.org> References: <20260722-contrib-pg-pixel10-initial-dts-v2-0-3abae9717feb@linaro.org> In-Reply-To: <20260722-contrib-pg-pixel10-initial-dts-v2-0-3abae9717feb@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Greg Kroah-Hartman , Jiri Slaby , Catalin Marinas , Will Deacon , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org, soc@lists.linux.dev, Douglas Anderson , Juan Yescas , RD Babiera , Brian Norris , William McVicker , kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3423; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=jU9hEfZSLyLN+jsh1uG4a2eIaQF/rbTm9P6jCmxJNGA=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBqYJO12UR3M+7UC8CvEUp8eg465llr3PM/kVBu0 3IVS0lprJiJAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCamCTtQAKCRDO6LjWAjRy utBND/9BS9YFGnYwgx5BNfo5rWAgybD6ZbSVdu5hqHcWrvC1RSl8ppFqr6hnSqiLL0WI2ZdVc1b 3P1k56Svr39AB4rtu8umDsSPeJJzT+9yR3TxpoAJ2fmC0A5oKGEgjcD9HBRTPpThBrxGIC+t/Ka l+lA5dDXcKbaAxb6GeYVOHQLQNTIl6j3fbNicDF1OV/hc0Uu/s5+1ZGsxYAXPqOft420r1zhWWw x1/reRPoVs8vxK+sY2qVipvx7BAH/cnGpnssel2EM7F4TPSzGPOLvR7Nn2zvTyyNjYPHKZzsIJW nY32CZtzwaJiEiduw67DGPuM69PyFFdqnADFWLmWqVInDP3R2MWcsSSq7CjJIKzExHZMtO5l+8Q NV2s3EoMnSkMDY6macBGnIxww5H7B7YBabNgM+swWhQ5+xDLMkwGJg6UNafVtfS/cwH4WLIGRG2 NT56GJ6RchmMz6ZaeBcTNwgTogns+Bona7cNtJNayO98OdGGwigZ/UeFRa6oTd87HK7pmGyHZPh uBoO5FacLucnKz5GCp7D7h0yVr+P0Tuau3/eiH+xC5y+1BaLPGn8F7WZf3+vHEW4C2T0keHn0LX /GQTku/Sq8FMS1xwSvhXe9K0IcZ39rguhR975Xdha2J4ztncgzuJ0W1Q52wWtwi3nTIHsJFqndW 8ULK6ahFXPlXK+Q== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Add binding documentation for Tensor G5 SoC (Laguna) which is referred to in code as "lga" and three of the boards that use the Laguna SoC Frankel (Pixel 10), Blazer (Pixel 10 Pro) and Mustang (Pixel 10 Pro XL). Additionally update to use a more efficient and scalable way to express the various names a SoC is known by. Co-developed-by: Douglas Anderson Signed-off-by: Douglas Anderson Signed-off-by: Peter Griffin Reviewed-by: Brian Norris Reviewed-by: Krzysztof Kozlowski Tested-by: Brian Norris --- Changes in v2: * Update ect rule as per Krysztof suggestion * Remove all the pre-production variants (EVT, DVT etc) * The equivalent patch in the previous submission is https://lore.kernel.org/lkml/05c833f0-15bc-4a86-9ac4-daf835fe4393@kernel= .org/ but this is now almost entirely different diff. I've added the co-developed-by tag as I've kept the more efficient way to express the names a SoC is known by. --- Documentation/devicetree/bindings/arm/google.yaml | 48 ++++++++++++++-----= ---- 1 file changed, 29 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/google.yaml b/Documentat= ion/devicetree/bindings/arm/google.yaml index 99961e5282e5..b5977e20f393 100644 --- a/Documentation/devicetree/bindings/arm/google.yaml +++ b/Documentation/devicetree/bindings/arm/google.yaml @@ -13,27 +13,16 @@ description: | ARM platforms using SoCs designed by Google branded "Tensor" used in Pix= el devices. =20 - Currently upstream this is devices using "gs101" SoC which is found in P= ixel - 6, Pixel 6 Pro and Pixel 6a. - - Google have a few different names for the SoC: - - Marketing name ("Tensor") - - Codename ("Whitechapel") - - SoC ID ("gs101") - - Die ID ("S5P9845") - - Likewise there are a couple of names for the actual device - - Marketing name ("Pixel 6") - - Codename ("Oriole") - - Devicetrees should use the lowercased SoC ID and lowercased board codena= me, - e.g. gs101 and gs101-oriole. + Currently upstream this is devices using gs101 SoC which is found in Pix= el + 6, Pixel 6 Pro and Pixel 6a and Laguna SoC canonically referred to as lga + found in Pixel 10, Pixel 10 Pro and Pixel 10 Pro XL. =20 properties: $nodename: const: '/' compatible: oneOf: + # Google Tensor G1 AKA gs101 AKA whitechapel AKA Die ID S5P9845 boar= ds - description: Google Pixel 6 or 6 Pro (Oriole or Raven) items: - enum: @@ -41,14 +30,35 @@ properties: - google,gs101-raven - const: google,gs101 =20 - # Bootloader requires empty ect node to be present + # Google Tensor G5 AKA lga (laguna) SoC and boards + - description: + Google Pixel 10, 10 Pro, 10 Pro XL (Frankel, Blazer, + Mustang). + items: + - enum: + - google,lga-blazer + - google,lga-frankel + - google,lga-mustang + - const: google,lga + ect: type: object additionalProperties: false =20 -required: - - ect - additionalProperties: true =20 +allOf: + # Bootloader requires empty ect node to be present + - if: + properties: + compatible: + contains: + const: google,gs101 + then: + required: + - ect + else: + properties: + ect: false + ... --=20 2.55.0.229.g6434b31f56-goog From nobody Fri Jul 24 23:30:47 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6375C49550C for ; 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Piccoli" Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org, soc@lists.linux.dev, Douglas Anderson , Juan Yescas , RD Babiera , Brian Norris , William McVicker , kernel-team@android.com, Peter Griffin , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1322; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=UIAuCpn9sBr07oQ2RwIwe4pVzRGN2evRfhuSeBFU/iE=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBqYJO2S5G3RXrgDdc0iZBu1hTMoCLLrgE6SJbjY TVJinLwtlOJAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCamCTtgAKCRDO6LjWAjRy uqBaEACecjhHzGhUtBGP2AxwpzQCb4I9hjLzjVA8jel/swb5ul1VNx1d33WlrwkkFTN37u+iL6f RToG6IHnRdaPjHsxUYQLr5fWNm2eb0Z84Lf7e6k2slRSz0W8CvExX797OFAIcT7OEiUNlZLsRMH ksu5N7kYRnG6YnvIf9qo+NHRWWsAG3U1RrrTAbtc0fQZrax1ruAc9ku5b5fge2NLdft9CSNKWlo rg4Gd/sQ5eoT7f5Da4zLKz3xnkt18jGUuqPZ8CZihaQ5eKs2Gf9zwCMU+ZAZsBgbpwXnHUhvZHF o+dcAJHqoId0jbRYc2rK5I8gBj5uLvTEr/Aug8sxICYE15Q8wVjI9UB4vQ3ds88Kehjw5OC3sN+ /AfaQRq4yBX8KTFf2HDtl/IFm8Zg1pBDmkB4mROcen7Lly6fvdCBPp6Cj5SZFcn0jiDCD7gRMSu XTMVmblIjGBcMllV4+aYIjXsWabeJFGKxV0fppeVhQPiSUN/apDQbejChCTeB6wUQzpXyRvIWVS nFxJ7I8LlLBn/zGwuFKB2qiXM2Ak1x+T5suXnWeAvWFM/9nqdQ5kEqLRvsO2r2CRD7kLBvr5aeg QWSfClbNCzjPa6WsUkXVRyDc+NKTs+iBTjJLW/riV6YG4AooRnm8elO2hpnxbNr6yloQjXtp12X 4gZTgROw5MX8Z3w== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA From: Douglas Anderson The Google Tensor G5 SoC (known as "laguna" and canonically written in code as "lga") has a UART based on Designware IP. The UART appears to work reasonably well, at least for serial console, with the existing driver in Linux. Add a compatible for this UART based on the canonical "lga" name for this SoC with a fallback to the existing "snps,dw-apb-uart". Signed-off-by: Douglas Anderson Reviewed-by: Krzysztof Kozlowski Signed-off-by: Peter Griffin Reviewed-by: Brian Norris Tested-by: Brian Norris --- Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml= b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 685c1eceb782..24589466a4be 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -54,6 +54,7 @@ properties: - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart + - google,lga-uart - rockchip,px30-uart - rockchip,rk1808-uart - rockchip,rk3036-uart --=20 2.55.0.229.g6434b31f56-goog From nobody Fri Jul 24 23:30:47 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5FC34963A9 for ; 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Wed, 22 Jul 2026 02:56:12 -0700 (PDT) Received: from gpeter-l.roam.corp.google.com ([2a00:23c7:314c:4601:ea7:d5d4:79db:6d52]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85c532d4sm4414533f8f.22.2026.07.22.02.56.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 02:56:11 -0700 (PDT) From: Peter Griffin Date: Wed, 22 Jul 2026 10:55:54 +0100 Subject: [PATCH v2 3/5] arm64: dts: google: Add dts directory for Google-designed silicon Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260722-contrib-pg-pixel10-initial-dts-v2-3-3abae9717feb@linaro.org> References: <20260722-contrib-pg-pixel10-initial-dts-v2-0-3abae9717feb@linaro.org> In-Reply-To: <20260722-contrib-pg-pixel10-initial-dts-v2-0-3abae9717feb@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Greg Kroah-Hartman , Jiri Slaby , Catalin Marinas , Will Deacon , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org, soc@lists.linux.dev, Douglas Anderson , Juan Yescas , RD Babiera , Brian Norris , William McVicker , kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2691; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=SHnnOHycO1M3KzDLgoFhcyeeohmukEIp6feU5iRFhhM=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBqYJO2NOwczhyNRIb4wdxPQ/5deipkuZ22m7G6C 3osSGVwLVSJAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCamCTtgAKCRDO6LjWAjRy uoP6D/9xSTEuwM0zy6yW60c2SdWiUsBjFzss9dmvogtPOMldBMfPCutZSeoZh/UMm7wb8dfBGu8 wSUn1z9D0BA9VaE2oOtE6wgKfjEhJ+liXJbqwGG5rTwcGOBAyKItpqBNuKEH1JoAbMuQ3JY/m23 61bcf2dT3PPPM8C/MVaIeII1H2NO56X4HTEq/LQEULXAphVi6UX1pSTS8MYoBzhTpNjTAG4Nfwu LFxEnqs12faS/yylh9vn+m2W0jPUpThWUCsmysRf1lVnV70iTP9Cvfli+tJm8Evonit5/zmCPgF uAWoJTAv9vBY8tHVneok2tVV3W0a5W5ky6fWntstAZSLTTLjb5OGx9OGaMVUovYhvFUb/KsDWIS ItlfYpSSzbfV49aBqxJ4LG7B+NlR0JesXlCbvDVOks0b3/CRMBuGmcgUDXZAZkGu02RNsfFlt6B ynDfop26Vyu4+1I/vg+53vcqwCaY2vVOLgrwJ1DyxnP40V42AgPjpGWgkrfO5F0xBS5gG74eA8a mIvMoqRXD4tY/DciX6hWq6jNso6V3v12ijydSKmHs5OMfLB2tZdjw/BW79Bj26SmiLb+Ut8cyd4 ncBUPXYTfujc1RQIC5N41vL/IdnT/KHI2FME21v9mCxdd1yKjQj9Wa8b0B8U+xgvuota8afu2/r 0a/92dGFDVfSitQ== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA From: Douglas Anderson The first four Google Tensor SoCs were offshoots of Samsung Exynos SoCs and their device trees were organized under the "exynos/google" directory. Starting with the Google Tensor G5 SoC in Pixel 10 phones, Google Tensor SoCs are now of Google's own design. Add a location in the tree to store these device tree files. Changes by Peter Griffin * update config symbol help with at least 4 lines to avoid checkpatch warning Signed-off-by: Douglas Anderson Signed-off-by: Peter Griffin Reviewed-by: Brian Norris Reviewed-by: Krzysztof Kozlowski Tested-by: Brian Norris --- MAINTAINERS | 1 + arch/arm64/Kconfig.platforms | 8 ++++++++ arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/google/Makefile | 1 + 4 files changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c61ef65d71ef..010d4de81a1b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11012,6 +11012,7 @@ F: Documentation/devicetree/bindings/phy/google,lga= -usb-phy.yaml F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.= yaml F: Documentation/devicetree/bindings/usb/google,lga-dwc3.yaml F: arch/arm64/boot/dts/exynos/google/ +F: arch/arm64/boot/dts/google/ F: drivers/clk/samsung/clk-gs101.c F: drivers/phy/phy-google-usb.c F: drivers/soc/samsung/gs101-pmu.c diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 72c812e76b0b..f83eb4ea878c 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -147,6 +147,14 @@ config ARCH_EXYNOS help This enables support for ARMv8 based Samsung Exynos SoC family. =20 +config ARCH_GOOGLE + bool "Google-Designed SoC family" + help + This enables support for Google Tensor SoCs starting at the + Google Tensor G5 (Laguna) found in Pixel 10 and later phones. + Tensor G1 to G4 are offshoots of the Exynos family and are + enabled via ARCH_EXYNOS. + config ARCH_K3 bool "Texas Instruments Inc. K3 multicore SoC architecture" select SOC_TI diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 98ec8f1b76e4..566f0c863d55 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -18,6 +18,7 @@ subdir-y +=3D cavium subdir-y +=3D cix subdir-y +=3D exynos subdir-y +=3D freescale +subdir-y +=3D google subdir-y +=3D hisilicon subdir-y +=3D intel subdir-y +=3D lg diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/goog= le/Makefile new file mode 100644 index 000000000000..a6b187e2d631 --- /dev/null +++ b/arch/arm64/boot/dts/google/Makefile @@ -0,0 +1 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) --=20 2.55.0.229.g6434b31f56-goog From nobody Fri Jul 24 23:30:47 2026 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A44C335C692 for ; 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Wed, 22 Jul 2026 02:56:13 -0700 (PDT) Received: from gpeter-l.roam.corp.google.com ([2a00:23c7:314c:4601:ea7:d5d4:79db:6d52]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85c532d4sm4414533f8f.22.2026.07.22.02.56.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 02:56:13 -0700 (PDT) From: Peter Griffin Date: Wed, 22 Jul 2026 10:55:55 +0100 Subject: [PATCH v2 4/5] arm64: dts: google: Add initial dts for frankel/blazer/mustang Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260722-contrib-pg-pixel10-initial-dts-v2-4-3abae9717feb@linaro.org> References: <20260722-contrib-pg-pixel10-initial-dts-v2-0-3abae9717feb@linaro.org> In-Reply-To: <20260722-contrib-pg-pixel10-initial-dts-v2-0-3abae9717feb@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Greg Kroah-Hartman , Jiri Slaby , Catalin Marinas , Will Deacon , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org, soc@lists.linux.dev, Douglas Anderson , Juan Yescas , RD Babiera , Brian Norris , William McVicker , kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=15623; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=5/Ox4AZKrNAcywtIaf5yMYb3vmYg681flxnKWa9di6A=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBqYJO2fFUcCXu+bVxz459upIHNZtKZFVSG+ErdL B4iFy2rQAeJAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCamCTtgAKCRDO6LjWAjRy ur3sD/9Jd1XShReo+e5Ajhg4g/nxciPr20Cjv1UNFdwzM7ASCpJeJIzcx7vruKPhkUSjntNbYmx LDzRG4gME4eHlGJqo8KV++Cr1Fd7OIbYt/MNCeJdkVzM4M0Qdh8ZqQvvU8ZS4bKZ5gu2Uewr1zG LfCzvXAAJPZmHRjFccGwuQJVmu7s8E2CSvII+1L8c9FdYHiuD+7l7OpKrIFAOBO/aSrucKl43ps xjDvKRM0msu3NDuoXB3BgtmGfTSpuMWPNVc1BtZFVYj3lcTlKycjCaCVcp8pH9mfn5ZojLc3JxR a0cRl0f6ikec5dx6z64Y1ovrFjiTr8Wdq5z9U9o24bzzKbWGa2yv1eTTv0tjO3ZdvGVWTNw/UT1 QGe/ab0Rqy0lTND4j3f32er6hVPDPgsbKk74rTW2PR5ueqbwTb7i6VTE6A0zwcbXp6lXeO86d0W qLlX6FBqfXsv+8mzooRUOWXYv76XB9TnCay/rlv52dq+FecKVHYAcJsf/WQY5EfxvEcR22sUtxh 41ECOXfoluLvb6uuXmn/oE4GBQ/EouxV9EXs7VQevSqiBppSEuKeOQo0uyL36D4rB2ScYrGh45k EehFlIrHfyHeL3hDEPSQfmqC8piZIu8ys+RwlFd8TuX270eCNcrX4+vOVec27AwQlaoriH6zAIK DpBBXXx8wj/b8WQ== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA From: Douglas Anderson Add initial device trees for frankel (Pixel 10), blazer (Pixel 10 Pro) and mustang (Pixel 10 Pro XL). These device trees are enough to boot to a serial prompt using an initramfs. Currently only Laguna B0 silicon found in mass production phones is officially supported. Further revisions such as A0 silicon and EVT devices maybe added in the future if they are useful. As of today, these device trees boot fine on EVT devices with A0 silicon. Many things can be noted about these device trees: 1. Even newer versions of the bootloader will still error out if they don't find a UFS node to add calibration data to. Until UFS is supported, we provide a bogus UFS node for the bootloader. While the bootloader could be changed, there is no long-term benefit since eventually the device tree will have a UFS node. 2. They purposely choose to use the full 64-bit address and size cells for the root node and the `soc@0` node. Although I haven't tested the need for this, I presume the arguments made in commit bede7d2dc8f3 ("arm64: dts: qcom: sdm845: Increase address and size cells for soc") would apply here. 3. Though it looks as if the UART is never enabled, the bootloader knows to enable the UART when the console is turned on. Baud rate is configurable in the bootloader so is never hardcoded in the device tree. Changes by Peter Griffin: - Remove dtbo overlay approach and add individual board dts - Update to lga-pixel-common naming like gs101-pixel-common - Reorder nodes alpha-numerically by the node name - Add ramoops reserved-memory (tested with console=3Dpstore) - Add reserved-memory for bootloader & gsa logs - Add reserved-memory for Android BootLoader ABL (used on Watchdog reset to extract boolotader logs / parse breadcrumbs / ramdump etc). - Add osc 38.4Mhz fixed-clock Signed-off-by: Douglas Anderson Co-developed-by: Peter Griffin Signed-off-by: Peter Griffin Reviewed-by: Brian Norris Tested-by: Brian Norris --- Changes in v2 (by Peter Griffin): * Remove dtbo overlay approach and add individual board dts * Update to lga-pixel-common naming like gs101-pixel-common * Reorder nodes alpha-numerically by the node name * Add ramoops reserved-memory (tested with console=3Dpstore) * Add reserved-memory for bootloader & gsa logs * Add reserved-memory for Android BootLoader ABL (used on Watchdog reset to extract boolotader logs / parse breadcrumbs / ramdump etc). * Add osc 38.4Mhz fixed-clock --- arch/arm64/boot/dts/google/Makefile | 5 + arch/arm64/boot/dts/google/lga-blazer.dts | 15 + arch/arm64/boot/dts/google/lga-frankel.dts | 16 + arch/arm64/boot/dts/google/lga-mustang.dts | 15 + arch/arm64/boot/dts/google/lga-pixel-common.dtsi | 23 ++ arch/arm64/boot/dts/google/lga.dtsi | 423 +++++++++++++++++++= ++++ 6 files changed, 497 insertions(+) diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/goog= le/Makefile index a6b187e2d631..4e833b2561e0 100644 --- a/arch/arm64/boot/dts/google/Makefile +++ b/arch/arm64/boot/dts/google/Makefile @@ -1 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) + +dtb-$(CONFIG_ARCH_GOOGLE) +=3D \ + lga-blazer.dtb \ + lga-frankel.dtb \ + lga-mustang.dtb diff --git a/arch/arm64/boot/dts/google/lga-blazer.dts b/arch/arm64/boot/dt= s/google/lga-blazer.dts new file mode 100644 index 000000000000..0894606624f8 --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-blazer.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Blazer Device Tree (Pixel 10 Pro) + * + * Copyright 2021-2023 Google LLC + */ + +/dts-v1/; + +#include "lga-pixel-common.dtsi" + +/ { + model =3D "Blazer"; + compatible =3D "google,lga-blazer", "google,lga"; +}; diff --git a/arch/arm64/boot/dts/google/lga-frankel.dts b/arch/arm64/boot/d= ts/google/lga-frankel.dts new file mode 100644 index 000000000000..57df197a544f --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-frankel.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Frankel Device Tree (Pixel 10) + * + * Copyright 2021-2023 Google LLC + */ + +/dts-v1/; + +#include "lga-pixel-common.dtsi" + +/ { + model =3D "Frankel"; + compatible =3D "google,lga-frankel", "google,lga"; +}; + diff --git a/arch/arm64/boot/dts/google/lga-mustang.dts b/arch/arm64/boot/d= ts/google/lga-mustang.dts new file mode 100644 index 000000000000..6ac0b5ef22ff --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-mustang.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Mustang Device Tree (Pixel 10 Pro XL) + * + * Copyright 2021-2023 Google LLC + */ + +/dts-v1/; + +#include "lga-pixel-common.dtsi" + +/ { + model =3D "Mustang"; + compatible =3D "google,lga-mustang", "google,lga"; +}; diff --git a/arch/arm64/boot/dts/google/lga-pixel-common.dtsi b/arch/arm64/= boot/dts/google/lga-pixel-common.dtsi new file mode 100644 index 000000000000..57c318ab44c9 --- /dev/null +++ b/arch/arm64/boot/dts/google/lga-pixel-common.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Pixel 10 family common dtsi. + * + * Copyright 2024-2025 Google LLC. + */ + +#include "lga.dtsi" + +&{/} { + chosen { + stdout-path =3D "serial0"; + }; + + aliases { + serial0 =3D "/soc@0/serial@db62000"; /* &lsion_cli16_uart */ + ufs0 =3D "/ufs-placeholder"; /* &ufs - TODO "/soc@0/ufs@3c400000" */ + }; +}; + +&osc { + clock-frequency =3D <38400000>; +}; diff --git a/arch/arm64/boot/dts/google/lga.dtsi b/arch/arm64/boot/dts/goog= le/lga.dtsi new file mode 100644 index 000000000000..343156a8c039 --- /dev/null +++ b/arch/arm64/boot/dts/google/lga.dtsi @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Google Tensor G5 (laguna) SoC rev B0 + * + * Copyright 2024-2025 Google LLC. + */ + +/dts-v1/; + +#include +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + + osc: clock-38400000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + hayes_0: cpu@0 { + compatible =3D "arm,cortex-a520"; + reg =3D <0x000>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <258>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd0>; + }; + + hayes_1: cpu@100 { + compatible =3D "arm,cortex-a520"; + reg =3D <0x100>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <258>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd1>; + }; + + hunter_0: cpu@200 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x200>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd2>; + }; + + hunter_1: cpu@300 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x300>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd3>; + }; + + hunter_2: cpu@400 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x400>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd4>; + }; + + hunter_3: cpu@500 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x500>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd5>; + }; + + hunter_4: cpu@600 { + compatible =3D "arm,cortex-a725"; + reg =3D <0x600>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <891>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd6>; + }; + + hunterelp_0: cpu@700 { + compatible =3D "arm,cortex-x4"; + reg =3D <0x700>; + + #cooling-cells =3D <2>; + capacity-dmips-mhz =3D <1024>; + device_type =3D "cpu"; + enable-method =3D "psci"; + power-domain-names =3D "psci"; + power-domains =3D <&cpu_pd7>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&hayes_0>; + }; + core1 { + cpu =3D <&hayes_1>; + }; + core2 { + cpu =3D <&hunter_0>; + }; + core3 { + cpu =3D <&hunter_1>; + }; + core4 { + cpu =3D <&hunter_2>; + }; + core5 { + cpu =3D <&hunter_3>; + }; + core6 { + cpu =3D <&hunter_4>; + }; + core7 { + cpu =3D <&hunterelp_0>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_lit_c2: cpu-lit-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <132>; + exit-latency-us =3D <296>; + min-residency-us =3D <3610>; + + idle-state-name =3D "cpu-lit-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + + cpu_mid1_c2: cpu-mid1-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <130>; + exit-latency-us =3D <274>; + min-residency-us =3D <2720>; + + idle-state-name =3D "cpu-mid1-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + + cpu_mid2_c2: cpu-mid2-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <130>; + exit-latency-us =3D <274>; + min-residency-us =3D <2720>; + + idle-state-name =3D "cpu-mid2-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + + cpu_big_c2: cpu-big-c2 { + compatible =3D "arm,idle-state"; + + entry-latency-us =3D <110>; + exit-latency-us =3D <413>; + min-residency-us =3D <3950>; + + idle-state-name =3D "cpu-big-c2"; + local-timer-stop; + + arm,psci-suspend-param =3D <0x40000003>; + }; + }; + + domain-idle-states { + cluster_1_c3: cluster-1-c3 { + compatible =3D "domain-idle-state"; + + entry-latency-us =3D <325>; + exit-latency-us =3D <553>; + min-residency-us =3D <10000>; + + idle-state-name =3D "cluster-1-c3"; + + arm,psci-suspend-param =3D <0x40010033>; + }; + + cluster_2_c3: cluster-2-c3 { + compatible =3D "domain-idle-state"; + + entry-latency-us =3D <345>; + exit-latency-us =3D <673>; + min-residency-us =3D <10000>; + + idle-state-name =3D "cluster-2-c3"; + + arm,psci-suspend-param =3D <0x40010033>; + }; + + cluster_c4_deep: cluster-c4-deep { + compatible =3D "domain-idle-state"; + + entry-latency-us =3D <510>; + exit-latency-us =3D <1027>; + min-residency-us =3D <10000>; + + idle-state-name =3D "cluster-c4-deep"; + + arm,psci-suspend-param =3D <0x40020333>; + }; + }; + }; + + memory: memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_lit_c2>; + power-domains =3D <&cpu_top_cl>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_lit_c2>; + power-domains =3D <&cpu_top_cl>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid1_c2>; + power-domains =3D <&cpucl1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid1_c2>; + power-domains =3D <&cpucl1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid1_c2>; + power-domains =3D <&cpucl1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid2_c2>; + power-domains =3D <&cpucl2>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_mid2_c2>; + power-domains =3D <&cpucl2>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cpu_big_c2>; + power-domains =3D <&cpucl2>; + }; + + cpucl1: power-domain-cluster-1 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_1_c3>; + power-domains =3D <&cpu_top_cl>; + }; + + cpucl2: power-domain-cluster-2 { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_2_c3>; + power-domains =3D <&cpu_top_cl>; + }; + + cpu_top_cl: power-domain-top-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_c4_deep>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * Store ramoops at a known location in DRAM, for access by the ABL + * following a crash-reset. + */ + ramoops@95200000 { + compatible =3D "ramoops"; + reg =3D <0x0 0x95200000 0x0 0x400000>; + console-size =3D <0x200000>; + pmsg-size =3D <0x200000>; + }; + + /* bootloader logs */ + bldr_log_reserved: bldr-log-reserved@95600000 { + reg =3D <0x0 0x95600000 0x0 0x100000>; + no-map; + }; + + /* gsa logs */ + gsa_reserved_log: gsa-reserved-log@a61b0000 { + reg =3D <0x0 0xa61b0000 0x0 0x00004000>; + no-map; + }; + + /* Android BootLoader (ABL) for ramdump/coredump processing */ + abl@be000000 { + reg =3D <0x0 0xbe000000 0x0 0x1000000>; + no-map; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0 0x10 0>; + + dma-ranges =3D <0 0 0 0 0x10 0>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + gic: interrupt-controller@5880000 { + compatible =3D "arm,gic-v3"; + reg =3D <0 0x05880000 0 0x10000>, + <0 0x05900000 0 0x200000>; + ranges; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + #interrupt-cells =3D <4>; + interrupt-controller; + interrupts =3D ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&hayes_0 &hayes_1 + &hunter_0 &hunter_1 &hunter_2 + &hunter_3 &hunter_4>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&hunterelp_0>; + }; + }; + }; + + lsion_cli16_uart: serial@db62000 { + compatible =3D "google,lga-uart", "snps,dw-apb-uart"; + reg =3D <0 0x0db62000 0 0x100>; + + clock-frequency =3D <200000000>; + interrupts =3D ; + reg-io-width =3D <4>; + reg-shift =3D <2>; + + status =3D "disabled"; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; 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Wed, 22 Jul 2026 02:56:14 -0700 (PDT) Received: from gpeter-l.roam.corp.google.com ([2a00:23c7:314c:4601:ea7:d5d4:79db:6d52]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85c532d4sm4414533f8f.22.2026.07.22.02.56.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 02:56:14 -0700 (PDT) From: Peter Griffin Date: Wed, 22 Jul 2026 10:55:56 +0100 Subject: [PATCH v2 5/5] arm64: defconfig: enable Tensor G5 SoC family Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260722-contrib-pg-pixel10-initial-dts-v2-5-3abae9717feb@linaro.org> References: <20260722-contrib-pg-pixel10-initial-dts-v2-0-3abae9717feb@linaro.org> In-Reply-To: <20260722-contrib-pg-pixel10-initial-dts-v2-0-3abae9717feb@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Greg Kroah-Hartman , Jiri Slaby , Catalin Marinas , Will Deacon , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org, soc@lists.linux.dev, Douglas Anderson , Juan Yescas , RD Babiera , Brian Norris , William McVicker , kernel-team@android.com, Peter Griffin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=677; i=peter.griffin@linaro.org; h=from:subject:message-id; bh=oIzmlAN/xUiGauIafN2ymeVSPRAXQ0H9cGKuE1HfPGQ=; b=owEBbQKS/ZANAwAKAc7ouNYCNHK6AcsmYgBqYJO3DxirCREaSZRzg4By9L4oe1J/cKMZY4ZRt ZPqiKTOSPuJAjMEAAEKAB0WIQQO/I5vVXh1DVa1SfzO6LjWAjRyugUCamCTtwAKCRDO6LjWAjRy utGoD/sGLlwsGbwkdHEoU3rAfAkSpRk76WlD1svFDSQzLco2bqGuiTMl95XleeZ8dmzd096IdtW H30hsxlgxBJYlta1JVJ9bJ6Pr4QZdcqUozZHu014CLJPwbUgN05bdvIPEo1PPWzxmqU5Gh1nwtS MRQWy4EGtgrITrtH/nFixj/0hyF8ybyszDS7TXB+pJm8PJO0zpKs5afVVF2laknXV/aIwGCtl35 IrUkDWIFLztAUmtjRgQ48VRHKgUoKVaGpyh2BKm9DfBDWwBn+wkHL+ReniPyQZ/ilLOx1XvjhnV 7NofygNm8k8wD1uUtqLpWjZyhLipwz9A2eRG9r8wz2y1zfcNxnHb1yBtIYGbwQGGzE8aY2z+3rn gfTc/LZywh1O7NMTE0Wgn9tdfHTJCQSqN1l1GR4bL6eZzIZB2WJu6LMVkaaPsTLRRWF04i1ScrG UCLELmalD5o44hHK0IRMwgbCgo3gZqGtTSTCDWuLX+vZArU/FJ97qZ73VJUkUmWpHPg2ZTNuwyp IhNuRKnMPh66HGyXCx34fj76bLz8dm8zeQeSKWLl9GbpVKU1/fBilq5BoSsG/wiQ/ianK2TNYkZ fVXm4MVq//TvqkvYyLr8o8co/LJT81FTfF5gRCU9Vm0hAwz0zG81Q/shtwCJa1ZzyOAhK0Ei0/9 WKg+qry3+sd1fyw== X-Developer-Key: i=peter.griffin@linaro.org; a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Enable the Google Tensor G5 (Laguna) SoC family in the arm64 defconfig. This SoC family is found in Pixel 10 and later phones. Signed-off-by: Peter Griffin Reviewed-by: Brian Norris Tested-by: Brian Norris --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f4dfd0cc853c..930a4f27ee56 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -50,6 +50,7 @@ CONFIG_ARCH_BLAIZE=3Dy CONFIG_ARCH_BST=3Dy CONFIG_ARCH_CIX=3Dy CONFIG_ARCH_EXYNOS=3Dy +CONFIG_ARCH_GOOGLE=3Dy CONFIG_ARCH_SPARX5=3Dy CONFIG_ARCH_K3=3Dy CONFIG_ARCH_LG1K=3Dy --=20 2.55.0.229.g6434b31f56-goog