From nobody Sat Jul 25 00:58:59 2026 Received: from canpmsgout01.his.huawei.com (canpmsgout01.his.huawei.com [113.46.200.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BF5831F986 for ; Tue, 21 Jul 2026 12:54:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.216 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784638444; cv=none; b=EAH/wB6PzQUAEfMy0fu8k8NSXyUYY5dgRPxTO5THk1fv+gLlyw6R14/Px+bluvs9YbxvGz0jpkTLq8cbdSoiNTbF5Gv/ziBrzLFWfB7dRGAm4BSQNK8ZKhdwjeJx/bBQyZYqyty40ZcNA7QW66FQ7xx8oaLUoiZIZHt5Y6wd/3Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784638444; c=relaxed/simple; bh=AEUQmxjwYu+uAhXf6t1ZGts2Mg58UzOsXy/31c6nlPs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QpC94OUjWV4q61jfzg+7LAJ8unpZId7lfH6jSbk1YjOq/75u11YWrngA/r/zWmGHxIanJA1m2wZDUKHIPwIdkhJEvW+1MdUKxF54wF6mXA/yQ6hyVXuUaTqZEUUlG3+rl9rDwOxPGorjw2f7VAygn0RzW7RRTeO30iAuugkupP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=G8SjaOBa; arc=none smtp.client-ip=113.46.200.216 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="G8SjaOBa" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=fYw3POhAXYqr/Iwv+AX1BKOL3bCwbDJzR2L11+7RLYY=; b=G8SjaOBaPMEXOYTv/u/SRq54bytD+OEXpy9nTQtTqdG/3N/qd76AFBhtRLpzlXf16jleognrd gx+ZMUzRzgxB9zdoq+XxGvgCAZ+C119nEXGyR/kdFHGeKJVqe8iGTyFvYtqn+fh9j/tszxj9y6l gch8WN1/z2x2447Em/pYKZo= Received: from mail.maildlp.com (unknown [172.19.163.0]) by canpmsgout01.his.huawei.com (SkyGuard) with ESMTPS id 4h4HC847VGz1T4Hh; Tue, 21 Jul 2026 20:44:36 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id EBF3D40561; Tue, 21 Jul 2026 20:53:55 +0800 (CST) Received: from kwepemq100007.china.huawei.com (7.202.195.175) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 21 Jul 2026 20:53:55 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 21 Jul 2026 20:53:55 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH for drm-misc-fixes v2 1/2] drm/hisilicon/hibmc: Modify the method of obtaining the hpd_status Date: Tue, 21 Jul 2026 20:43:23 +0800 Message-ID: <20260721124324.1885856-2-shiyongbang@huawei.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260721124324.1885856-1-shiyongbang@huawei.com> References: <20260721124324.1885856-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Lin He To more accurately determine whether the current HPD status matches the interrupt status, the polling mechanism in the lower half of the HPD interrupt (via hibmc_dp_check_hpd_status) has been replaced with directly retrieving the interrupt status in the upper half of the interrupt (via hibmc_dp_get_hpd_status). * Detection and training are not performed if hpd_status is not HPD_IN. * Set the initial status of hpd_status to HPD_OUT. Fixes: 3906e7a3b26d ("drm/hisilicon/hibmc: fix dp probabilistical detect er= rors after HPD irq") Signed-off-by: Lin He Signed-off-by: Yongbang Shi --- ChangeLog: v1 -> v2: - More states in HIBMC_DP_HPD_STATUS are added to the 'hibmc_dp_get_hpd_status'. --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h | 1 - drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 32 ++++++++++++------- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h | 4 ++- .../gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c | 29 ++++++++++------- .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 1 + 5 files changed, 43 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_comm.h index f53dac256ee0..b0e258b9265e 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h @@ -43,7 +43,6 @@ struct hibmc_dp_dev { u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; struct drm_dp_desc desc; bool is_branch; - int hpd_status; void __iomem *serdes_base; }; =20 diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index d5bd3c45649b..c9a113a1937d 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -191,6 +191,10 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG); /* clock enable */ writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL); + /* To latch the HPD interrupt, ensuring that DP can support more modes + * within the fbcon framework when connected alone. + */ + msleep(100); =20 return 0; } @@ -322,20 +326,26 @@ void hibmc_dp_set_cbar(struct hibmc_dp *dp, const str= uct hibmc_dp_cbar_cfg *cfg) writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL); } =20 -bool hibmc_dp_check_hpd_status(struct hibmc_dp *dp, int exp_status) +int hibmc_dp_get_hpd_status(struct hibmc_dp *dp) { + int ret =3D HIBMC_HPD_UNKNOWN; u32 status; - int ret; =20 - ret =3D readl_poll_timeout(dp->dp_dev->base + HIBMC_DP_HPD_STATUS, status, - FIELD_GET(HIBMC_DP_HPD_CUR_STATE, status) =3D=3D exp_status, - 1000, 100000); /* DP spec says 100ms */ - if (ret) { - drm_dbg_dp(dp->drm_dev, "wait hpd status timeout"); - return false; + status =3D FIELD_GET(HIBMC_DP_HPD_CUR_STATE, + readl(dp->dp_dev->base + HIBMC_DP_HPD_STATUS)); + switch (status) { + case 0: /* idle */ + case 3: /* unplug */ + case 4: /* unplug intermediate */ + ret =3D HIBMC_HPD_OUT; + break; + case 1: /* plug */ + case 2: /* plug intermediate */ + ret =3D HIBMC_HPD_IN; + break; + default: + break; } =20 - dp->dp_dev->hpd_status =3D exp_status; - - return true; + return ret; } diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.h index 0f3662d8737e..bcd4e9d155c8 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h @@ -15,6 +15,7 @@ struct hibmc_dp_dev; =20 enum hibmc_hpd_status { + HIBMC_HPD_UNKNOWN, HIBMC_HPD_OUT, HIBMC_HPD_IN, }; @@ -55,6 +56,7 @@ struct hibmc_dp { struct drm_dp_aux aux; struct hibmc_dp_cbar_cfg cfg; u32 irq_status; + int hpd_status; int phys_status; }; =20 @@ -66,7 +68,7 @@ void hibmc_dp_reset_link(struct hibmc_dp *dp); void hibmc_dp_hpd_cfg(struct hibmc_dp *dp); void hibmc_dp_enable_int(struct hibmc_dp *dp); void hibmc_dp_disable_int(struct hibmc_dp *dp); -bool hibmc_dp_check_hpd_status(struct hibmc_dp *dp, int exp_status); +int hibmc_dp_get_hpd_status(struct hibmc_dp *dp); u8 hibmc_dp_get_link_rate(struct hibmc_dp *dp); u8 hibmc_dp_get_lanes(struct hibmc_dp *dp); =20 diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c b/drivers/gpu/d= rm/hisilicon/hibmc/hibmc_drm_dp.c index 2e9403b8bf3c..23716d48149f 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c @@ -63,12 +63,8 @@ static int hibmc_dp_detect(struct drm_connector *connect= or, struct hibmc_dp_dev *dp_dev =3D dp->dp_dev; int ret =3D connector_status_disconnected; =20 - if (dp->irq_status) { - if (dp_dev->hpd_status !=3D HIBMC_HPD_IN) { - ret =3D connector_status_disconnected; - goto exit; - } - } + if (dp->hpd_status !=3D HIBMC_HPD_IN) + goto exit; =20 if (!hibmc_dp_get_dpcd(dp_dev)) { ret =3D connector_status_disconnected; @@ -166,6 +162,9 @@ static void hibmc_dp_encoder_enable(struct drm_encoder = *drm_encoder, struct hibmc_dp *dp =3D container_of(drm_encoder, struct hibmc_dp, encode= r); struct drm_display_mode *mode =3D &drm_encoder->crtc->state->mode; =20 + if (dp->hpd_status !=3D HIBMC_HPD_IN) + return; + if (hibmc_dp_prepare(dp, mode)) return; =20 @@ -189,24 +188,31 @@ irqreturn_t hibmc_dp_hpd_isr(int irq, void *arg) { struct drm_device *dev =3D (struct drm_device *)arg; struct hibmc_drm_private *priv =3D to_hibmc_drm_private(dev); - int idx, exp_status; + int status =3D priv->dp.hpd_status; + int idx; =20 if (!drm_dev_enter(dev, &idx)) return -ENODEV; =20 if (priv->dp.irq_status & DP_MASKED_SINK_HPD_PLUG_INT) { drm_dbg_dp(&priv->dev, "HPD IN isr occur!\n"); + if (status !=3D HIBMC_HPD_IN) { + drm_err(&priv->dev, "HPD status (%d) error", status); + goto exit; + } hibmc_dp_hpd_cfg(&priv->dp); - exp_status =3D HIBMC_HPD_IN; } else { drm_dbg_dp(&priv->dev, "HPD OUT isr occur!\n"); + if (status !=3D HIBMC_HPD_OUT) { + drm_err(&priv->dev, "HPD status (%d) error", status); + goto exit; + } hibmc_dp_reset_link(&priv->dp); - exp_status =3D HIBMC_HPD_OUT; } =20 - if (hibmc_dp_check_hpd_status(&priv->dp, exp_status)) - drm_connector_helper_hpd_irq_event(&priv->dp.connector); + drm_connector_helper_hpd_irq_event(&priv->dp.connector); =20 +exit: drm_dev_exit(idx); =20 return IRQ_HANDLED; @@ -223,6 +229,7 @@ int hibmc_dp_init(struct hibmc_drm_private *priv) =20 dp->mmio =3D priv->mmio; dp->drm_dev =3D dev; + dp->hpd_status =3D HIBMC_HPD_OUT; =20 ret =3D hibmc_dp_hw_init(&priv->dp); if (ret) { diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.c index 4d85c89f3f88..e5cca7b63b78 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -63,6 +63,7 @@ static irqreturn_t hibmc_dp_interrupt(int irq, void *arg) status =3D readl(priv->mmio + HIBMC_DP_INTSTAT); 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Tue, 21 Jul 2026 20:53:55 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH for drm-misc-fixes v2 2/2] drm/hisilicon/hibmc: Add a flag to indicate whether the OS-side driver has been loaded Date: Tue, 21 Jul 2026 20:43:24 +0800 Message-ID: <20260721124324.1885856-3-shiyongbang@huawei.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260721124324.1885856-1-shiyongbang@huawei.com> References: <20260721124324.1885856-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Lin He Add a flag to indicate whether the OS-side driver has been loaded to prevent the BMC from enabling DP if the driver is not loaded, which could lead to system failure in handling interrupts and generate error messages like: irq xx: nobody cared (try booting with the "irqpoll" option) ... Call Trace: ... Fixes: 0ab6ea261c1f ("drm/hisilicon/hibmc: add dp module in hibmc") Signed-off-by: Lin He Signed-off-by: Yongbang Shi --- ChangeLog: v1 -> v2: - The call to `hibmc_set_enable_flag()` has been moved before `drm_client_setup()`, specifically before the connector detection triggers the I2C bit operation. (sashiko-bot) - A read-modify-write operation has been implemented instead of directly writing to prevent clearing the I2C mask bits. (sashiko-bot) --- .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 21 +++++++++++++++++++ .../gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.c index e5cca7b63b78..53c02f8b8841 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -424,6 +424,24 @@ static int hibmc_load(struct drm_device *dev) return ret; } =20 +static inline void hibmc_set_enable_flag(struct hibmc_drm_private *priv) +{ + u32 value; + + value =3D readl(priv->mmio + HIBMC_ENABLE_FLAG); + value |=3D HIBMC_ENABLE_STATE; + writel(value, priv->mmio + HIBMC_ENABLE_FLAG); +} + +static inline void hibmc_set_disable_flag(struct hibmc_drm_private *priv) +{ + u32 value; + + value =3D readl(priv->mmio + HIBMC_ENABLE_FLAG); + value &=3D ~HIBMC_ENABLE_STATE; + writel(value, priv->mmio + HIBMC_ENABLE_FLAG); +} + static int hibmc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { @@ -466,6 +484,8 @@ static int hibmc_pci_probe(struct pci_dev *pdev, goto err_unload; } =20 + hibmc_set_enable_flag(priv); + drm_client_setup(dev, NULL); =20 return 0; @@ -480,6 +500,7 @@ static void hibmc_pci_remove(struct pci_dev *pdev) { struct drm_device *dev =3D pci_get_drvdata(pdev); =20 + hibmc_set_disable_flag(to_hibmc_drm_private(dev)); drm_dev_unregister(dev); hibmc_unload(dev); } diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h b/drivers/gpu= /drm/hisilicon/hibmc/hibmc_drm_regs.h index 17b30c393b10..b95add5b253c 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h @@ -200,5 +200,8 @@ =20 #define HIBMC_CRT_PALETTE 0x80C00 =20 +#define HIBMC_ENABLE_FLAG 0x802A4 +#define HIBMC_ENABLE_STATE BIT(2) + #define HIBMC_FIELD(field, value) (field(value) & field##_MASK) #endif --=20 2.43.0