From nobody Sat Jul 25 01:34:42 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40960430CF4; Tue, 21 Jul 2026 07:03:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784617419; cv=none; b=eYtxGwguEYSUud9wORa5pNrrMWZ2hZrmBiQ7WyQGCuC2UpMKBbcx9S1oEufQOhXxL18OlEsYWTj/PEv4ATsaSq6EeYFMHN8IVkLcd8o8e8Q2/K8Lr4fq2JLs7xL18xrQ7NMv7Agc39EUP4XZ6bUTZNGGEYD4CYlG0gdKbDlVwaw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784617419; c=relaxed/simple; bh=fZSLRntAQAsNigCKOb/JIqWmsCXowWJHNP/OxZpHdlo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M5zN4D85fv6ZTxOAxAeeOMVnml+OHhURUM2XGZjWcRKDXZMYWT+UzUNlPBwlW1Dup9CNs1vARHELxzYve1oinEPE8QJLEa0F8jb3KM/z+sTFfOljaGhqZ7S2heanSu5RC3dtB7F/jqc9vHqZD6Bkxr5hGR5ojlbUl9X6dDik1jQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Rk4/YOXh; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Rk4/YOXh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1784617416; x=1816153416; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fZSLRntAQAsNigCKOb/JIqWmsCXowWJHNP/OxZpHdlo=; b=Rk4/YOXhml/sMa1xP8rUM8SiSoHYFr0VWiGRySOIAzjbbqrbJLFnH/eX Boq+IS49LOLNdTSQQbKhotGIxFWWxu0WhSreq2cG/OoeXm03iohWjzpWo CSWxCP/lkfKy3JQWWHr85Pf0SAYHhQCexrIL9YMm29PL56ux0ruxv4ZNC enXXEwB262H1tAcHgVLo5JF/Bh6jfIUq38+fCKBvb3gbs86sj0HPQ8s63 +3QwtjKtng3Fs+HpGkXOetJfqArVyk2GL1uWZaA/kUVf7QVtmN9XFqoWw 1btJuyojg8aEznJTjdZd7qYKJCngdUPoo77wH0MFfX36OfJS4Uut4MwHB A==; X-CSE-ConnectionGUID: 4/5ekZZiRImVhZN4DJScqw== X-CSE-MsgGUID: Cj8jySmASCK+pJzi05R6kw== X-IronPort-AV: E=McAfee;i="6800,10657,11852"; a="96717615" X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="96717615" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2026 00:03:32 -0700 X-CSE-ConnectionGUID: A57DBL9PRN+LVssYH00t8w== X-CSE-MsgGUID: mPQjLjKJS6aIxP1GrvgUcw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="255036639" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.17]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2026 00:03:12 -0700 From: Adrian Hunter To: Peter Zijlstra Cc: Ingo Molnar , Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , Namhyung Kim , Ian Rogers , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: [PATCH 1/3] perf/x86/intel/pt: Factor out pt_config_enable() Date: Tue, 21 Jul 2026 10:02:52 +0300 Message-ID: <20260721070254.13557-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260721070254.13557-1-adrian.hunter@intel.com> References: <20260721070254.13557-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pt_config() enables tracing by allowing NMIs and pause/resume, issuing the necessary barriers, and calling pt_config_start(). A later change needs to re-enable tracing on a (re-)start path without repeating the full pt_config() setup (filters, RTIT_CTL, buffer configuration). Factor that enabling sequence out into a new helper, pt_config_enable(), so it can be called on its own. No functional change intended. Signed-off-by: Adrian Hunter --- arch/x86/events/intel/pt.c | 41 ++++++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index b5726b50e77d..dc1be7f6e04b 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -502,6 +502,29 @@ static u64 pt_config_filters(struct perf_event *event) return rtit_ctl; } =20 +static void pt_config_enable(struct perf_event *event) +{ + struct pt *pt =3D this_cpu_ptr(&pt_ctx); + + /* + * Allow resume before starting so as not to overwrite a value set by a + * PMI. + */ + barrier(); + WRITE_ONCE(pt->resume_allowed, 1); + /* Configuration is complete, it is now OK to handle an NMI */ + barrier(); + WRITE_ONCE(pt->handle_nmi, 1); + barrier(); + pt_config_start(event); + barrier(); + /* + * Allow pause after starting so its pt_config_stop() doesn't race with + * pt_config_start(). + */ + WRITE_ONCE(pt->pause_allowed, 1); +} + static void pt_config(struct perf_event *event) { struct pt *pt =3D this_cpu_ptr(&pt_ctx); @@ -541,23 +564,7 @@ static void pt_config(struct perf_event *event) =20 event->hw.aux_config =3D reg; =20 - /* - * Allow resume before starting so as not to overwrite a value set by a - * PMI. - */ - barrier(); - WRITE_ONCE(pt->resume_allowed, 1); - /* Configuration is complete, it is now OK to handle an NMI */ - barrier(); - WRITE_ONCE(pt->handle_nmi, 1); - barrier(); - pt_config_start(event); - barrier(); - /* - * Allow pause after starting so its pt_config_stop() doesn't race with - * pt_config_start(). - */ - WRITE_ONCE(pt->pause_allowed, 1); + pt_config_enable(event); } =20 static void pt_config_stop(struct perf_event *event) --=20 2.53.0 From nobody Sat Jul 25 01:34:42 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F75642FCBC; Tue, 21 Jul 2026 07:03:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" The Intel PT driver reads and writes event->hw.state as a whole value, assuming it is either 0 or PERF_HES_STOPPED. That is true today, but a subsequent fix needs to also track an open AUX output buffer using the PERF_HES_UPTODATE bit of the same field. When more than one bit can be set, whole-value assignments would overwrite the other bits and whole-value comparisons would fail to match. Convert all accesses to set, clear and test the PERF_HES_STOPPED bit individually, in preparation for that change. No functional change intended: event->hw.state currently only ever holds 0 or PERF_HES_STOPPED, so the bitwise forms are equivalent. Signed-off-by: Adrian Hunter --- arch/x86/events/intel/pt.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index dc1be7f6e04b..2163e5ccdc04 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -1540,12 +1540,12 @@ void intel_pt_interrupt(void) =20 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0)); =20 - if (!event->hw.state) { + if (!(event->hw.state & PERF_HES_STOPPED)) { int ret; =20 buf =3D perf_aux_output_begin(&pt->handle, event); if (!buf) { - event->hw.state =3D PERF_HES_STOPPED; + event->hw.state |=3D PERF_HES_STOPPED; WRITE_ONCE(pt->resume_allowed, 0); return; } @@ -1639,7 +1639,7 @@ static void pt_event_start(struct perf_event *event, = int mode) goto fail_end_stop; } =20 - hwc->state =3D 0; + hwc->state &=3D ~PERF_HES_STOPPED; =20 pt_config_buffer(buf); pt_config(event); @@ -1649,7 +1649,7 @@ static void pt_event_start(struct perf_event *event, = int mode) fail_end_stop: perf_aux_output_end(&pt->handle, 0); fail_stop: - hwc->state =3D PERF_HES_STOPPED; + hwc->state |=3D PERF_HES_STOPPED; } =20 static void pt_event_stop(struct perf_event *event, int mode) @@ -1680,10 +1680,10 @@ static void pt_event_stop(struct perf_event *event,= int mode) =20 pt_config_stop(event); =20 - if (event->hw.state =3D=3D PERF_HES_STOPPED) + if (event->hw.state & PERF_HES_STOPPED) return; =20 - event->hw.state =3D PERF_HES_STOPPED; + event->hw.state |=3D PERF_HES_STOPPED; =20 if (mode & PERF_EF_UPDATE) { struct pt_buffer *buf =3D perf_get_aux(&pt->handle); @@ -1778,10 +1778,10 @@ static int pt_event_add(struct perf_event *event, i= nt mode) if (mode & PERF_EF_START) { pt_event_start(event, 0); ret =3D -EINVAL; - if (hwc->state =3D=3D PERF_HES_STOPPED) + if (hwc->state & PERF_HES_STOPPED) goto fail; } else { - hwc->state =3D PERF_HES_STOPPED; + hwc->state |=3D PERF_HES_STOPPED; } =20 ret =3D 0; --=20 2.53.0 From nobody Sat Jul 25 01:34:42 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8E1C4307AD; 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a="96717627" X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="96717627" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2026 00:03:33 -0700 X-CSE-ConnectionGUID: qQXBBjgvSWS68FlDQ02cBA== X-CSE-MsgGUID: o2bw5LsCSNe5wQzHd+pkww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="255036648" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.245.17]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2026 00:03:21 -0700 From: Adrian Hunter To: Peter Zijlstra Cc: Ingo Molnar , Alexander Shishkin , Arnaldo Carvalho de Melo , Jiri Olsa , Namhyung Kim , Ian Rogers , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Subject: [PATCH 3/3] perf/x86/intel/pt: Fix stop/start with no update Date: Tue, 21 Jul 2026 10:02:54 +0300 Message-ID: <20260721070254.13557-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260721070254.13557-1-adrian.hunter@intel.com> References: <20260721070254.13557-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If pt_event_stop() is called without PERF_EF_UPDATE flag, then perf_aux_output_end() is not called. A subsequent call to pt_event_start() will call perf_aux_output_begin() again which violates the rule against nesting and triggers a WARNING in perf_aux_output_begin(). Originally, pt_event_stop() was never called without PERF_EF_UPDATE, because the only code paths to do so are from event overflow, and Intel PT does not do that. However the introduction of group throttling by commit 9734e25fbf5ae ("perf: Fix the throttle logic for a group") meant that an Intel PT event could be throttled if it was part of a group. Throttling calls PMU ->stop() / ->start() callbacks without flags. An example is when AUX area sampling is used. The following commands hit the issue: echo 10000 > /proc/sys/kernel/perf_event_max_sample_rate perf record -F32000 --aux-sample -e '{intel_pt//u,cycles:u}' \ -- bash -c 'for i in `seq 1 100000` ; do true ; done' Use PERF_HES_UPTODATE to track whether perf_aux_output_begin() and perf_aux_output_end() are balanced. A cleared PERF_HES_UPTODATE bit indicates that an AUX output context is still open. Amend pt_event_start() / pt_event_stop() accordingly so that begin/end stay balanced: - In non-snapshot mode, stop() always closes the buffer (the buffer may have run out of space, and that accounting is done by the update), so a following start() opens a fresh one as before. - In snapshot/overwrite mode, stop() without PERF_EF_UPDATE leaves the buffer open so that pt_event_snapshot_aux() can still copy from it, and start() then only re-enables tracing instead of calling perf_aux_output_begin() again. Note that pt_event_del() calls pt_event_stop() with PERF_EF_UPDATE flag set (as is required by the documentation), so a final call to perf_aux_output_end() is assured. Fixes: 52ca9ced3f707 ("perf/x86/intel/pt: Add Intel PT PMU driver") Signed-off-by: Adrian Hunter --- arch/x86/events/intel/pt.c | 45 ++++++++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c index 2163e5ccdc04..5754cd405562 100644 --- a/arch/x86/events/intel/pt.c +++ b/arch/x86/events/intel/pt.c @@ -1540,6 +1540,8 @@ void intel_pt_interrupt(void) =20 perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0)); =20 + event->hw.state |=3D PERF_HES_UPTODATE; + if (!(event->hw.state & PERF_HES_STOPPED)) { int ret; =20 @@ -1561,6 +1563,8 @@ void intel_pt_interrupt(void) =20 pt_config_buffer(buf); pt_config_start(event); + + event->hw.state &=3D ~PERF_HES_UPTODATE; } } =20 @@ -1629,6 +1633,18 @@ static void pt_event_start(struct perf_event *event,= int mode) return; } =20 + /* + * Re-start subsequent to a call to pt_event_stop() without the + * PERF_EF_UPDATE flag. Absence of PERF_HES_UPTODATE indicates that + * perf_aux_output_begin() has already been called. This path can + * come about only in snapshot/overwrite mode - see pt_event_stop(). + */ + if (!(hwc->state & PERF_HES_UPTODATE)) { + hwc->state &=3D ~PERF_HES_STOPPED; + pt_config_enable(event); + return; + } + buf =3D perf_aux_output_begin(&pt->handle, event); if (!buf) goto fail_stop; @@ -1639,7 +1655,7 @@ static void pt_event_start(struct perf_event *event, = int mode) goto fail_end_stop; } =20 - hwc->state &=3D ~PERF_HES_STOPPED; + hwc->state &=3D ~(PERF_HES_STOPPED | PERF_HES_UPTODATE); =20 pt_config_buffer(buf); pt_config(event); @@ -1649,12 +1665,13 @@ static void pt_event_start(struct perf_event *event= , int mode) fail_end_stop: perf_aux_output_end(&pt->handle, 0); fail_stop: - hwc->state |=3D PERF_HES_STOPPED; + hwc->state |=3D PERF_HES_STOPPED | PERF_HES_UPTODATE; } =20 static void pt_event_stop(struct perf_event *event, int mode) { struct pt *pt =3D this_cpu_ptr(&pt_ctx); + struct pt_buffer *buf; =20 if (mode & PERF_EF_PAUSE) { if (READ_ONCE(pt->pause_allowed)) @@ -1680,17 +1697,24 @@ static void pt_event_stop(struct perf_event *event,= int mode) =20 pt_config_stop(event); =20 - if (event->hw.state & PERF_HES_STOPPED) - return; - event->hw.state |=3D PERF_HES_STOPPED; =20 - if (mode & PERF_EF_UPDATE) { - struct pt_buffer *buf =3D perf_get_aux(&pt->handle); + if (event->hw.state & PERF_HES_UPTODATE) + return; =20 - if (!buf) - return; + buf =3D perf_get_aux(&pt->handle); + if (!buf) + return; =20 + /* + * When not in snapshot/overwrite mode, there is a possibility that the + * buffer has run out of space. The accounting for that is handled by + * the update, so always update in that case. Snapshot/overwrite mode is + * treated differently to allow for pt_event_snapshot_aux() which can + * still get called if the AUX-sampling event is not stopped until after + * PT is stopped. + */ + if ((mode & PERF_EF_UPDATE) || !buf->snapshot) { if (WARN_ON_ONCE(pt->handle.event !=3D event)) return; =20 @@ -1705,6 +1729,7 @@ static void pt_event_stop(struct perf_event *event, i= nt mode) local_xchg(&buf->data_size, buf->nr_pages << PAGE_SHIFT); perf_aux_output_end(&pt->handle, local_xchg(&buf->data_size, 0)); + event->hw.state |=3D PERF_HES_UPTODATE; } } =20 @@ -1775,6 +1800,8 @@ static int pt_event_add(struct perf_event *event, int= mode) if (pt->handle.event) goto fail; =20 + event->hw.state |=3D PERF_HES_UPTODATE; + if (mode & PERF_EF_START) { pt_event_start(event, 0); ret =3D -EINVAL; --=20 2.53.0