From nobody Sat Jul 25 01:35:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45DC23D812D; Tue, 21 Jul 2026 05:29:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784611774; cv=none; b=omqE9cOHR1fvw8LGYd+0J5jjDAC28LHQP/5duh/Uvku58qKQ8bqq9K/X8sswN2hzOa2JG2gzlF6sSAsUROfSqNOsYYFN++Ak7Un4bSr3dX2tggRLRbmMnZTMkDooWipSngfY/BcoIKidVSKiggFWo/3/RxGpX1lyJmeuZjY09NU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784611774; c=relaxed/simple; bh=2+B4vL0Lm/cbnMEOwb9Ux7Y4yhkEvIsIu+j+RbEs7Ic=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tDO+zydWO6vQ0XcWGM9RGm/7xh86B+ZTX6HIlGkO8Sy5gjXzzAIh/ecSzZfJDGRHutlxMJTyT+z0bnB6xHPO4hVLoeCO7qhIhdsP3dYhe0Wx81YFB74pVHjxveDF9v8NAkiSW0IUFR1Xz1uyKGsbwKMvAoA+1rCSyZTiBsEW3SM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=UMOEBSkb; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="UMOEBSkb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1784611773; x=1816147773; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2+B4vL0Lm/cbnMEOwb9Ux7Y4yhkEvIsIu+j+RbEs7Ic=; b=UMOEBSkbjlTcGpeDYK+Vjrzx4uWAZIaQJB+uIZwVIge7mf5oiVKjC/HZ XlEL1i2FRIx9PmXrOOwBzvKW1cI61BWEyTYwfwD6ppXrI4YC5SPw8D9wV UvMAQc1XEr2FUDbhYhkPApVMJrZ5FiDsDylThxqnznWNke6egt/6N7uYM jsaAhmc3RF9LXSLW+B0FByZVxEqpK8Oo5xLMNlQrBUhnZzc9RsyFpNPLV C2JpwS7wggYtLrliAGT47LYc7c1Q7qQAegHRZZBQJ04xceOaZtWKotpAJ OqhUj45hojjMAinxu5XhTQzsNxpri/R30qZREOw8D6sSwmG6qF6ofz1I0 g==; X-CSE-ConnectionGUID: 5DN3Cy/FTAazffb+4AroTg== X-CSE-MsgGUID: 2MbCVFiISQyHiHbPvqhbDg== X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="60925929" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2026 22:29:32 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Mon, 20 Jul 2026 22:29:31 -0700 Received: from che-ll-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 20 Jul 2026 22:29:23 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: Manikandan Muralidharan Subject: [PATCH v5 1/7] dt-bindings: mtd: jedec,spi-nor: allow the SFDP to be exposed via NVMEM Date: Tue, 21 Jul 2026 10:58:53 +0530 Message-ID: <20260721052859.171341-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260721052859.171341-1-manikandan.m@microchip.com> References: <20260721052859.171341-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add an optional "sfdp" child node (compatible "jedec,sfdp") that describes the SFDP as a read-only NVMEM provider via nvmem.yaml, so its contents (e.g. a vendor EUI-48/EUI-64) can be read through NVMEM cells. Signed-off-by: Manikandan Muralidharan Reviewed-by: Linus Walleij --- .../devicetree/bindings/mtd/jedec,spi-nor.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Doc= umentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 587af4968255..98fd954598ab 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -103,6 +103,20 @@ properties: spi-cpol: true spi-cpha: true =20 + sfdp: + $ref: /schemas/nvmem/nvmem.yaml# + unevaluatedProperties: false + description: + The Serial Flash Discoverable Parameters (SFDP) tables exposed as a + read-only NVMEM device. This allows standard or vendor-specific SFDP + data (for example a factory-programmed EUI-48/EUI-64 identifier) to = be + consumed through NVMEM cells. + properties: + compatible: + const: jedec,sfdp + required: + - compatible + dependencies: spi-cpol: [ spi-cpha ] spi-cpha: [ spi-cpol ] @@ -122,6 +136,10 @@ examples: spi-max-frequency =3D <40000000>; m25p,fast-read; reset-gpios =3D <&gpio 12 GPIO_ACTIVE_LOW>; + + sfdp { + compatible =3D "jedec,sfdp"; + }; }; }; ... --=20 2.43.0 From nobody Sat Jul 25 01:35:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D8FC3EB7FB; Tue, 21 Jul 2026 05:29:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784611786; cv=none; b=Fng5VvVwxJ2lNeV5E56QlPqXv4wgCBTxWOOk6PmBqGKM6fTKEczKteBCubd+aVRYTiODdJZHnMZ7rH+Qk2nHLeArFDc5zUimkN2B89NOXbReUh26q9umNrs+RiWL2WkgbDErZwHBq3+v2qzTITXb0QTGPolp7AjbMkUUfsf5+Zo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784611786; c=relaxed/simple; bh=ul2AN1PX1j52nJQ4/DQ2FY1Vi/Pv2UeQc6IZXxAKTuY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sOv5HdcZ3oOlPJK1QzPS/U6Lsom2r5H9z9nuN/u3yESZcdFKPOYRoz+eIxReLKfFlphk6krWlr12jK1zl2bbGSPu2KFRhbcBf0gV7f+LUEeNXq9Fts+NHq/5G397187ctFKY8fWlxCoL9zSh3QtV79l075blsvNdBXVGEMg2/1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=BRlpGFHF; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="BRlpGFHF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1784611788; x=1816147788; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ul2AN1PX1j52nJQ4/DQ2FY1Vi/Pv2UeQc6IZXxAKTuY=; b=BRlpGFHFW3WZlT7CtDneVG2JMcAxxgvByNpE6bfNXeZe88UfBca22LBO jWbe7N6T6l+FsDDa6QyVgBoKUPOUZAM+WLPcaIjYNEwRrb4enyeZxbLpk LVfNnuSmRTyfQ9z6DIUR8C/nNRUx4ie5qt5EL5Qg85jOClGswlspEMv7g 2973H0QeYrBJwIuaC2+RtLMGZucenWNCasLjnDCcGPm6r1u8iBorruy3X v1sc6xEQfxD60kNfdBIMZTJJDwrTHPZhJIEZuVBkwT9AfMHf3zKubr8V3 ArknN8yJFCBSGrfJvIdIciZcznOiMWMzDDfflHq0kaaPx9gj8PH/5MzWc A==; X-CSE-ConnectionGUID: 8/GfNbG4RQmG2SQoGKp6Fw== X-CSE-MsgGUID: BcCpRDj3SWCx9ic29KVnqA== X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="292305116" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Jul 2026 22:29:47 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 20 Jul 2026 22:29:43 -0700 Received: from che-ll-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 20 Jul 2026 22:29:35 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: Manikandan Muralidharan Subject: [PATCH v5 2/7] dt-bindings: nvmem: layouts: add Microchip/SST SFDP EUI layout Date: Tue, 21 Jul 2026 10:58:54 +0530 Message-ID: <20260721052859.171341-3-manikandan.m@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260721052859.171341-1-manikandan.m@microchip.com> References: <20260721052859.171341-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a binding for the NVMEM layout that exposes the factory-programmed EUI-48 identifier from the Microchip/SST vendor-specific SFDP parameter table (e.g. SST26VF064BEUI) as a "mac-address" NVMEM cell, and reference it from nvmem-layout.yaml. Signed-off-by: Manikandan Muralidharan Reviewed-by: Linus Walleij --- .../layouts/microchip,sst26vf-sfdp-eui.yaml | 60 +++++++++++++++++++ .../bindings/nvmem/layouts/nvmem-layout.yaml | 1 + 2 files changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/layouts/microch= ip,sst26vf-sfdp-eui.yaml diff --git a/Documentation/devicetree/bindings/nvmem/layouts/microchip,sst2= 6vf-sfdp-eui.yaml b/Documentation/devicetree/bindings/nvmem/layouts/microch= ip,sst26vf-sfdp-eui.yaml new file mode 100644 index 000000000000..37357efb7840 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/layouts/microchip,sst26vf-sfd= p-eui.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/layouts/microchip,sst26vf-sfdp-eu= i.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVMEM layout of the Microchip/SST SFDP EUI-48 identifier + +maintainers: + - Manikandan Muralidharan + +description: + Some Microchip/SST serial flashes (for example the SST26VF064BEUI) are + factory programmed with a globally unique EUI-48 identifier stored in a + vendor-specific SFDP parameter table and permanently write-protected. Th= is + layout locates that table and exposes the EUI-48 as an NVMEM cell so tha= t, + for example, a network driver can use it as a MAC address. The location = of + the data is discovered at runtime from the SFDP; no offset is encoded in= the + device tree. + +select: false + +properties: + compatible: + const: microchip,sst26vf-sfdp-eui + + mac-address: + type: object + description: + The factory-programmed EUI-48 identifier, usable as a MAC address. + additionalProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + + sfdp { + compatible =3D "jedec,sfdp"; + + nvmem-layout { + compatible =3D "microchip,sst26vf-sfdp-eui"; + + mac-address { + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/nvmem/layouts/nvmem-layout.y= aml b/Documentation/devicetree/bindings/nvmem/layouts/nvmem-layout.yaml index 382507060651..e63b93083821 100644 --- a/Documentation/devicetree/bindings/nvmem/layouts/nvmem-layout.yaml +++ b/Documentation/devicetree/bindings/nvmem/layouts/nvmem-layout.yaml @@ -20,6 +20,7 @@ description: | oneOf: - $ref: fixed-layout.yaml - $ref: kontron,sl28-vpd.yaml + - $ref: microchip,sst26vf-sfdp-eui.yaml - $ref: onie,tlv-layout.yaml - $ref: u-boot,env.yaml =20 --=20 2.43.0 From nobody Sat Jul 25 01:35:28 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7948A35F609; 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charset="utf-8" The SPI NOR core already reads the SFDP tables during enumeration and caches them in nor->sfdp->dwords (see spi_nor_parse_sfdp()). Re-expose that cached data as a read-only NVMEM device, in on-flash byte order, rooted at the flash's SFDP child node (compatible "jedec,sfdp"). This lets NVMEM cells reference any SFDP data: a fixed-layout for parameters at a known offset, or an nvmem-layout parser for vendor data whose location must be discovered at runtime.The device is only registered when an "sfdp" node is present in the device tree. Signed-off-by: Manikandan Muralidharan --- drivers/mtd/spi-nor/core.c | 8 ++++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/sfdp.c | 86 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index ccf4396cdcd0..b833d8ec2d65 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3204,6 +3204,14 @@ static int spi_nor_init_params(struct spi_nor *nor) spi_nor_init_params_deprecated(nor); } =20 + /* + * Expose the SFDP table as an NVMEM device only when + * the flash actually provides one + */ + ret =3D spi_nor_register_sfdp_nvmem(nor); + if (ret) + return ret; + ret =3D spi_nor_late_init_params(nor); if (ret) return ret; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index ba2d1a862c9d..0a6484298c5c 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -698,6 +698,7 @@ int spi_nor_controller_ops_write_reg(struct spi_nor *no= r, u8 opcode, =20 int spi_nor_check_sfdp_signature(struct spi_nor *nor); int spi_nor_parse_sfdp(struct spi_nor *nor); +int spi_nor_register_sfdp_nvmem(struct spi_nor *nor); =20 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) { diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 4600983cb579..704799fe92ae 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -6,6 +6,8 @@ =20 #include #include +#include +#include #include #include =20 @@ -1612,3 +1614,87 @@ int spi_nor_parse_sfdp(struct spi_nor *nor) kfree(param_headers); return err; } + +static int spi_nor_sfdp_reg_read(void *priv, unsigned int offset, + void *val, size_t bytes) +{ + struct spi_nor *nor =3D priv; + struct sfdp *sfdp =3D nor->sfdp; + size_t sfdp_size =3D sfdp->num_dwords * sizeof(*sfdp->dwords); + + if (offset >=3D sfdp_size || bytes > sfdp_size - offset) + return -EINVAL; + + /* The cached SFDP is kept in on-flash (little-endian) byte order. */ + memcpy(val, (u8 *)sfdp->dwords + offset, bytes); + + return 0; +} + +static void spi_nor_sfdp_nvmem_put_np(void *data) +{ + of_node_put(data); +} + +/** + * spi_nor_register_sfdp_nvmem() - expose the SFDP as a read-only NVMEM de= vice + * @nor: pointer to a 'struct spi_nor' + * + * Expose the whole SFDP, in on-flash byte order, as a read-only NVMEM dev= ice + * rooted at the flash's SFDP child node (compatible "jedec,sfdp"). This l= ets + * generic (fixed-layout) or vendor (nvmem-layout) cells reference any SFDP + * data. The device is only registered when a child node with the "jedec,s= fdp" + * compatible is described in the device tree. + * + * Return: 0 on success or if there is nothing to do, -errno otherwise. + */ +int spi_nor_register_sfdp_nvmem(struct spi_nor *nor) +{ + struct device *dev =3D nor->dev; + struct nvmem_config config =3D { }; + struct nvmem_device *nvmem; + struct device_node *np; + int ret; + + if (!nor->sfdp) + return 0; + + for_each_available_child_of_node(dev_of_node(dev), np) + if (of_device_is_compatible(np, "jedec,sfdp")) + break; + if (!np) + return 0; + + /* + * Register the put before devm_nvmem_register() so it runs last on + * detach, after the NVMEM device that uses the node is gone. + */ + ret =3D devm_add_action_or_reset(dev, spi_nor_sfdp_nvmem_put_np, np); + if (ret) + return ret; + + config.dev =3D dev; + config.of_node =3D np; + config.name =3D "sfdp"; + config.id =3D NVMEM_DEVID_AUTO; + config.owner =3D THIS_MODULE; + config.read_only =3D true; + config.word_size =3D 1; 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20 Jul 2026 22:30:10 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 20 Jul 2026 22:30:09 -0700 Received: from che-ll-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 20 Jul 2026 22:30:01 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: Manikandan Muralidharan Subject: [PATCH v5 4/7] nvmem: layouts: add Microchip/SST SFDP EUI layout driver Date: Tue, 21 Jul 2026 10:58:56 +0530 Message-ID: <20260721052859.171341-5-manikandan.m@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260721052859.171341-1-manikandan.m@microchip.com> References: <20260721052859.171341-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add an NVMEM layout that exposes the factory-programmed EUI-48 identifier from the Microchip/SST vendor SFDP parameter table (e.g. SST26VF064BEUI) as a "mac-address" cell, for use as a network MAC address. The vendor table is located at runtime via the SFDP NVMEM device (no offset in DT), and a read_post_process callback reverses the LSB-first bytes into canonical MAC order. Binds to an "nvmem-layout" node with compatible "microchip,sst26vf-sfdp-eui". Signed-off-by: Manikandan Muralidharan --- MAINTAINERS | 6 + drivers/nvmem/layouts/Kconfig | 10 ++ drivers/nvmem/layouts/Makefile | 1 + drivers/nvmem/layouts/sst26vf-sfdp-eui.c | 182 +++++++++++++++++++++++ 4 files changed, 199 insertions(+) create mode 100644 drivers/nvmem/layouts/sst26vf-sfdp-eui.c diff --git a/MAINTAINERS b/MAINTAINERS index 1ab8736850ea..9fac8c5203a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17815,6 +17815,12 @@ F: Documentation/devicetree/bindings/sound/atmel,a= t91-ssc.yaml F: drivers/misc/atmel-ssc.c F: include/linux/atmel-ssc.h =20 +MICROCHIP SST SFDP EUI NVMEM LAYOUT DRIVER +M: Manikandan Muralidharan +S: Maintained +F: Documentation/devicetree/bindings/nvmem/layouts/microchip,sst26vf-sfdp-= eui.yaml +F: drivers/nvmem/layouts/sst26vf-sfdp-eui.c + Microchip Timer Counter Block (TCB) Capture Driver M: Kamel Bouhara L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/drivers/nvmem/layouts/Kconfig b/drivers/nvmem/layouts/Kconfig index 5e586dfebe47..855c7db530da 100644 --- a/drivers/nvmem/layouts/Kconfig +++ b/drivers/nvmem/layouts/Kconfig @@ -26,6 +26,16 @@ config NVMEM_LAYOUT_ONIE_TLV =20 If unsure, say N. =20 +config NVMEM_LAYOUT_SST26VF_SFDP_EUI + tristate "Microchip/SST SFDP EUI-48 layout support" + help + Say Y here if you want to expose the factory-programmed EUI-48 + identifier stored in the Microchip/SST vendor-specific SFDP parameter + table (e.g. SST26VF064BEUI) as NVMEM cells, so that network drivers + can use them as a MAC address. + + If unsure, say N. + config NVMEM_LAYOUT_U_BOOT_ENV tristate "U-Boot environment variables layout" select CRC32 diff --git a/drivers/nvmem/layouts/Makefile b/drivers/nvmem/layouts/Makefile index 4940c9db0665..b99eac1f63f2 100644 --- a/drivers/nvmem/layouts/Makefile +++ b/drivers/nvmem/layouts/Makefile @@ -5,4 +5,5 @@ =20 obj-$(CONFIG_NVMEM_LAYOUT_SL28_VPD) +=3D sl28vpd.o obj-$(CONFIG_NVMEM_LAYOUT_ONIE_TLV) +=3D onie-tlv.o +obj-$(CONFIG_NVMEM_LAYOUT_SST26VF_SFDP_EUI) +=3D sst26vf-sfdp-eui.o obj-$(CONFIG_NVMEM_LAYOUT_U_BOOT_ENV) +=3D u-boot-env.o diff --git a/drivers/nvmem/layouts/sst26vf-sfdp-eui.c b/drivers/nvmem/layou= ts/sst26vf-sfdp-eui.c new file mode 100644 index 000000000000..641318d6f0af --- /dev/null +++ b/drivers/nvmem/layouts/sst26vf-sfdp-eui.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * NVMEM layout for the factory-programmed EUI-48 identifier stored in the + * Microchip/SST vendor-specific SFDP parameter table (e.g. SST26VF064BEUI= ). + * + * The whole SFDP is exposed as a read-only NVMEM device by the SPI NOR co= re. + * This layout locates the Microchip vendor parameter table at runtime and + * registers the EUI-48 address as an NVMEM cell, so that a network driver= can + * consume it as a MAC address. No offset is hardcoded in the device tree. + * + * Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries + * + * Author: Manikandan Muralidharan + */ + +#include +#include +#include +#include +#include +#include +#include + +/* SFDP header and parameter header, as laid out on the flash. */ +struct sfdp_header { + u8 signature[4]; + u8 minor; + u8 major; + u8 nph; + u8 unused; +}; + +struct sfdp_parameter_header { + u8 id_lsb; + u8 minor; + u8 major; + u8 length; + u8 parameter_table_pointer[3]; + u8 id_msb; +}; + +#define SFDP_SIGNATURE 0x50444653U + +#define SFDP_PARAM_HEADER_ID(h) (((h)->id_msb << 8) | (h)->id_lsb) +#define SFDP_PARAM_HEADER_PTP(h) get_unaligned_le24((h)->parameter_table_p= ointer) + +/* Microchip (vendor) parameter table identifier: id_msb << 8 | id_lsb. */ +#define SFDP_MCHP_VENDOR_ID 0x01bf + +#define SFDP_MCHP_EUI48_MARKER_OFFSET 0x60 +#define SFDP_MCHP_EUI48_MARKER 0x30 +#define SFDP_MCHP_EUI48_OFFSET 0x61 + +static int sfdp_eui_read_post_process(void *priv, const char *id, int inde= x, + unsigned int offset, void *buf, + size_t bytes) +{ + u8 *data =3D buf; + int i; + + /* SFDP stores the address least-significant octet first; reverse it. */ + for (i =3D 0; i < bytes / 2; i++) + swap(data[i], data[bytes - 1 - i]); + + if (bytes =3D=3D ETH_ALEN && !is_valid_ether_addr(buf)) + return -EINVAL; + + return 0; +} + +static int sfdp_eui_find_vendor_table(struct nvmem_device *nvmem, u32 *ptp) +{ + struct sfdp_parameter_header ph; + struct sfdp_header hdr; + int nph, i, ret; + + ret =3D nvmem_device_read(nvmem, 0, sizeof(hdr), &hdr); + if (ret < 0) + return ret; + + if (get_unaligned_le32(hdr.signature) !=3D SFDP_SIGNATURE) + return -EINVAL; + + /* The number of parameter headers (NPH) field is zero-based. */ + nph =3D hdr.nph; + + for (i =3D 0; i <=3D nph; i++) { + ret =3D nvmem_device_read(nvmem, sizeof(hdr) + i * sizeof(ph), + sizeof(ph), &ph); + if (ret < 0) + return ret; + + if (SFDP_PARAM_HEADER_ID(&ph) !=3D SFDP_MCHP_VENDOR_ID) + continue; + + *ptp =3D SFDP_PARAM_HEADER_PTP(&ph); + return 0; + } + + return -ENOENT; +} + +static int sfdp_eui_add_cells(struct nvmem_layout *layout) +{ + struct nvmem_device *nvmem =3D layout->nvmem; + struct device *dev =3D &layout->dev; + struct nvmem_cell_info info =3D { }; + struct device_node *layout_np; + u32 base =3D 0; + u8 marker; + int ret; + + ret =3D sfdp_eui_find_vendor_table(nvmem, &base); + if (ret =3D=3D -ENOENT) { + dev_dbg(dev, "no Microchip SFDP vendor table found\n"); + return 0; + } + if (ret) + return ret; + + /* The EUI-48 is present only if its marker byte is programmed. */ + ret =3D nvmem_device_read(nvmem, base + SFDP_MCHP_EUI48_MARKER_OFFSET, + 1, &marker); + if (ret < 0) + return ret; + if (marker !=3D SFDP_MCHP_EUI48_MARKER) { + dev_dbg(dev, "EUI-48 not programmed (marker 0x%02x)\n", marker); + return 0; + } + + layout_np =3D of_nvmem_layout_get_container(nvmem); + if (!layout_np) + return -ENOENT; + + info.name =3D "mac-address"; + info.offset =3D base + SFDP_MCHP_EUI48_OFFSET; + info.bytes =3D ETH_ALEN; + info.np =3D of_get_child_by_name(layout_np, "mac-address"); + info.read_post_process =3D sfdp_eui_read_post_process; + + ret =3D nvmem_add_one_cell(nvmem, &info); + if (ret) + of_node_put(info.np); + else + dev_dbg(dev, "exposed EUI-48 at SFDP offset 0x%x\n", info.offset); + + of_node_put(layout_np); + + return ret; +} + +static int sfdp_eui_probe(struct nvmem_layout *layout) +{ + layout->add_cells =3D sfdp_eui_add_cells; + + return nvmem_layout_register(layout); +} + +static void sfdp_eui_remove(struct nvmem_layout *layout) +{ + nvmem_layout_unregister(layout); +} + +static const struct of_device_id sfdp_eui_of_match_table[] =3D { + { .compatible =3D "microchip,sst26vf-sfdp-eui" }, + {} +}; +MODULE_DEVICE_TABLE(of, sfdp_eui_of_match_table); + +static struct nvmem_layout_driver sfdp_eui_layout =3D { + .driver =3D { + .name =3D "microchip-sst26vf-sfdp-eui-layout", + .of_match_table =3D sfdp_eui_of_match_table, + }, + .probe =3D sfdp_eui_probe, + .remove =3D sfdp_eui_remove, +}; +module_nvmem_layout_driver(sfdp_eui_layout); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Manikandan Muralidharan "); +MODULE_DESCRIPTION("NVMEM layout for the EUI-48 in the Microchip/SST SFDP = vendor table"); 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charset="utf-8" Move the QSPI flash partitions under a "partitions" node with the "fixed-partitions" compatible, as required by the current MTD partition binding, instead of declaring them as direct children of the flash node. No functional change. Signed-off-by: Manikandan Muralidharan Reviewed-by: Linus Walleij --- .../dts/microchip/at91-sama5d27_wlsom1.dtsi | 52 +++++++++++-------- 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi b/arch/a= rm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi index 0417f53b3e96..062aa02a98ed 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi @@ -240,34 +240,40 @@ qspi1_flash: flash@0 { m25p,fast-read; status =3D "disabled"; =20 - at91bootstrap@0 { - label =3D "at91bootstrap"; - reg =3D <0x0 0x40000>; - }; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + at91bootstrap@0 { + label =3D "at91bootstrap"; + reg =3D <0x0 0x40000>; + }; =20 - bootloader@40000 { - label =3D "bootloader"; - reg =3D <0x40000 0xc0000>; - }; + bootloader@40000 { + label =3D "bootloader"; + reg =3D <0x40000 0xc0000>; + }; =20 - bootloaderenvred@100000 { - label =3D "bootloader env redundant"; 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d="scan'208";a="60054923" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jul 2026 22:30:49 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Mon, 20 Jul 2026 22:30:48 -0700 Received: from che-ll-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 20 Jul 2026 22:30:40 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: Manikandan Muralidharan Subject: [PATCH v5 6/7] ARM: dts: microchip: sama5d27_wlsom1: read MAC address from QSPI SFDP Date: Tue, 21 Jul 2026 10:58:58 +0530 Message-ID: <20260721052859.171341-7-manikandan.m@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260721052859.171341-1-manikandan.m@microchip.com> References: <20260721052859.171341-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describe the QSPI flash SFDP as an NVMEM provider with the microchip,sst26vf-sfdp-eui layout, which exposes the factory-programmed EUI-48 as a "mac-address" cell, and point macb0 at it through nvmem-cells. This yields a stable MAC address on boards where U-Boot does not program one, instead of falling back to a random address. Signed-off-by: Manikandan Muralidharan Reviewed-by: Linus Walleij --- arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi | 11 +++++++++++ .../boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts | 2 ++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi b/arch/a= rm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi index 062aa02a98ed..6016d7f2a39c 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1.dtsi @@ -240,6 +240,17 @@ qspi1_flash: flash@0 { m25p,fast-read; status =3D "disabled"; =20 + sfdp { + compatible =3D "jedec,sfdp"; + + nvmem-layout { + compatible =3D "microchip,sst26vf-sfdp-eui"; + + mac_address_eui48: mac-address { + }; + }; + }; + partitions { compatible =3D "fixed-partitions"; #address-cells =3D <1>; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts b/arch= /arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts index 35a933eec573..5e87bf04bc47 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts @@ -97,6 +97,8 @@ uart6: serial@200 { =20 &macb0 { status =3D "okay"; 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Mon, 20 Jul 2026 22:30:53 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , CC: Manikandan Muralidharan Subject: [PATCH v5 7/7] ARM: configs: sama5: enable Microchip/SST SFDP EUI NVMEM layout Date: Tue, 21 Jul 2026 10:58:59 +0530 Message-ID: <20260721052859.171341-8-manikandan.m@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260721052859.171341-1-manikandan.m@microchip.com> References: <20260721052859.171341-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable CONFIG_NVMEM_LAYOUT_SST26VF_SFDP_EUI so the factory EUI-48 stored in the SST26VF QSPI flash SFDP can be used as a MAC address on boards such as the sama5d27_wlsom1. Signed-off-by: Manikandan Muralidharan Reviewed-by: Linus Walleij --- arch/arm/configs/sama5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defc= onfig index bd7f0b5f7d66..14dda4b0cfd0 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -220,6 +220,7 @@ CONFIG_PWM=3Dy CONFIG_PWM_ATMEL=3Dy CONFIG_PWM_ATMEL_HLCDC_PWM=3Dy CONFIG_PWM_ATMEL_TCB=3Dy +CONFIG_NVMEM_LAYOUT_SST26VF_SFDP_EUI=3Dy CONFIG_EXT4_FS=3Dy CONFIG_FANOTIFY=3Dy CONFIG_AUTOFS_FS=3Dm --=20 2.43.0