From nobody Sat Jul 25 00:47:26 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3587E342173; Tue, 21 Jul 2026 15:41:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784648497; cv=none; b=odBnKLh5K3qeluDBr83ERCe/OHgoT0mElofqjiiyXDB6Zqi25RyywWhG2iKGjjmY96WgXA6F1rhIEry9kw2cU0JK7H2Ww1/umokWmSDxQtBqArPyhxTm6C5I0razhgLHBfIy45GEkiwHsU7dlOZFzRXfB24+etrIK62GkrgjqDU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784648497; c=relaxed/simple; bh=T1fGJquZ1PQ3x9Puk6RACOZxVIFWT/srP2SCTPcbPAA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Y5y14Pl6pPqF//yPHR+Afzob8CiCC/h++i34JVcpGlFyTCYVmFCT2uca3ggWIkURl9NJkpgOhBqUR2S675sLQuqXdSMn9eXOZ8d7eVb1LtqOjJLqi0kzzh6FqzU/50KnLWn3GEPYk5rPvi5v35kHG72h89RdzgAvGRMfrj0NBJs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rf+Y4B9A; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rf+Y4B9A" Received: by smtp.kernel.org (Postfix) with ESMTPS id E5CD9C2BCF6; Tue, 21 Jul 2026 15:41:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784648497; bh=T1fGJquZ1PQ3x9Puk6RACOZxVIFWT/srP2SCTPcbPAA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=rf+Y4B9AvnYKrzG7WGv/h9SE6C4H8zF+DW4H/ZWU3zQ+8uDhhnw+r9BsAjS8DAwZe XW8S0E4YrJHzbpO+mCzGI5N5fX1N8mvq+CB4jckzfsVokqgqYo6VUau+pUHFnAT1Yk m0tHiAUe8Kec3yr6wrHEVR9qdx8ZiUqmaGe6Itbr2Lg0VF12GyAVMwIc8VDnnibW2O L5VtSmS3PlgzHMUJ4WU1BO7zw5V/ORq515GQCzQrGmtlvC7lvVFM1DztVPTn9iR2ya A57exQtSindmZiq8Ab7S8mkwxZgxDLLMshes9E5uCKypQmtQXU1ro8Ta2S2wlSISmW yIm/6qRBHS8XA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C43B1C44533; Tue, 21 Jul 2026 15:41:36 +0000 (UTC) From: Antonin Malzieu Ridolfi via B4 Relay Date: Tue, 21 Jul 2026 17:41:07 +0200 Subject: [PATCH 1/3] gpu: nova-core: Add function to query WPR2 range Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260721-nova-core-regs-split-v1-1-384fa2a42244@nanonej.com> References: <20260721-nova-core-regs-split-v1-0-384fa2a42244@nanonej.com> In-Reply-To: <20260721-nova-core-regs-split-v1-0-384fa2a42244@nanonej.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter Cc: nova-gpu@lists.linux.dev, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, daniel.almeida@collabora.com, Antonin Malzieu Ridolfi X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5155; i=dev@nanonej.com; h=from:subject:message-id; bh=VlhUb7uLUDcrDDc81OAAEbtjZcATBSKEOEjEUDRfBGo=; b=owEBbQKS/ZANAwAKAWaH8SMKFRX9AcsmYgBqX5MtR7OCSOaTB7f95uxZ5CMIwjTPCK7TGBH60 mjyQm1eFAaJAjMEAAEKAB0WIQSDtk+wfJEhL1KFIn1mh/EjChUV/QUCal+TLQAKCRBmh/EjChUV /W/iD/9jaSQEbjCMeg1Mx4sE5SFlECu638a1tBA6Zq/yFVBYaJS1GItxZT0QHsukoZMNONxYSrF qOPfWHkyhGFEVV8mSdvrXn463aOAvWZ0CbTyU6DoRqk1c5u3jroLIswpJdjj+obS51v0RPtc24q L9yPmKB6yQUEj9kmlHsGQra7l59luiFdR06/W9kFAwNOXNl3VR5A+dgiuBVPFSh8Al2zuI9642k He9OgHKRk9RPZOmxn4RYZa1dBx0qbSbhMbELLepVrmkBOSd4yzHwsEuHwpejgMu+Z/6vfZIMCBJ PXRRPlSXWmKVu+DOQgBh5vKg+/W0g73BB9DFBf8Io6ebpTnnl9z1jzC35LZEVea7nayAlL+D6DN b23dd71oz23NWaSeotE4J7phbFnqkr8vZRX170SkEvKrR0jfM6n2MB5FQHWQA4eKSlm5PZ3JiyZ ECbOmyq1dAd50R6FqdfJnx7he2HccyyJWeN+l1RDoH8XrIOTaQ2seZLVT9wmo5et+MZwJwMaxv/ i0GyG3y2eYRFLWo9/YpLYJfRrVczTzhzIXJa2aJCeFG3DGbtKpCpKn8/Ki7eRuVVzUoR3RUD7qX oM0SVo3I3Ig/baNzmH0jAtLjrcqie9TGj7H19xdJWPatt48QQGpe5LpQgvtBGytdVudyWXX/pwL wHbEhOQl7M6sGqg== X-Developer-Key: i=dev@nanonej.com; a=openpgp; fpr=83B64FB07C91212F5285227D6687F1230A1515FD X-Endpoint-Received: by B4 Relay for dev@nanonej.com/default with auth_id=825 X-Original-From: Antonin Malzieu Ridolfi Reply-To: dev@nanonej.com From: Antonin Malzieu Ridolfi Create new function abstracting WPR2 region range query. Refactor gsp hal tu102 to query the WPR2 region range using this new function. Suggested-by: Alexandre Courbot Signed-off-by: Antonin Malzieu Ridolfi Suggested-by: Danilo Krummrich --- drivers/gpu/nova-core/fb.rs | 15 +++++++++ drivers/gpu/nova-core/gsp/hal/tu102.rs | 58 +++++++++++++++---------------= ---- 2 files changed, 41 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 273cff752fae..864a34ca20b8 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -270,3 +270,18 @@ pub(crate) fn new(chipset: Chipset, bar: Bar0<'_>, gsp= _fw: &GspFirmware) -> Resu }) } } + +/// Reads the WPR2 memory region registers and returns the range if set. +/// Returns `None` if the WPR2 region is not set. +pub(crate) fn wpr2_range(bar: Bar0<'_>) -> Option> { + let (wpr2_lo, wpr2_hi) =3D ( + bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO), + bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI), + ); + + if !wpr2_hi.is_wpr2_set() { + return None; + } + + Some(wpr2_lo.lower_bound()..wpr2_hi.higher_bound()) +} diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core= /gsp/hal/tu102.rs index 29bb17171f56..b3242aaeea45 100644 --- a/drivers/gpu/nova-core/gsp/hal/tu102.rs +++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs @@ -17,7 +17,10 @@ sec2::Sec2, Falcon, // }, - fb::FbLayout, + fb::{ + wpr2_range, + FbLayout, // + }, firmware::{ booter::{ BooterFirmware, @@ -90,9 +93,8 @@ fn run(&self, ctx: &mut GspBootContext<'_, '_>) -> Result= { .inspect_err(|e| dev_err!(dev, "FWSEC-SB failed to run: {:?}\n= ", e)); =20 // Remove WPR2 region if set. - let wpr2_hi =3D bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); let booter_unloader_res =3D (|| { - if !wpr2_hi.is_wpr2_set() { + if wpr2_range(bar).is_none() { return Ok(()); } =20 @@ -110,8 +112,7 @@ fn run(&self, ctx: &mut GspBootContext<'_, '_>) -> Resu= lt { } =20 // Confirm that the WPR2 region has been removed. - let wpr2_hi =3D bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI); - if wpr2_hi.is_wpr2_set() { + if wpr2_range(bar).is_some() { dev_err!( dev, "WPR2 region still set after Booter Unloader returned\= n" @@ -144,9 +145,9 @@ fn run_fwsec_frts( bios: &Vbios, fb_layout: &FbLayout, ) -> Result { - // Check that the WPR2 region does not already exist - if it does,= we cannot run - // FWSEC-FRTS until the GPU is reset. - if bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound() !=3D= 0 { + // Check that the WPR2 region does not already exist - + // if it does, we cannot run FWSEC-FRTS until the GPU is reset. + if wpr2_range(bar).is_some() { dev_err!( dev, "WPR2 region already exists - GPU needs to be reset to pro= ceed\n" @@ -189,34 +190,27 @@ fn run_fwsec_frts( } =20 // Check that the WPR2 region has been created as we requested. - let (wpr2_lo, wpr2_hi) =3D ( - bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO).lower_bound(), - bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound(), - ); - - match (wpr2_lo, wpr2_hi) { - (_, 0) =3D> { - dev_err!(dev, "WPR2 region not created after running FWSEC= -FRTS\n"); + let Some(wpr2_range) =3D wpr2_range(bar) else { + dev_err!(dev, "WPR2 region not created after running FWSEC-FRT= S\n"); =20 - Err(EIO) - } - (wpr2_lo, _) if wpr2_lo !=3D fb_layout.frts.start =3D> { - dev_err!( - dev, - "WPR2 region created at unexpected address {:#x}; expe= cted {:#x}\n", - wpr2_lo, - fb_layout.frts.start, - ); + return Err(EIO); + }; =20 - Err(EIO) - } - (wpr2_lo, wpr2_hi) =3D> { - dev_dbg!(dev, "WPR2: {:#x}-{:#x}\n", wpr2_lo, wpr2_hi); - dev_dbg!(dev, "GPU instance built\n"); + if wpr2_range.start !=3D fb_layout.frts.start { + dev_err!( + dev, + "WPR2 region created at unexpected address {:#x}; expected= {:#x}\n", + wpr2_range.start, + fb_layout.frts.start, + ); =20 - Ok(()) - } + return Err(EIO); } + + dev_dbg!(dev, "WPR2: {:#x}-{:#x}\n", wpr2_range.start, wpr2_range.= end); + dev_dbg!(dev, "GPU instance built\n"); + + Ok(()) } =20 /// Load and prepare the resources required to properly reset the GSP = after it has been stopped. --=20 2.55.0 From nobody Sat Jul 25 00:47:26 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 357EB46AA9C; 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a=openpgp; fpr=83B64FB07C91212F5285227D6687F1230A1515FD X-Endpoint-Received: by B4 Relay for dev@nanonej.com/default with auth_id=825 X-Original-From: Antonin Malzieu Ridolfi Reply-To: dev@nanonej.com From: Antonin Malzieu Ridolfi Suggested-by: Alexandre Courbot Suggested-by: Danilo Krummrich Signed-off-by: Antonin Malzieu Ridolfi --- drivers/gpu/nova-core/fb.rs | 4 +- drivers/gpu/nova-core/fb/hal/ga100.rs | 8 ++- drivers/gpu/nova-core/fb/hal/gb100.rs | 6 +- drivers/gpu/nova-core/fb/hal/gb202.rs | 6 +- drivers/gpu/nova-core/fb/hal/gh100.rs | 6 +- drivers/gpu/nova-core/fb/hal/tu102.rs | 8 ++- drivers/gpu/nova-core/fb/regs.rs | 132 ++++++++++++++++++++++++++++++= +++- drivers/gpu/nova-core/regs.rs | 127 ------------------------------= -- 8 files changed, 155 insertions(+), 142 deletions(-) diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs index 864a34ca20b8..59e715b73479 100644 --- a/drivers/gpu/nova-core/fb.rs +++ b/drivers/gpu/nova-core/fb.rs @@ -275,8 +275,8 @@ pub(crate) fn new(chipset: Chipset, bar: Bar0<'_>, gsp_= fw: &GspFirmware) -> Resu /// Returns `None` if the WPR2 region is not set. pub(crate) fn wpr2_range(bar: Bar0<'_>) -> Option> { let (wpr2_lo, wpr2_hi) =3D ( - bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO), - bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI), + bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO), + bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI), ); =20 if !wpr2_hi.is_wpr2_set() { diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/= fb/hal/ga100.rs index 3cc1caf361c7..d13c9a826eef 100644 --- a/drivers/gpu/nova-core/fb/hal/ga100.rs +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs @@ -9,8 +9,10 @@ =20 use crate::{ driver::Bar0, - fb::hal::FbHal, - regs, // + fb::{ + hal::FbHal, + regs, // + }, }; =20 use super::tu102::FLUSH_SYSMEM_ADDR_SHIFT; @@ -41,7 +43,7 @@ pub(super) fn write_sysmem_flush_page_ga100(bar: Bar0<'_>= , addr: u64) { } =20 pub(super) fn display_enabled_ga100(bar: Bar0<'_>) -> bool { - !bar.read(regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY) + !bar.read(crate::regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY) .display_disabled() } =20 diff --git a/drivers/gpu/nova-core/fb/hal/gb100.rs b/drivers/gpu/nova-core/= fb/hal/gb100.rs index 6e0eba101ca1..ec55ec3fc7e1 100644 --- a/drivers/gpu/nova-core/fb/hal/gb100.rs +++ b/drivers/gpu/nova-core/fb/hal/gb100.rs @@ -22,9 +22,11 @@ =20 use crate::{ driver::Bar0, - fb::hal::FbHal, + fb::{ + hal::FbHal, + regs, // + }, num::usize_into_u32, - regs, // }; =20 struct Gb100; diff --git a/drivers/gpu/nova-core/fb/hal/gb202.rs b/drivers/gpu/nova-core/= fb/hal/gb202.rs index b78e0970f66d..69ba35d2ea08 100644 --- a/drivers/gpu/nova-core/fb/hal/gb202.rs +++ b/drivers/gpu/nova-core/fb/hal/gb202.rs @@ -12,8 +12,10 @@ =20 use crate::{ driver::Bar0, - fb::hal::FbHal, - regs, // + fb::{ + hal::FbHal, + regs, // + }, }; =20 struct Gb202; diff --git a/drivers/gpu/nova-core/fb/hal/gh100.rs b/drivers/gpu/nova-core/= fb/hal/gh100.rs index d39fe99537ed..2867ae058d0a 100644 --- a/drivers/gpu/nova-core/fb/hal/gh100.rs +++ b/drivers/gpu/nova-core/fb/hal/gh100.rs @@ -10,8 +10,10 @@ =20 use crate::{ driver::Bar0, - fb::hal::FbHal, - regs, // + fb::{ + hal::FbHal, + regs, // + }, }; =20 struct Gh100; diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/= fb/hal/tu102.rs index f629e8e9d5d5..2ef04ccb550c 100644 --- a/drivers/gpu/nova-core/fb/hal/tu102.rs +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs @@ -9,8 +9,10 @@ =20 use crate::{ driver::Bar0, - fb::hal::FbHal, - regs, // + fb::{ + hal::FbHal, // + regs, + }, }; =20 /// Shift applied to the sysmem address before it is written into `NV_PFB_= NISO_FLUSH_SYSMEM_ADDR`, @@ -31,7 +33,7 @@ pub(super) fn write_sysmem_flush_page_gm107(bar: Bar0<'_>= , addr: u64) -> Result } =20 pub(super) fn display_enabled_gm107(bar: Bar0<'_>) -> bool { - !bar.read(regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY) + !bar.read(crate::regs::gm107::NV_FUSE_STATUS_OPT_DISPLAY) .display_disabled() } =20 diff --git a/drivers/gpu/nova-core/fb/regs.rs b/drivers/gpu/nova-core/fb/re= gs.rs index b2ec02f584be..b2baa4a2a85f 100644 --- a/drivers/gpu/nova-core/fb/regs.rs +++ b/drivers/gpu/nova-core/fb/regs.rs @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 =20 -use kernel::io::register; +use kernel::{ + io::register, + sizes::SizeConstants, // +}; =20 // PDISP =20 @@ -23,3 +26,130 @@ pub(super) fn vga_workspace_addr(self) -> Option { } } } + +// PFB + +register! { + /// Low bits of the physical system memory address used by the GPU to = perform sysmembar + /// operations (see [`super::fb::SysmemFlush`]). + pub(super) NV_PFB_NISO_FLUSH_SYSMEM_ADDR(u32) @ 0x00100c10 { + 31:0 adr_39_08; + } + + /// High bits of the physical system memory address used by the GPU to= perform sysmembar + /// operations. + pub(super) NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00100c40 { + 23:0 adr_63_40; + } + + pub(super) NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE(u32) @ 0x00100ce0 { + 30:30 ecc_mode_enabled =3D> bool; + 9:4 lower_mag; + 3:0 lower_scale; + } + + pub(super) NV_PFB_PRI_MMU_WPR2_ADDR_LO(u32) @ 0x001fa824 { + /// Bits 12..40 of the lower (inclusive) bound of the WPR2 region. + 31:4 lo_val; + } + + pub(super) NV_PFB_PRI_MMU_WPR2_ADDR_HI(u32) @ 0x001fa828 { + /// Bits 12..40 of the higher (exclusive) bound of the WPR2 region. + 31:4 hi_val; + } +} + +/// Base of the GB10x HSHUB0 register window (`NV_HSHUB0_PRIV_BASE` in Ope= n RM). +/// +/// The base is provided by the GB10x framebuffer HAL. +pub(super) struct Hshub0Base(()); + +register! { + // GB10x sysmem flush registers, relative to the HSHUB0 base. GB10x ro= utes sysmembar + // through a primary and an EG (egress) pair that must both be program= med to the same + // address. Hardware ignores bits 7:0 of each LO register. The boot pa= th uses a fixed + // HSHUB0 base, so the multiple runtime-discovered HSHUB bases are not= needed here. + pub(super) NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ Hshub0Base + = 0x00000e50 { + 31:0 adr =3D> u32; + } + + pub(super) NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Hshub0Base + = 0x00000e54 { + 19:0 adr; + } + + pub(super) NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ Hshub0Base= + 0x000006c0 { + 31:0 adr =3D> u32; + } + + pub(super) NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Hshub0Base= + 0x000006c4 { + 19:0 adr; + } +} + +register! { + // GB20x FBHUB0 sysmem flush registers. Unlike the older + // NV_PFB_NISO_FLUSH_SYSMEM_ADDR registers, which encode the address w= ith an + // 8-bit right-shift, these take the raw address split into lower and = upper + // halves. Hardware ignores bits 7:0 of the LO register. + pub(super) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x008a1d58 { + 31:0 adr =3D> u32; + } + + pub(super) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x008a1d5c { + 19:0 adr; + } +} + +register! { + /// Low bits of the physical system memory address used by the GPU to = perform + /// sysmembar operations on Hopper. + /// + /// Like the GB20x FBHUB0 registers, and unlike the Ampere + /// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR` registers (which encode the addres= s with an + /// 8-bit right-shift), these take the raw address split into lower an= d upper + /// halves. Hardware ignores bits 7:0 of the LO register. + pub(super) NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x00100a34 { + 31:0 adr =3D> u32; + } + + /// High bits of the physical system memory address used by the GPU to= perform + /// sysmembar operations on Hopper. + pub(super) NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00100a38 { + 19:0 adr; + } +} + +impl NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE { + /// Returns the usable framebuffer size, in bytes. + pub(super) fn usable_fb_size(self) -> u64 { + let size =3D (u64::from(self.lower_mag()) << u64::from(self.lower_= scale())) * u64::SZ_1M; + + if self.ecc_mode_enabled() { + // Remove the amount of memory reserved for ECC (one per 16 un= its). + size / 16 * 15 + } else { + size + } + } +} + +impl NV_PFB_PRI_MMU_WPR2_ADDR_LO { + /// Returns the lower (inclusive) bound of the WPR2 region. + pub(super) fn lower_bound(self) -> u64 { + u64::from(self.lo_val()) << 12 + } +} + +impl NV_PFB_PRI_MMU_WPR2_ADDR_HI { + /// Returns the higher (exclusive) bound of the WPR2 region. + /// + /// A value of zero means the WPR2 region is not set. + pub(super) fn higher_bound(self) -> u64 { + u64::from(self.hi_val()) << 12 + } + + /// Returns whether the WPR2 region is currently set. + pub(super) fn is_wpr2_set(self) -> bool { + self.hi_val() !=3D 0 + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index 397124f245ee..f7304b27ae0c 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -116,133 +116,6 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> = kernel::fmt::Result { } } =20 -// PFB - -register! { - /// Low bits of the physical system memory address used by the GPU to = perform sysmembar - /// operations (see [`crate::fb::SysmemFlush`]). - pub(crate) NV_PFB_NISO_FLUSH_SYSMEM_ADDR(u32) @ 0x00100c10 { - 31:0 adr_39_08; - } - - /// High bits of the physical system memory address used by the GPU to= perform sysmembar - /// operations. - pub(crate) NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00100c40 { - 23:0 adr_63_40; - } - - pub(crate) NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE(u32) @ 0x00100ce0 { - 30:30 ecc_mode_enabled =3D> bool; - 9:4 lower_mag; - 3:0 lower_scale; - } - - pub(crate) NV_PFB_PRI_MMU_WPR2_ADDR_LO(u32) @ 0x001fa824 { - /// Bits 12..40 of the lower (inclusive) bound of the WPR2 region. - 31:4 lo_val; - } - - pub(crate) NV_PFB_PRI_MMU_WPR2_ADDR_HI(u32) @ 0x001fa828 { - /// Bits 12..40 of the higher (exclusive) bound of the WPR2 region. - 31:4 hi_val; - } -} - -/// Base of the GB10x HSHUB0 register window (`NV_HSHUB0_PRIV_BASE` in Ope= n RM). -/// -/// The base is provided by the GB10x framebuffer HAL. -pub(crate) struct Hshub0Base(()); - -register! { - // GB10x sysmem flush registers, relative to the HSHUB0 base. GB10x ro= utes sysmembar - // through a primary and an EG (egress) pair that must both be program= med to the same - // address. Hardware ignores bits 7:0 of each LO register. The boot pa= th uses a fixed - // HSHUB0 base, so the multiple runtime-discovered HSHUB bases are not= needed here. - pub(crate) NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ Hshub0Base + = 0x00000e50 { - 31:0 adr =3D> u32; - } - - pub(crate) NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Hshub0Base + = 0x00000e54 { - 19:0 adr; - } - - pub(crate) NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ Hshub0Base= + 0x000006c0 { - 31:0 adr =3D> u32; - } - - pub(crate) NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Hshub0Base= + 0x000006c4 { - 19:0 adr; - } -} - -register! { - // GB20x FBHUB0 sysmem flush registers. Unlike the older - // NV_PFB_NISO_FLUSH_SYSMEM_ADDR registers, which encode the address w= ith an - // 8-bit right-shift, these take the raw address split into lower and = upper - // halves. Hardware ignores bits 7:0 of the LO register. - pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x008a1d58 { - 31:0 adr =3D> u32; - } - - pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x008a1d5c { - 19:0 adr; - } -} - -register! { - /// Low bits of the physical system memory address used by the GPU to = perform - /// sysmembar operations on Hopper. - /// - /// Like the GB20x FBHUB0 registers, and unlike the Ampere - /// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR` registers (which encode the addres= s with an - /// 8-bit right-shift), these take the raw address split into lower an= d upper - /// halves. Hardware ignores bits 7:0 of the LO register. - pub(crate) NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x00100a34 { - 31:0 adr =3D> u32; - } - - /// High bits of the physical system memory address used by the GPU to= perform - /// sysmembar operations on Hopper. - pub(crate) NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00100a38 { - 19:0 adr; - } -} - -impl NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE { - /// Returns the usable framebuffer size, in bytes. - pub(crate) fn usable_fb_size(self) -> u64 { - let size =3D (u64::from(self.lower_mag()) << u64::from(self.lower_= scale())) * u64::SZ_1M; - - if self.ecc_mode_enabled() { - // Remove the amount of memory reserved for ECC (one per 16 un= its). - size / 16 * 15 - } else { - size - } - } -} - -impl NV_PFB_PRI_MMU_WPR2_ADDR_LO { - /// Returns the lower (inclusive) bound of the WPR2 region. - pub(crate) fn lower_bound(self) -> u64 { - u64::from(self.lo_val()) << 12 - } -} - -impl NV_PFB_PRI_MMU_WPR2_ADDR_HI { - /// Returns the higher (exclusive) bound of the WPR2 region. - /// - /// A value of zero means the WPR2 region is not set. - pub(crate) fn higher_bound(self) -> u64 { - u64::from(self.hi_val()) << 12 - } - - /// Returns whether the WPR2 region is currently set. - pub(crate) fn is_wpr2_set(self) -> bool { - self.hi_val() !=3D 0 - } -} - // PGC6 register space. // // `GC6` is a GPU low-power state where VRAM is in self-refresh and the GP= U is powered down (except --=20 2.55.0 From nobody Sat Jul 25 00:47:26 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D340372B5E; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260721-nova-core-regs-split-v1-3-384fa2a42244@nanonej.com> References: <20260721-nova-core-regs-split-v1-0-384fa2a42244@nanonej.com> In-Reply-To: <20260721-nova-core-regs-split-v1-0-384fa2a42244@nanonej.com> To: Danilo Krummrich , Alexandre Courbot , Alice Ryhl , David Airlie , Simona Vetter Cc: nova-gpu@lists.linux.dev, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, daniel.almeida@collabora.com, Antonin Malzieu Ridolfi X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2078; i=dev@nanonej.com; h=from:subject:message-id; bh=bO+SB+QdzWlFEnKzthXbRE6mmjHZMmu3RJMJ0HXXY+c=; b=owEBbQKS/ZANAwAKAWaH8SMKFRX9AcsmYgBqX5Mt4IxqTt5dVTWxHBWYyBEDhr7RLWoOGDk3h AuNZoGhPPqJAjMEAAEKAB0WIQSDtk+wfJEhL1KFIn1mh/EjChUV/QUCal+TLQAKCRBmh/EjChUV /bprD/9Mkj9a4c8Z0kei+Bm3WJHQ9mUI18uUqtuwOEDF7pOwqtbhcSK0S1PGpmah3//8SUjekR7 MGa3vJv9Ahg8g8joDzOy5R2RwZWYca7gD3N0Tvw4wqMjD07vO5/3VvLHraGoe/6YtZm+3d41QsO hH74Xc6TzQAfUWdN0nr0NG9JLO0MX64aT+v+0UVEMKEZET4VAU8R0VTqflC4WzGreDM8UfTNhWV +T1LzXato0K1zUxmKdsWTvz0WqKA/UbydXkTqKmRx70ZFPKTUyQWhLcyXumlQQC8/H+fXTcqS2l NeHe/ZrO8dYs/jKS1OPIUrBSynkvusfXOZ45bj4ib+2SuvlGvDvHECBp7vemtldwTqBImIvJ+Ml bPyDX7A9P/v8jPMHkv35ViQUimt4PaVCB+nTaK77n94+AxpuJa43v3x+S+xFj6t0ipnYQgEwVkP chsIkLSiVLihToVGkukrv8dNq+PxyHYCAz1shRFbIPvav8lW+mCqOiNMg8HqT0PcyykICVFLSkI WfTYwMYgS2c5w6bWG9iKhWYyxoKSixWHkd4wfSviTW92GsZy+xXGtx+akLIqGn8Pt6wIUXDLyQa fvoJt8Tq4hyiLjJYyiUVvbeIpifbpSXIelWlLW8qXbCkKBb4sulsbYMK+/0wzhwmGpqmC3RXvm9 VJBMD3eQD6M9ieg== X-Developer-Key: i=dev@nanonej.com; a=openpgp; fpr=83B64FB07C91212F5285227D6687F1230A1515FD X-Endpoint-Received: by B4 Relay for dev@nanonej.com/default with auth_id=825 X-Original-From: Antonin Malzieu Ridolfi Reply-To: dev@nanonej.com From: Antonin Malzieu Ridolfi Suggested-by: Alexandre Courbot Suggested-by: Danilo Krummrich Signed-off-by: Antonin Malzieu Ridolfi --- drivers/gpu/nova-core/gsp/hal/tu102.rs | 2 +- drivers/gpu/nova-core/gsp/regs.rs | 11 +++++++++++ drivers/gpu/nova-core/regs.rs | 5 ----- 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core= /gsp/hal/tu102.rs index b3242aaeea45..91b995c2ee57 100644 --- a/drivers/gpu/nova-core/gsp/hal/tu102.rs +++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs @@ -40,12 +40,12 @@ GspHal, UnloadBundle, // }, + regs, sequencer::GspSequencer, Gsp, GspBootContext, GspFwWprMeta, // }, - regs, vbios::Vbios, // }; =20 diff --git a/drivers/gpu/nova-core/gsp/regs.rs b/drivers/gpu/nova-core/gsp/= regs.rs index a76dea3c3ab0..9a48aa87e7fb 100644 --- a/drivers/gpu/nova-core/gsp/regs.rs +++ b/drivers/gpu/nova-core/gsp/regs.rs @@ -2,6 +2,8 @@ =20 use kernel::io::register; =20 +use crate::regs::NV_PBUS_SW_SCRATCH; + // PGSP =20 register! { @@ -9,3 +11,12 @@ 31:0 address; } } + +// PBUS + +register! { + /// Scratch register 0xe used as FRTS firmware error code. + pub(super) NV_PBUS_SW_SCRATCH_0E_FRTS_ERR(u32) =3D> NV_PBUS_SW_SCRATCH= [0xe] { + 31:16 frts_err_code; + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index f7304b27ae0c..dda3be837f62 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -109,11 +109,6 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> k= ernel::fmt::Result { =20 register! { pub(crate) NV_PBUS_SW_SCRATCH(u32)[64] @ 0x00001400 {} - - /// Scratch register 0xe used as FRTS firmware error code. - pub(crate) NV_PBUS_SW_SCRATCH_0E_FRTS_ERR(u32) =3D> NV_PBUS_SW_SCRATCH= [0xe] { - 31:16 frts_err_code; - } } =20 // PGC6 register space. --=20 2.55.0