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Representing them as clk_branch instances allows them to be gated, which is undesirable. Remove their clk_branch definitions and register their CBCRs as critical clocks instead so they remain enabled. This matches the handling of similar always-on clocks in other Qualcomm clock drivers. Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller = driver for Nord SoC") Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Reviewed-by: Alexandre Mergnat --- drivers/clk/qcom/gcc-nord.c | 37 +++++++------------------------------ 1 file changed, 7 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/gcc-nord.c b/drivers/clk/qcom/gcc-nord.c index 8a6e429f264022d55fc5e59b9ec46ae1124f9ad8..299c616be325156ccd457b7b6ef= 45afef364ad4e 100644 --- a/drivers/clk/qcom/gcc-nord.c +++ b/drivers/clk/qcom/gcc-nord.c @@ -1185,34 +1185,6 @@ static struct clk_branch gcc_pcie_d_slv_q2a_axi_clk = =3D { }, }; =20 -static struct clk_branch gcc_pcie_link_ahb_clk =3D { - .halt_reg =3D 0x52464, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x52464, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "gcc_pcie_link_ahb_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pcie_link_xo_clk =3D { - .halt_reg =3D 0x52468, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x52468, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x52468, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "gcc_pcie_link_xo_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_pcie_noc_async_bridge_clk =3D { .halt_reg =3D 0x52048, .halt_check =3D BRANCH_HALT_SKIP, @@ -1758,8 +1730,6 @@ static struct clk_regmap *gcc_nord_clocks[] =3D { [GCC_PCIE_D_PIPE_CLK_SRC] =3D &gcc_pcie_d_pipe_clk_src.clkr, [GCC_PCIE_D_SLV_AXI_CLK] =3D &gcc_pcie_d_slv_axi_clk.clkr, [GCC_PCIE_D_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_d_slv_q2a_axi_clk.clkr, - [GCC_PCIE_LINK_AHB_CLK] =3D &gcc_pcie_link_ahb_clk.clkr, - [GCC_PCIE_LINK_XO_CLK] =3D &gcc_pcie_link_xo_clk.clkr, [GCC_PCIE_NOC_ASYNC_BRIDGE_CLK] =3D &gcc_pcie_noc_async_bridge_clk.clkr, [GCC_PCIE_NOC_CNOC_SF_QX_CLK] =3D &gcc_pcie_noc_cnoc_sf_qx_clk.clkr, [GCC_PCIE_NOC_M_CFG_CLK] =3D &gcc_pcie_noc_m_cfg_clk.clkr, @@ -1850,9 +1820,16 @@ static const struct regmap_config gcc_nord_regmap_co= nfig =3D { .fast_io =3D true, }; =20 +static const u32 gcc_nord_critical_cbcrs[] =3D { + 0x52464, /* GCC_PCIE_LINK_AHB_CLK */ + 0x52468, /* GCC_PCIE_LINK_XO_CLK */ +}; + static const struct qcom_cc_driver_data gcc_nord_driver_data =3D { .dfs_rcgs =3D gcc_nord_dfs_clocks, .num_dfs_rcgs =3D ARRAY_SIZE(gcc_nord_dfs_clocks), + .clk_cbcrs =3D gcc_nord_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gcc_nord_critical_cbcrs), }; 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Tue, 21 Jul 2026 00:07:42 -0700 (PDT) X-Received: by 2002:a05:6a00:928a:b0:848:65f3:23c1 with SMTP id d2e1a72fcca58-84c2956f89bmr17945720b3a.69.1784617662518; Tue, 21 Jul 2026 00:07:42 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84c2adcc74csm7080833b3a.18.2026.07.21.00.07.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2026 00:07:42 -0700 (PDT) From: Taniya Das Date: Tue, 21 Jul 2026 12:37:17 +0530 Subject: [PATCH v2 2/6] clk: qcom: negcc-nord: keep GPU2 CFG clock enabled via critical CBCR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260721-nords_mm_v1-v2-2-17e5a445a512@oss.qualcomm.com> References: <20260721-nords_mm_v1-v2-0-17e5a445a512@oss.qualcomm.com> In-Reply-To: <20260721-nords_mm_v1-v2-0-17e5a445a512@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Shawn Guo , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA3MyBTYWx0ZWRfX45cK5yWhCaSr kkW/XS2bji6Jr2AJPounOrwkrLLQme8DZzVcRo8G45d4TJWk7AYoq1iPfiuo3BzY1uLiNfhEVBB Jzguo1sRve+kfGtPpINQYn4kVPngiEhFf12o/vG0YgcIwDFMNC6dfPkdt3iu6QwyXel6aV+NWPj 0YEhsN7RAZvcSZErL/T+pDGPuNQ0ouLQhMZr2W8O03ZoTaV7h8AQmO1YI0j1vv+H5n++7xzvM2D kk+gE88DJQdooNq+78EhDvTXEiNS6eY6NWq/eJlk6HDo/kSdH1z7W9H/JAoDRfJ+xhv2bT9B3n2 08pz3uvbCuUb/IHEz7bQEuhK8ut5cz+xwF0pABIjWvPtEVRL0jvLK0O9uz5QB7Y/JkMWYgJ+BDu +W6wKNustL5AvYo/0O3n4ITxjYiUNRc2Sjd3RyitK0E7bv52hPD0s+uUvPa68jt1oUeWGlF/KCH sz2UuU6amXiAGLXD5RA== X-Proofpoint-ORIG-GUID: cTLOG_2n_UNdcB2fap0fskH2gKCJ0JM5 X-Proofpoint-GUID: cTLOG_2n_UNdcB2fap0fskH2gKCJ0JM5 X-Authority-Analysis: v=2.4 cv=M5F97Sws c=1 sm=1 tr=0 ts=6a5f1abf cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=mEVXwad1GdBeBoogAroA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA3MyBTYWx0ZWRfX03DMTq9oB65A /ZOvPMKgCdFC2PtiWjdSrDW5etxB5/r63O5bzor+XDaDSBLdgdHpm9ELMJjIexvvdznQfC+tLjq p1w1X1JSG6DV7ERMBrykFmAW6y6pyKo= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 spamscore=0 bulkscore=0 impostorscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210073 The GPU2 CFG clock must remain enabled for correct operation and should not be exposed as a controllable clk_branch. Remove the clk_branch and mark its CBCR as critical instead to prevent unintended gating. This follows the same approach as 'nw_gcc_gpu_cfg_ahb_clk' and aligns with other always-on clocks in Qualcomm CC drivers. Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller = driver for Nord SoC") Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Reviewed-by: Alexandre Mergnat --- drivers/clk/qcom/negcc-nord.c | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/negcc-nord.c b/drivers/clk/qcom/negcc-nord.c index 2e653ef0fe0e304f09ed354d5578fdbed9151d20..bc4d478d5606ad7478431573f98= b62f6f9b7d9fb 100644 --- a/drivers/clk/qcom/negcc-nord.c +++ b/drivers/clk/qcom/negcc-nord.c @@ -952,21 +952,6 @@ static struct clk_branch ne_gcc_gp2_clk =3D { }, }; =20 -static struct clk_branch ne_gcc_gpu_2_cfg_clk =3D { - .halt_reg =3D 0x34004, - .halt_check =3D BRANCH_HALT_VOTED, - .hwcg_reg =3D 0x34004, - .hwcg_bit =3D 1, - .clkr =3D { - .enable_reg =3D 0x34004, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "ne_gcc_gpu_2_cfg_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch ne_gcc_gpu_2_gpll0_clk_src =3D { .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { @@ -1817,7 +1802,6 @@ static struct clk_regmap *ne_gcc_nord_clocks[] =3D { [NE_GCC_GPLL0] =3D &ne_gcc_gpll0.clkr, [NE_GCC_GPLL0_OUT_EVEN] =3D &ne_gcc_gpll0_out_even.clkr, [NE_GCC_GPLL2] =3D &ne_gcc_gpll2.clkr, - [NE_GCC_GPU_2_CFG_CLK] =3D &ne_gcc_gpu_2_cfg_clk.clkr, [NE_GCC_GPU_2_GPLL0_CLK_SRC] =3D &ne_gcc_gpu_2_gpll0_clk_src.clkr, [NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC] =3D &ne_gcc_gpu_2_gpll0_div_clk_src.clkr, [NE_GCC_GPU_2_HSCNOC_GFX_CLK] =3D &ne_gcc_gpu_2_hscnoc_gfx_clk.clkr, @@ -1946,10 +1930,16 @@ static void clk_nord_regs_configure(struct device *= dev, struct regmap *regmap) qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true); 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Tue, 21 Jul 2026 00:07:48 -0700 (PDT) X-Received: by 2002:a05:6a00:9295:b0:845:d286:1fa2 with SMTP id d2e1a72fcca58-84c2946eeddmr17836582b3a.49.1784617668348; Tue, 21 Jul 2026 00:07:48 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84c2adcc74csm7080833b3a.18.2026.07.21.00.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2026 00:07:48 -0700 (PDT) From: Taniya Das Date: Tue, 21 Jul 2026 12:37:18 +0530 Subject: [PATCH v2 3/6] dt-bindings: clock: qcom: Document Nord display clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260721-nords_mm_v1-v2-3-17e5a445a512@oss.qualcomm.com> References: <20260721-nords_mm_v1-v2-0-17e5a445a512@oss.qualcomm.com> In-Reply-To: <20260721-nords_mm_v1-v2-0-17e5a445a512@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Shawn Guo , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-GUID: CiMB29zu2q75_gXzHzm2trNy7GoweyOS X-Proofpoint-ORIG-GUID: CiMB29zu2q75_gXzHzm2trNy7GoweyOS X-Authority-Analysis: v=2.4 cv=e+U2j6p/ c=1 sm=1 tr=0 ts=6a5f1ac5 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=EEkIxoOJKZrbPHcHuzUA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA3MyBTYWx0ZWRfX6k8jT5bTUgso D63IxvbitkmF3MZorRRV9bRkvEfG1L1u05onvIiApaTvZAl/AcO0cKdeLwo7rmj2pjYqcGYci/3 NisFDVDLon+NGvKZqW4FeXq1FHoTmes= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA3MyBTYWx0ZWRfX3ECoqOru1wkP fGE3ssTRrTCUDBFjXI+7/heqoWe1rOK8DVkxGLBfPhjwv6W0H4NVDmv87enx7UaZVlzAFsapq50 B6QkqOnp/v065u1/GsNhAHzsi4mR6PnFJRqJC2E2P9pznF61n9Va2YG8EFR6KKosK38BOFrKnH2 nNkPq1s4xnzYCbyuIfGC9tC5RBRe07PZRI7yEcxqbvVabcl1KbNq6tGRjQX3hX67wUk80Bcl1Cu PNXvgvTM1goVgY38UiILBi2BgFi2RqDsrpHY1+DY4Mw4+L/jpz8wGrI1JBOnLDCuaAravr5W2F0 o3Oqf+ZRqEhmiO8rMZVSjzfNEM/LKsH1STWxjSEsuYzRAlwcfOP7dYF3y4b2wkahoW8RCRy5+ev JWPKoQlS8vc9DjiglBapVQCE5O5ADoVdv6IiyxJm3kWFeKiocfHOjBYUUxawu3Iwob/28nmeQTt uK/dNIDl1OYGjzzherg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210073 Add Device Tree binding documentation for the display clock controller on the Qualcomm Nord SoC. The Nord platform contains two instances of the display clock controller, DISPCC_0 and DISPCC_1. Update the bindings to include compatible strings for both instances. Signed-off-by: Taniya Das Reviewed-by: Alexandre Mergnat Reviewed-by: Krzysztof Kozlowski Reviewed-by: Shawn Guo --- .../bindings/clock/qcom,sm8550-dispcc.yaml | 3 + include/dt-bindings/clock/qcom,nord-dispcc.h | 115 +++++++++++++++++= ++++ 2 files changed, 118 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yam= l b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml index 591ce91b8d54dd6f78a66d029882bcd94b53beda..61f58fbd5bd21c7f36081e7ae06= 6176fd19a5811 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -16,6 +16,7 @@ description: | =20 See also: - include/dt-bindings/clock/qcom,kaanapali-dispcc.h + - include/dt-bindings/clock/qcom,nord-dispcc.h - include/dt-bindings/clock/qcom,sm8550-dispcc.h - include/dt-bindings/clock/qcom,sm8650-dispcc.h - include/dt-bindings/clock/qcom,sm8750-dispcc.h @@ -25,6 +26,8 @@ properties: compatible: enum: - qcom,kaanapali-dispcc + - qcom,nord-dispcc0 + - qcom,nord-dispcc1 - qcom,sar2130p-dispcc - qcom,sm8550-dispcc - qcom,sm8650-dispcc diff --git a/include/dt-bindings/clock/qcom,nord-dispcc.h b/include/dt-bind= ings/clock/qcom,nord-dispcc.h new file mode 100644 index 0000000000000000000000000000000000000000..219facbbda106488d3f00391c9e= 14cb584fd12ff --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-dispcc.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_NORD_H + +/* DISP_CC_0 and DISP_CC_1 clocks */ +#define MDSS_DISP_CC_ACMU_CLK 0 +#define MDSS_DISP_CC_MDSS_ACCU_SHIFT_CLK 1 +#define MDSS_DISP_CC_MDSS_AHB1_CLK 2 +#define MDSS_DISP_CC_MDSS_AHB_CLK 3 +#define MDSS_DISP_CC_MDSS_AHB_CLK_SRC 4 +#define MDSS_DISP_CC_MDSS_BYTE0_CLK 5 +#define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC 6 +#define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 7 +#define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK 8 +#define MDSS_DISP_CC_MDSS_BYTE1_CLK 9 +#define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC 10 +#define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 11 +#define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK 12 +#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK 13 +#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 14 +#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK 15 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK 16 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 17 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 18 +#define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 19 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK 20 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 21 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK 22 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 23 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK 24 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC 25 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK 26 +#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC 27 +#define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 28 +#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK 29 +#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 30 +#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK 31 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK 32 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 33 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 34 +#define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 35 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK 36 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 37 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK 38 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 39 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK 40 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK_SRC 41 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK 42 +#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK_SRC 43 +#define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 44 +#define MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK 45 +#define MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 46 +#define MDSS_DISP_CC_MDSS_DPTX2_CRYPTO_CLK 47 +#define MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK 48 +#define MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 49 +#define MDSS_DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 50 +#define MDSS_DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 51 +#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK 52 +#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 53 +#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK 54 +#define MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 55 +#define MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK 56 +#define MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 57 +#define MDSS_DISP_CC_MDSS_DPTX3_CRYPTO_CLK 58 +#define MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK 59 +#define MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 60 +#define MDSS_DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 61 +#define MDSS_DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 62 +#define MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK 63 +#define MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 64 +#define MDSS_DISP_CC_MDSS_ESC0_CLK 65 +#define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC 66 +#define MDSS_DISP_CC_MDSS_ESC1_CLK 67 +#define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC 68 +#define MDSS_DISP_CC_MDSS_MDP1_CLK 69 +#define MDSS_DISP_CC_MDSS_MDP_CLK 70 +#define MDSS_DISP_CC_MDSS_MDP_CLK_SRC 71 +#define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK 72 +#define MDSS_DISP_CC_MDSS_MDP_LUT_CLK 73 +#define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK 74 +#define MDSS_DISP_CC_MDSS_PCLK0_CLK 75 +#define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC 76 +#define MDSS_DISP_CC_MDSS_PCLK1_CLK 77 +#define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC 78 +#define MDSS_DISP_CC_MDSS_PCLK2_CLK 79 +#define MDSS_DISP_CC_MDSS_PCLK2_CLK_SRC 80 +#define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK 81 +#define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK 82 +#define MDSS_DISP_CC_MDSS_VSYNC1_CLK 83 +#define MDSS_DISP_CC_MDSS_VSYNC_CLK 84 +#define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC 85 +#define MDSS_DISP_CC_PLL0 86 +#define MDSS_DISP_CC_PLL1 87 +#define MDSS_DISP_CC_PLL2 88 +#define MDSS_DISP_CC_PLL3 89 +#define MDSS_DISP_CC_SLEEP_CLK 90 +#define MDSS_DISP_CC_SLEEP_CLK_SRC 91 +#define MDSS_DISP_CC_SM_DIV_CLK_SRC 92 +#define MDSS_DISP_CC_XO_CLK 93 +#define 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<20260721-nords_mm_v1-v2-0-17e5a445a512@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Shawn Guo , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=BL6DalQG c=1 sm=1 tr=0 ts=6a5f1ace cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=N9uIJh8cW-Q2sVI0eSAA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA3MyBTYWx0ZWRfX/LRO+RopJdI/ 6huWQQHuTfIejW2kJWkehhdZv4AO97IvDk0mOm8XDXl2s2bDvbsZh7E7F0RT/uppTolO8TZJ1/d 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adultscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210073 Add support for the display clock controllers (DISPCC) on the Qualcomm Nord platform. The platform includes two display clock controller instances, display0 and display1. Register support for both controllers. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Reviewed-by: Shawn Guo --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/dispcc0-nord.c | 2004 +++++++++++++++++++++++++++++++++++= ++++ drivers/clk/qcom/dispcc1-nord.c | 2004 +++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 4020 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 7d84c2f1d911a35430bba7670409f59972dcca0f..874136a2ad9aaa117df2c7ad5c8= abc5280b76339 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -145,6 +145,17 @@ config CLK_KAANAPALI_VIDEOCC Say Y if you want to support video devices and functionality such as video encode/decode. =20 +config CLK_NORD_DISPCC + tristate "Nord Display Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_NORD_GCC + default m if ARCH_QCOM + help + Support for the display clock controllers on Qualcomm Technologies, Inc + Nord devices. There are two display clock controllers on Nord SoC. + Say Y if you want to support display devices and functionality such as + splash screen. + config CLK_NORD_GCC tristate "Nord Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 58f9a5eb6fd7fc457607a179d8bab5623fedf706..4282f43e7078f1fe0dde6f94204= 0eb6bd122d7ce 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) +=3D gcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GPUCC) +=3D gpucc-kaanapali.o gxclkctl-kaanapal= i.o obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o +obj-$(CONFIG_CLK_NORD_DISPCC) +=3D dispcc0-nord.o dispcc1-nord.o obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o diff --git a/drivers/clk/qcom/dispcc0-nord.c b/drivers/clk/qcom/dispcc0-nor= d.c new file mode 100644 index 0000000000000000000000000000000000000000..6d9c74ffe9a130ec934eb998228= 779af7bb3309a --- /dev/null +++ b/drivers/clk/qcom/dispcc0-nord.c @@ -0,0 +1,2004 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_AHB_CLK, + DT_SLEEP_CLK, + + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI1_PHY_PLL_OUT_BYTECLK, + DT_DSI1_PHY_PLL_OUT_DSICLK, + + DT_DP0_PHY_PLL_LINK_CLK, + DT_DP0_PHY_PLL_VCO_DIV_CLK, + DT_DP1_PHY_PLL_LINK_CLK, + DT_DP1_PHY_PLL_VCO_DIV_CLK, + DT_DP2_PHY_PLL_LINK_CLK, + DT_DP2_PHY_PLL_VCO_DIV_CLK, + DT_DP3_PHY_PLL_LINK_CLK, + DT_DP3_PHY_PLL_VCO_DIV_CLK, +}; + +enum { + P_BI_TCXO, + P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, + P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, + P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, + P_MDSS_0_DISP_CC_PLL2_OUT_MAIN, + P_MDSS_0_DISP_CC_PLL3_OUT_MAIN, + P_DP0_PHY_PLL_LINK_CLK, + P_DP0_PHY_PLL_VCO_DIV_CLK, + P_DP1_PHY_PLL_LINK_CLK, + P_DP1_PHY_PLL_VCO_DIV_CLK, + P_DP2_PHY_PLL_LINK_CLK, + P_DP2_PHY_PLL_VCO_DIV_CLK, + P_DP3_PHY_PLL_LINK_CLK, + P_DP3_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_BYTECLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +static const struct pll_vco zonda_ole_vco[] =3D { + { 700000000, 3600000000, 0 }, +}; + +/* 900.0 MHz Configuration */ +static const struct alpha_pll_config mdss_0_disp_cc_pll0_config =3D { + .l =3D 0x2e, + .alpha =3D 0xe000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll mdss_0_disp_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &mdss_0_disp_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 600.0 MHz Configuration */ +static const struct alpha_pll_config mdss_0_disp_cc_pll1_config =3D { + .l =3D 0x1f, + .alpha =3D 0x4000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll mdss_0_disp_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &mdss_0_disp_cc_pll1_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1363.2 MHz Configuration */ +static const struct alpha_pll_config mdss_0_disp_cc_pll2_config =3D { + .l =3D 0x47, + .alpha =3D 0x0, + .config_ctl_val =3D 0x08240800, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x00000000, + .config_ctl_hi2_val =3D 0x00000000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000080, +}; + +static struct clk_alpha_pll mdss_0_disp_cc_pll2 =3D { + .offset =3D 0x2000, + .config =3D &mdss_0_disp_cc_pll2_config, + .vco_table =3D zonda_ole_vco, + .num_vco =3D ARRAY_SIZE(zonda_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_pll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_zonda_ole_ops, + }, + }, +}; + +/* 1363.2 MHz Configuration */ +static const struct alpha_pll_config mdss_0_disp_cc_pll3_config =3D { + .l =3D 0x47, + .alpha =3D 0x0, + .config_ctl_val =3D 0x08240800, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x00000000, + .config_ctl_hi2_val =3D 0x00000000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000080, +}; + +static struct clk_alpha_pll mdss_0_disp_cc_pll3 =3D { + .offset =3D 0x3000, + .config =3D &mdss_0_disp_cc_pll3_config, + .vco_table =3D zonda_ole_vco, + .num_vco =3D ARRAY_SIZE(zonda_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_pll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_zonda_ole_ops, + }, + }, +}; + +static const struct parent_map disp_cc_0_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_MDSS_0_DISP_CC_PLL2_OUT_MAIN, 1 }, + { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, + { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, + { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, + { P_MDSS_0_DISP_CC_PLL3_OUT_MAIN, 5 }, + { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &mdss_0_disp_cc_pll2.clkr.hw }, + { .index =3D DT_DP0_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DP3_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DP1_PHY_PLL_VCO_DIV_CLK }, + { .hw =3D &mdss_0_disp_cc_pll3.clkr.hw }, + { .index =3D DT_DP2_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_0_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map disp_cc_0_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_0_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_MDSS_0_DISP_CC_PLL2_OUT_MAIN, 1 }, + { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, + { P_MDSS_0_DISP_CC_PLL3_OUT_MAIN, 5 }, + { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &mdss_0_disp_cc_pll2.clkr.hw }, + { .index =3D DT_DP3_PHY_PLL_VCO_DIV_CLK }, + { .hw =3D &mdss_0_disp_cc_pll3.clkr.hw }, + { .index =3D DT_DP2_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_0_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_DP0_PHY_PLL_LINK_CLK, 1 }, + { P_DP1_PHY_PLL_LINK_CLK, 2 }, + { P_DP2_PHY_PLL_LINK_CLK, 3 }, + { P_DP3_PHY_PLL_LINK_CLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP0_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP1_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP2_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP3_PHY_PLL_LINK_CLK }, +}; + +static const struct parent_map disp_cc_0_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_DP2_PHY_PLL_LINK_CLK, 3 }, + { P_DP3_PHY_PLL_LINK_CLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP2_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP3_PHY_PLL_LINK_CLK }, +}; + +static const struct parent_map disp_cc_0_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_0_parent_map_7[] =3D { + { P_BI_TCXO, 0 }, + { P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 4 }, + { P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_7[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &mdss_0_disp_cc_pll1.clkr.hw }, + { .hw =3D &mdss_0_disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_0_parent_map_8[] =3D { + { P_BI_TCXO, 0 }, + { P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 4 }, + { P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_8[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &mdss_0_disp_cc_pll0.clkr.hw }, + { .hw =3D &mdss_0_disp_cc_pll1.clkr.hw }, + { .hw =3D &mdss_0_disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_0_parent_map_9[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data disp_cc_0_parent_data_9[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_ahb_clk_src[] =3D { + F(37500000, P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), + F(75000000, P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x837c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_7, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_ahb_clk_src", + .parent_data =3D disp_cc_0_parent_data_7, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_7), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_byte0_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_byte0_clk_src =3D { + .cmd_rcgr =3D 0x813c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_2, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte0_clk_src", + .parent_data =3D disp_cc_0_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_byte1_clk_src =3D { + .cmd_rcgr =3D 0x8158, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_2, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte1_clk_src", + .parent_data =3D disp_cc_0_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_aux_clk_src =3D { + .cmd_rcgr =3D 0x8220, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_1, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_aux_clk_src", + .parent_data =3D disp_cc_0_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_link_clk_src =3D { + .cmd_rcgr =3D 0x81a4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_4, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_link_clk_src", + .parent_data =3D disp_cc_0_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x81c0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x81d8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src =3D { + .cmd_rcgr =3D 0x81f0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src =3D { + .cmd_rcgr =3D 0x8208, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_aux_clk_src =3D { + .cmd_rcgr =3D 0x82b4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_1, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_aux_clk_src", + .parent_data =3D disp_cc_0_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_link_clk_src =3D { + .cmd_rcgr =3D 0x8298, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_4, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_link_clk_src", + .parent_data =3D disp_cc_0_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x8238, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x8250, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel2_clk_src =3D { + .cmd_rcgr =3D 0x8268, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_pixel2_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx1_pixel3_clk_src =3D { + .cmd_rcgr =3D 0x8280, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_0, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_pixel3_clk_src", + .parent_data =3D disp_cc_0_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx2_aux_clk_src =3D { + .cmd_rcgr =3D 0x8318, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_1, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx2_aux_clk_src", + .parent_data =3D disp_cc_0_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx2_link_clk_src =3D { + .cmd_rcgr =3D 0x82cc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_5, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx2_link_clk_src", + .parent_data =3D disp_cc_0_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx2_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x82e8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_3, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx2_pixel0_clk_src", + .parent_data =3D disp_cc_0_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx2_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x8300, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_3, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx2_pixel1_clk_src", + .parent_data =3D disp_cc_0_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx3_aux_clk_src =3D { + .cmd_rcgr =3D 0x8364, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_1, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx3_aux_clk_src", + .parent_data =3D disp_cc_0_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx3_link_clk_src =3D { + .cmd_rcgr =3D 0x8348, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_5, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx3_link_clk_src", + .parent_data =3D disp_cc_0_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_dptx3_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x8330, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_3, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx3_pixel0_clk_src", + .parent_data =3D disp_cc_0_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_esc0_clk_src =3D { + .cmd_rcgr =3D 0x8174, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_6, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_esc0_clk_src", + .parent_data =3D disp_cc_0_parent_data_6, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_esc1_clk_src =3D { + .cmd_rcgr =3D 0x818c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_6, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_esc1_clk_src", + .parent_data =3D disp_cc_0_parent_data_6, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_mdss_0_disp_cc_mdss_mdp_clk_src[] =3D { + F(300000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(417000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(532000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(650000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(710000000, P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_mdp_clk_src =3D { + .cmd_rcgr =3D 0x810c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_8, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_mdp_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_mdp_clk_src", + .parent_data =3D disp_cc_0_parent_data_8, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_8), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_pclk0_clk_src =3D { + .cmd_rcgr =3D 0x80c4, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_2, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_pclk0_clk_src", + .parent_data =3D disp_cc_0_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_pclk1_clk_src =3D { + .cmd_rcgr =3D 0x80dc, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_2, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_pclk1_clk_src", + .parent_data =3D disp_cc_0_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_pclk2_clk_src =3D { + .cmd_rcgr =3D 0x80f4, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_2, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_pclk2_clk_src", + .parent_data =3D disp_cc_0_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_mdss_vsync_clk_src =3D { + .cmd_rcgr =3D 0x8124, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_1, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_vsync_clk_src", + .parent_data =3D disp_cc_0_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_mdss_0_disp_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_0_disp_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0xe064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_9, + .freq_tbl =3D ftbl_mdss_0_disp_cc_sleep_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_sleep_clk_src", + .parent_data =3D disp_cc_0_parent_data_9, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_9), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 mdss_0_disp_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0xe044, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_0_parent_map_1, + .freq_tbl =3D ftbl_mdss_0_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_xo_clk_src", + .parent_data =3D disp_cc_0_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_0_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div mdss_0_disp_cc_mdss_byte0_div_clk_src =3D { + .reg =3D 0x8154, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div mdss_0_disp_cc_mdss_byte1_div_clk_src =3D { + .reg =3D 0x8170, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte1_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx0_link_div_clk_src = =3D { + .reg =3D 0x81bc, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx1_link_div_clk_src = =3D { + .reg =3D 0x82b0, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx2_link_div_clk_src = =3D { + .reg =3D 0x82e4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx2_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx2_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div mdss_0_disp_cc_mdss_dptx3_link_div_clk_src = =3D { + .reg =3D 0x8360, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx3_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx3_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_accu_shift_clk =3D { + .halt_reg =3D 0xe060, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xe060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_ahb1_clk =3D { + .halt_reg =3D 0xa028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_ahb1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_ahb_clk =3D { + .halt_reg =3D 0x80c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_byte0_clk =3D { + .halt_reg =3D 0x8034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_byte0_intf_clk =3D { + .halt_reg =3D 0x8038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte0_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_byte1_clk =3D { + .halt_reg =3D 0x803c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x803c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_byte1_intf_clk =3D { + .halt_reg =3D 0x8040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_byte1_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_byte1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_aux_clk =3D { + .halt_reg =3D 0x806c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x806c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_crypto_clk =3D { + .halt_reg =3D 0x8058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_link_clk =3D { + .halt_reg =3D 0x804c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x804c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_link_intf_clk =3D { + .halt_reg =3D 0x8054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel0_clk =3D { + .halt_reg =3D 0x805c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x805c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel1_clk =3D { + .halt_reg =3D 0x8060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel2_clk =3D { + .halt_reg =3D 0x8064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_pixel2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_pixel3_clk =3D { + .halt_reg =3D 0x8068, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_pixel3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_pixel3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_cl= k =3D { + .halt_reg =3D 0x8050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_aux_clk =3D { + .halt_reg =3D 0x8090, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_crypto_clk =3D { + .halt_reg =3D 0x808c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x808c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_link_clk =3D { + .halt_reg =3D 0x8080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_link_intf_clk =3D { + .halt_reg =3D 0x8088, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel0_clk =3D { + .halt_reg =3D 0x8070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel1_clk =3D { + .halt_reg =3D 0x8074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel2_clk =3D { + .halt_reg =3D 0x8078, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8078, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_pixel2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_pixel2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_pixel3_clk =3D { + .halt_reg =3D 0x807c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x807c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_pixel3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_pixel3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_cl= k =3D { + .halt_reg =3D 0x8084, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx2_aux_clk =3D { + .halt_reg =3D 0x80a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx2_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx2_crypto_clk =3D { + .halt_reg =3D 0x80a4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x80a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx2_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx2_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx2_link_clk =3D { + .halt_reg =3D 0x809c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x809c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx2_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx2_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx2_link_intf_clk =3D { + .halt_reg =3D 0x80a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx2_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx2_pixel0_clk =3D { + .halt_reg =3D 0x8094, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8094, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx2_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx2_pixel1_clk =3D { + .halt_reg =3D 0x8098, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8098, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx2_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx3_aux_clk =3D { + .halt_reg =3D 0x80b8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx3_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx3_crypto_clk =3D { + .halt_reg =3D 0x80bc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x80bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx3_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx3_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx3_link_clk =3D { + .halt_reg =3D 0x80b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx3_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx3_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx3_link_intf_clk =3D { + .halt_reg =3D 0x80b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx3_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_dptx3_pixel0_clk =3D { + .halt_reg =3D 0x80ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_dptx3_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_esc0_clk =3D { + .halt_reg =3D 0x8044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_esc0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_esc1_clk =3D { + .halt_reg =3D 0x8048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_esc1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_esc1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_mdp1_clk =3D { + .halt_reg =3D 0xa004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_mdp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_mdp_clk =3D { + .halt_reg =3D 0x8010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_mdp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_mdp_lut1_clk =3D { + .halt_reg =3D 0xa014, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xa014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_mdp_lut1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_mdp_lut_clk =3D { + .halt_reg =3D 0x8020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_mdp_lut_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_non_gdsc_ahb_clk =3D { + .halt_reg =3D 0xc004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xc004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_pclk0_clk =3D { + .halt_reg =3D 0x8004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_pclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_pclk1_clk =3D { + .halt_reg =3D 0x8008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_pclk1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_pclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_pclk2_clk =3D { + .halt_reg =3D 0x800c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x800c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_pclk2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_pclk2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_vsync1_clk =3D { + .halt_reg =3D 0xa024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_vsync1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_0_disp_cc_mdss_vsync_clk =3D { + .halt_reg =3D 0x8030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_0_disp_cc_mdss_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_0_disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_0_disp_cc_mdss_core_gdsc =3D { + .gdscr =3D 0x9000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "mdss_0_disp_cc_mdss_core_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc mdss_0_disp_cc_mdss_core_int2_gdsc =3D { + .gdscr =3D 0xb000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "mdss_0_disp_cc_mdss_core_int2_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *disp_cc_0_nord_clocks[] =3D { + [MDSS_DISP_CC_MDSS_ACCU_SHIFT_CLK] =3D &mdss_0_disp_cc_mdss_accu_shift_cl= k.clkr, + [MDSS_DISP_CC_MDSS_AHB1_CLK] =3D &mdss_0_disp_cc_mdss_ahb1_clk.clkr, + [MDSS_DISP_CC_MDSS_AHB_CLK] =3D &mdss_0_disp_cc_mdss_ahb_clk.clkr, + [MDSS_DISP_CC_MDSS_AHB_CLK_SRC] =3D &mdss_0_disp_cc_mdss_ahb_clk_src.clkr, + [MDSS_DISP_CC_MDSS_BYTE0_CLK] =3D &mdss_0_disp_cc_mdss_byte0_clk.clkr, + [MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC] =3D &mdss_0_disp_cc_mdss_byte0_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =3D &mdss_0_disp_cc_mdss_byte0_div_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK] =3D &mdss_0_disp_cc_mdss_byte0_intf_cl= k.clkr, + [MDSS_DISP_CC_MDSS_BYTE1_CLK] =3D &mdss_0_disp_cc_mdss_byte1_clk.clkr, + [MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC] =3D &mdss_0_disp_cc_mdss_byte1_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =3D &mdss_0_disp_cc_mdss_byte1_div_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK] =3D &mdss_0_disp_cc_mdss_byte1_intf_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_aux_clk.= clkr, + [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_aux_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_crypt= o_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_link_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_lin= k_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] =3D + &mdss_0_disp_cc_mdss_dptx0_link_div_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_li= nk_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_pixel= 0_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_p= ixel0_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_pixel= 1_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_p= ixel1_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_pixel= 2_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_p= ixel2_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK] =3D &mdss_0_disp_cc_mdss_dptx0_pixel= 3_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx0_p= ixel3_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =3D + &mdss_0_disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_aux_clk.= clkr, + [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx1_aux_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_crypt= o_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_link_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx1_lin= k_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] =3D + &mdss_0_disp_cc_mdss_dptx1_link_div_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_li= nk_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_pixel= 0_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx1_p= ixel0_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_pixel= 1_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx1_p= ixel1_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_pixel= 2_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx1_p= ixel2_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK] =3D &mdss_0_disp_cc_mdss_dptx1_pixel= 3_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx1_p= ixel3_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =3D + &mdss_0_disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK] =3D &mdss_0_disp_cc_mdss_dptx2_aux_clk.= clkr, + [MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx2_aux_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_CRYPTO_CLK] =3D &mdss_0_disp_cc_mdss_dptx2_crypt= o_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK] =3D &mdss_0_disp_cc_mdss_dptx2_link_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx2_lin= k_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] =3D + &mdss_0_disp_cc_mdss_dptx2_link_div_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] =3D &mdss_0_disp_cc_mdss_dptx2_li= nk_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK] =3D &mdss_0_disp_cc_mdss_dptx2_pixel= 0_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx2_p= ixel0_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK] =3D &mdss_0_disp_cc_mdss_dptx2_pixel= 1_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx2_p= ixel1_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK] =3D &mdss_0_disp_cc_mdss_dptx3_aux_clk.= clkr, + [MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx3_aux_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_CRYPTO_CLK] =3D &mdss_0_disp_cc_mdss_dptx3_crypt= o_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK] =3D &mdss_0_disp_cc_mdss_dptx3_link_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx3_lin= k_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] =3D + &mdss_0_disp_cc_mdss_dptx3_link_div_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] =3D &mdss_0_disp_cc_mdss_dptx3_li= nk_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK] =3D &mdss_0_disp_cc_mdss_dptx3_pixel= 0_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] =3D &mdss_0_disp_cc_mdss_dptx3_p= ixel0_clk_src.clkr, + [MDSS_DISP_CC_MDSS_ESC0_CLK] =3D &mdss_0_disp_cc_mdss_esc0_clk.clkr, + [MDSS_DISP_CC_MDSS_ESC0_CLK_SRC] =3D &mdss_0_disp_cc_mdss_esc0_clk_src.cl= kr, + [MDSS_DISP_CC_MDSS_ESC1_CLK] =3D &mdss_0_disp_cc_mdss_esc1_clk.clkr, + [MDSS_DISP_CC_MDSS_ESC1_CLK_SRC] =3D &mdss_0_disp_cc_mdss_esc1_clk_src.cl= kr, + [MDSS_DISP_CC_MDSS_MDP1_CLK] =3D &mdss_0_disp_cc_mdss_mdp1_clk.clkr, + [MDSS_DISP_CC_MDSS_MDP_CLK] =3D &mdss_0_disp_cc_mdss_mdp_clk.clkr, + [MDSS_DISP_CC_MDSS_MDP_CLK_SRC] =3D &mdss_0_disp_cc_mdss_mdp_clk_src.clkr, + [MDSS_DISP_CC_MDSS_MDP_LUT1_CLK] =3D &mdss_0_disp_cc_mdss_mdp_lut1_clk.cl= kr, + [MDSS_DISP_CC_MDSS_MDP_LUT_CLK] =3D &mdss_0_disp_cc_mdss_mdp_lut_clk.clkr, + [MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK] =3D &mdss_0_disp_cc_mdss_non_gdsc_ah= b_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK0_CLK] =3D &mdss_0_disp_cc_mdss_pclk0_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC] =3D &mdss_0_disp_cc_mdss_pclk0_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_PCLK1_CLK] =3D &mdss_0_disp_cc_mdss_pclk1_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC] =3D &mdss_0_disp_cc_mdss_pclk1_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_PCLK2_CLK] =3D &mdss_0_disp_cc_mdss_pclk2_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK2_CLK_SRC] =3D &mdss_0_disp_cc_mdss_pclk2_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_VSYNC1_CLK] =3D &mdss_0_disp_cc_mdss_vsync1_clk.clkr, + [MDSS_DISP_CC_MDSS_VSYNC_CLK] =3D &mdss_0_disp_cc_mdss_vsync_clk.clkr, + [MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC] =3D &mdss_0_disp_cc_mdss_vsync_clk_src.= clkr, + [MDSS_DISP_CC_PLL0] =3D &mdss_0_disp_cc_pll0.clkr, + [MDSS_DISP_CC_PLL1] =3D &mdss_0_disp_cc_pll1.clkr, + [MDSS_DISP_CC_PLL2] =3D &mdss_0_disp_cc_pll2.clkr, + [MDSS_DISP_CC_PLL3] =3D &mdss_0_disp_cc_pll3.clkr, + [MDSS_DISP_CC_SLEEP_CLK_SRC] =3D &mdss_0_disp_cc_sleep_clk_src.clkr, + [MDSS_DISP_CC_XO_CLK_SRC] =3D &mdss_0_disp_cc_xo_clk_src.clkr, +}; + +static struct gdsc *disp_cc_0_nord_gdscs[] =3D { + [MDSS_DISP_CC_MDSS_CORE_GDSC] =3D &mdss_0_disp_cc_mdss_core_gdsc, + [MDSS_DISP_CC_MDSS_CORE_INT2_GDSC] =3D &mdss_0_disp_cc_mdss_core_int2_gds= c, +}; + +static const struct qcom_reset_map disp_cc_0_nord_resets[] =3D { + [MDSS_DISP_CC_MDSS_CORE_BCR] =3D { 0x8000 }, + [MDSS_DISP_CC_MDSS_CORE_INT2_BCR] =3D { 0xa000 }, + [MDSS_DISP_CC_MDSS_RSCC_BCR] =3D { 0xc000 }, +}; + +static struct clk_alpha_pll *disp_cc_0_nord_plls[] =3D { + &mdss_0_disp_cc_pll0, + &mdss_0_disp_cc_pll1, + &mdss_0_disp_cc_pll2, + &mdss_0_disp_cc_pll3, +}; + +static const u32 disp_cc_0_nord_critical_cbcrs[] =3D { + 0xc00c, /* MDSS_DISP_CC_AHB_CLK */ + 0xc008, /* MDSS_DISP_CC_VSYNC_CLK */ + 0xe07c, /* MDSS_DISP_CC_SLEEP_CLK */ + 0xe05c, /* MDSS_DISP_CC_XO_CLK */ +}; + +static const struct regmap_config disp_cc_0_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1a00c, + .fast_io =3D true, +}; + +static const struct qcom_cc_driver_data disp_cc_0_nord_driver_data =3D { + .alpha_plls =3D disp_cc_0_nord_plls, + .num_alpha_plls =3D ARRAY_SIZE(disp_cc_0_nord_plls), + .clk_cbcrs =3D disp_cc_0_nord_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(disp_cc_0_nord_critical_cbcrs), +}; + +static const struct qcom_cc_desc disp_cc_0_nord_desc =3D { + .config =3D &disp_cc_0_nord_regmap_config, + .clks =3D disp_cc_0_nord_clocks, + .num_clks =3D ARRAY_SIZE(disp_cc_0_nord_clocks), + .resets =3D disp_cc_0_nord_resets, + .num_resets =3D ARRAY_SIZE(disp_cc_0_nord_resets), + .gdscs =3D disp_cc_0_nord_gdscs, + .num_gdscs =3D ARRAY_SIZE(disp_cc_0_nord_gdscs), + .use_rpm =3D true, + .driver_data =3D &disp_cc_0_nord_driver_data, +}; + +static const struct of_device_id disp_cc_0_nord_match_table[] =3D { + { .compatible =3D "qcom,nord-dispcc0" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_0_nord_match_table); + +static int disp_cc_0_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &disp_cc_0_nord_desc); +} + +static struct platform_driver disp_cc_0_nord_driver =3D { + .probe =3D disp_cc_0_nord_probe, + .driver =3D { + .name =3D "dispcc0-nord", + .of_match_table =3D disp_cc_0_nord_match_table, + }, +}; + +module_platform_driver(disp_cc_0_nord_driver); + +MODULE_DESCRIPTION("QTI DISPCC0 NORD Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/dispcc1-nord.c b/drivers/clk/qcom/dispcc1-nor= d.c new file mode 100644 index 0000000000000000000000000000000000000000..6b4efa735b9e7ab42937ec5a52f= d3c1366f4adf5 --- /dev/null +++ b/drivers/clk/qcom/dispcc1-nord.c @@ -0,0 +1,2004 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_AHB_CLK, + DT_SLEEP_CLK, + + DT_DSI0_PHY_PLL_OUT_BYTECLK, + DT_DSI0_PHY_PLL_OUT_DSICLK, + DT_DSI1_PHY_PLL_OUT_BYTECLK, + DT_DSI1_PHY_PLL_OUT_DSICLK, + + DT_DP0_PHY_PLL_LINK_CLK, + DT_DP0_PHY_PLL_VCO_DIV_CLK, + DT_DP1_PHY_PLL_LINK_CLK, + DT_DP1_PHY_PLL_VCO_DIV_CLK, + DT_DP2_PHY_PLL_LINK_CLK, + DT_DP2_PHY_PLL_VCO_DIV_CLK, + DT_DP3_PHY_PLL_LINK_CLK, + DT_DP3_PHY_PLL_VCO_DIV_CLK, +}; + +enum { + P_BI_TCXO, + P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, + P_MDSS_1_DISP_CC_PLL1_OUT_EVEN, + P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, + P_MDSS_1_DISP_CC_PLL2_OUT_MAIN, + P_MDSS_1_DISP_CC_PLL3_OUT_MAIN, + P_DP0_PHY_PLL_LINK_CLK, + P_DP0_PHY_PLL_VCO_DIV_CLK, + P_DP1_PHY_PLL_LINK_CLK, + P_DP1_PHY_PLL_VCO_DIV_CLK, + P_DP2_PHY_PLL_LINK_CLK, + P_DP2_PHY_PLL_VCO_DIV_CLK, + P_DP3_PHY_PLL_LINK_CLK, + P_DP3_PHY_PLL_VCO_DIV_CLK, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_BYTECLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +static const struct pll_vco zonda_ole_vco[] =3D { + { 700000000, 3600000000, 0 }, +}; + +/* 900.0 MHz Configuration */ +static const struct alpha_pll_config mdss_1_disp_cc_pll0_config =3D { + .l =3D 0x2e, + .alpha =3D 0xe000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll mdss_1_disp_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &mdss_1_disp_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 600.0 MHz Configuration */ +static const struct alpha_pll_config mdss_1_disp_cc_pll1_config =3D { + .l =3D 0x1f, + .alpha =3D 0x4000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll mdss_1_disp_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &mdss_1_disp_cc_pll1_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1363.2 MHz Configuration */ +static const struct alpha_pll_config mdss_1_disp_cc_pll2_config =3D { + .l =3D 0x47, + .alpha =3D 0x0, + .config_ctl_val =3D 0x08240800, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x00000000, + .config_ctl_hi2_val =3D 0x00000000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000080, +}; + +static struct clk_alpha_pll mdss_1_disp_cc_pll2 =3D { + .offset =3D 0x2000, + .config =3D &mdss_1_disp_cc_pll2_config, + .vco_table =3D zonda_ole_vco, + .num_vco =3D ARRAY_SIZE(zonda_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_pll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_zonda_ole_ops, + }, + }, +}; + +/* 1363.2 MHz Configuration */ +static const struct alpha_pll_config mdss_1_disp_cc_pll3_config =3D { + .l =3D 0x47, + .alpha =3D 0x0, + .config_ctl_val =3D 0x08240800, + .config_ctl_hi_val =3D 0x05008001, + .config_ctl_hi1_val =3D 0x00000000, + .config_ctl_hi2_val =3D 0x00000000, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000080, +}; + +static struct clk_alpha_pll mdss_1_disp_cc_pll3 =3D { + .offset =3D 0x3000, + .config =3D &mdss_1_disp_cc_pll3_config, + .vco_table =3D zonda_ole_vco, + .num_vco =3D ARRAY_SIZE(zonda_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_pll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_zonda_ole_ops, + }, + }, +}; + +static const struct parent_map disp_cc_1_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_MDSS_1_DISP_CC_PLL2_OUT_MAIN, 1 }, + { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, + { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, + { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, + { P_MDSS_1_DISP_CC_PLL3_OUT_MAIN, 5 }, + { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &mdss_1_disp_cc_pll2.clkr.hw }, + { .index =3D DT_DP0_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DP3_PHY_PLL_VCO_DIV_CLK }, + { .index =3D DT_DP1_PHY_PLL_VCO_DIV_CLK }, + { .hw =3D &mdss_1_disp_cc_pll3.clkr.hw }, + { .index =3D DT_DP2_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_1_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map disp_cc_1_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_DSICLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_1_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_MDSS_1_DISP_CC_PLL2_OUT_MAIN, 1 }, + { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, + { P_MDSS_1_DISP_CC_PLL3_OUT_MAIN, 5 }, + { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &mdss_1_disp_cc_pll2.clkr.hw }, + { .index =3D DT_DP3_PHY_PLL_VCO_DIV_CLK }, + { .hw =3D &mdss_1_disp_cc_pll3.clkr.hw }, + { .index =3D DT_DP2_PHY_PLL_VCO_DIV_CLK }, +}; + +static const struct parent_map disp_cc_1_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_DP0_PHY_PLL_LINK_CLK, 1 }, + { P_DP1_PHY_PLL_LINK_CLK, 2 }, + { P_DP2_PHY_PLL_LINK_CLK, 3 }, + { P_DP3_PHY_PLL_LINK_CLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP0_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP1_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP2_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP3_PHY_PLL_LINK_CLK }, +}; + +static const struct parent_map disp_cc_1_parent_map_5[] =3D { + { P_BI_TCXO, 0 }, + { P_DP2_PHY_PLL_LINK_CLK, 3 }, + { P_DP3_PHY_PLL_LINK_CLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_5[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DP2_PHY_PLL_LINK_CLK }, + { .index =3D DT_DP3_PHY_PLL_LINK_CLK }, +}; + +static const struct parent_map disp_cc_1_parent_map_6[] =3D { + { P_BI_TCXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_6[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_DSI0_PHY_PLL_OUT_BYTECLK }, + { .index =3D DT_DSI1_PHY_PLL_OUT_BYTECLK }, +}; + +static const struct parent_map disp_cc_1_parent_map_7[] =3D { + { P_BI_TCXO, 0 }, + { P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 4 }, + { P_MDSS_1_DISP_CC_PLL1_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_7[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &mdss_1_disp_cc_pll1.clkr.hw }, + { .hw =3D &mdss_1_disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_1_parent_map_8[] =3D { + { P_BI_TCXO, 0 }, + { P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 1 }, + { P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 4 }, + { P_MDSS_1_DISP_CC_PLL1_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_8[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &mdss_1_disp_cc_pll0.clkr.hw }, + { .hw =3D &mdss_1_disp_cc_pll1.clkr.hw }, + { .hw =3D &mdss_1_disp_cc_pll1.clkr.hw }, +}; + +static const struct parent_map disp_cc_1_parent_map_9[] =3D { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data disp_cc_1_parent_data_9[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_mdss_1_disp_cc_mdss_ahb_clk_src[] =3D { + F(37500000, P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), + F(75000000, P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_ahb_clk_src =3D { + .cmd_rcgr =3D 0x837c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_7, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_ahb_clk_src", + .parent_data =3D disp_cc_1_parent_data_7, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_7), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_mdss_1_disp_cc_mdss_byte0_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_byte0_clk_src =3D { + .cmd_rcgr =3D 0x813c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_2, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte0_clk_src", + .parent_data =3D disp_cc_1_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_byte1_clk_src =3D { + .cmd_rcgr =3D 0x8158, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_2, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte1_clk_src", + .parent_data =3D disp_cc_1_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_aux_clk_src =3D { + .cmd_rcgr =3D 0x8220, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_1, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_aux_clk_src", + .parent_data =3D disp_cc_1_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_link_clk_src =3D { + .cmd_rcgr =3D 0x81a4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_4, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_link_clk_src", + .parent_data =3D disp_cc_1_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x81c0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x81d8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src =3D { + .cmd_rcgr =3D 0x81f0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src =3D { + .cmd_rcgr =3D 0x8208, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_aux_clk_src =3D { + .cmd_rcgr =3D 0x82b4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_1, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_aux_clk_src", + .parent_data =3D disp_cc_1_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_link_clk_src =3D { + .cmd_rcgr =3D 0x8298, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_4, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_link_clk_src", + .parent_data =3D disp_cc_1_parent_data_4, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x8238, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x8250, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_pixel2_clk_src =3D { + .cmd_rcgr =3D 0x8268, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_pixel2_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_pixel3_clk_src =3D { + .cmd_rcgr =3D 0x8280, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_0, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_pixel3_clk_src", + .parent_data =3D disp_cc_1_parent_data_0, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx2_aux_clk_src =3D { + .cmd_rcgr =3D 0x8318, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_1, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx2_aux_clk_src", + .parent_data =3D disp_cc_1_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx2_link_clk_src =3D { + .cmd_rcgr =3D 0x82cc, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_5, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx2_link_clk_src", + .parent_data =3D disp_cc_1_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx2_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x82e8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_3, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx2_pixel0_clk_src", + .parent_data =3D disp_cc_1_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx2_pixel1_clk_src =3D { + .cmd_rcgr =3D 0x8300, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_3, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx2_pixel1_clk_src", + .parent_data =3D disp_cc_1_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx3_aux_clk_src =3D { + .cmd_rcgr =3D 0x8364, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_1, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx3_aux_clk_src", + .parent_data =3D disp_cc_1_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx3_link_clk_src =3D { + .cmd_rcgr =3D 0x8348, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_5, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx3_link_clk_src", + .parent_data =3D disp_cc_1_parent_data_5, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_5), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx3_pixel0_clk_src =3D { + .cmd_rcgr =3D 0x8330, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_3, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx3_pixel0_clk_src", + .parent_data =3D disp_cc_1_parent_data_3, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_dp_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_esc0_clk_src =3D { + .cmd_rcgr =3D 0x8174, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_6, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_esc0_clk_src", + .parent_data =3D disp_cc_1_parent_data_6, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_esc1_clk_src =3D { + .cmd_rcgr =3D 0x818c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_6, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_esc1_clk_src", + .parent_data =3D disp_cc_1_parent_data_6, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_6), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_mdss_1_disp_cc_mdss_mdp_clk_src[] =3D { + F(300000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(417000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(532000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(650000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(710000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_mdp_clk_src =3D { + .cmd_rcgr =3D 0x810c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_8, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_mdp_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_mdp_clk_src", + .parent_data =3D disp_cc_1_parent_data_8, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_8), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_pclk0_clk_src =3D { + .cmd_rcgr =3D 0x80c4, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_2, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_pclk0_clk_src", + .parent_data =3D disp_cc_1_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_pclk1_clk_src =3D { + .cmd_rcgr =3D 0x80dc, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_2, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_pclk1_clk_src", + .parent_data =3D disp_cc_1_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_pclk2_clk_src =3D { + .cmd_rcgr =3D 0x80f4, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_2, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_pclk2_clk_src", + .parent_data =3D disp_cc_1_parent_data_2, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_mdss_vsync_clk_src =3D { + .cmd_rcgr =3D 0x8124, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_1, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_vsync_clk_src", + .parent_data =3D disp_cc_1_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_mdss_1_disp_cc_sleep_clk_src[] =3D { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 mdss_1_disp_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0xe064, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_9, + .freq_tbl =3D ftbl_mdss_1_disp_cc_sleep_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_sleep_clk_src", + .parent_data =3D disp_cc_1_parent_data_9, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_9), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 mdss_1_disp_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0xe044, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D disp_cc_1_parent_map_1, + .freq_tbl =3D ftbl_mdss_1_disp_cc_mdss_byte0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_xo_clk_src", + .parent_data =3D disp_cc_1_parent_data_1, + .num_parents =3D ARRAY_SIZE(disp_cc_1_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div mdss_1_disp_cc_mdss_byte0_div_clk_src =3D { + .reg =3D 0x8154, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte0_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div mdss_1_disp_cc_mdss_byte1_div_clk_src =3D { + .reg =3D 0x8170, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte1_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div mdss_1_disp_cc_mdss_dptx0_link_div_clk_src = =3D { + .reg =3D 0x81bc, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div mdss_1_disp_cc_mdss_dptx1_link_div_clk_src = =3D { + .reg =3D 0x82b0, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div mdss_1_disp_cc_mdss_dptx2_link_div_clk_src = =3D { + .reg =3D 0x82e4, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx2_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx2_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div mdss_1_disp_cc_mdss_dptx3_link_div_clk_src = =3D { + .reg =3D 0x8360, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx3_link_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx3_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_accu_shift_clk =3D { + .halt_reg =3D 0xe060, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xe060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_accu_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_ahb1_clk =3D { + .halt_reg =3D 0xa028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_ahb1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_ahb_clk =3D { + .halt_reg =3D 0x80c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_byte0_clk =3D { + .halt_reg =3D 0x8034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_byte0_intf_clk =3D { + .halt_reg =3D 0x8038, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8038, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte0_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_byte1_clk =3D { + .halt_reg =3D 0x803c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x803c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_byte1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_byte1_intf_clk =3D { + .halt_reg =3D 0x8040, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8040, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_byte1_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_byte1_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_aux_clk =3D { + .halt_reg =3D 0x806c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x806c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_crypto_clk =3D { + .halt_reg =3D 0x8058, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8058, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_link_clk =3D { + .halt_reg =3D 0x804c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x804c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_link_intf_clk =3D { + .halt_reg =3D 0x8054, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel0_clk =3D { + .halt_reg =3D 0x805c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x805c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel1_clk =3D { + .halt_reg =3D 0x8060, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8060, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel2_clk =3D { + .halt_reg =3D 0x8064, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8064, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel3_clk =3D { + .halt_reg =3D 0x8068, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_pixel3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx0_usb_router_link_intf_cl= k =3D { + .halt_reg =3D 0x8050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx0_usb_router_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_aux_clk =3D { + .halt_reg =3D 0x8090, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_crypto_clk =3D { + .halt_reg =3D 0x808c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x808c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_link_clk =3D { + .halt_reg =3D 0x8080, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8080, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_link_intf_clk =3D { + .halt_reg =3D 0x8088, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8088, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_pixel0_clk =3D { + .halt_reg =3D 0x8070, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8070, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_pixel1_clk =3D { + .halt_reg =3D 0x8074, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8074, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_pixel2_clk =3D { + .halt_reg =3D 0x8078, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8078, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_pixel2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_pixel2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_pixel3_clk =3D { + .halt_reg =3D 0x807c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x807c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_pixel3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_pixel3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx1_usb_router_link_intf_cl= k =3D { + .halt_reg =3D 0x8084, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8084, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx1_usb_router_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx2_aux_clk =3D { + .halt_reg =3D 0x80a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx2_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx2_crypto_clk =3D { + .halt_reg =3D 0x80a4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x80a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx2_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx2_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx2_link_clk =3D { + .halt_reg =3D 0x809c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x809c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx2_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx2_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx2_link_intf_clk =3D { + .halt_reg =3D 0x80a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx2_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx2_pixel0_clk =3D { + .halt_reg =3D 0x8094, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8094, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx2_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx2_pixel1_clk =3D { + .halt_reg =3D 0x8098, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8098, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx2_pixel1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx3_aux_clk =3D { + .halt_reg =3D 0x80b8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx3_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx3_crypto_clk =3D { + .halt_reg =3D 0x80bc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x80bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx3_crypto_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx3_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx3_link_clk =3D { + .halt_reg =3D 0x80b0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80b0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx3_link_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx3_link_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx3_link_intf_clk =3D { + .halt_reg =3D 0x80b4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx3_link_intf_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_dptx3_pixel0_clk =3D { + .halt_reg =3D 0x80ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_dptx3_pixel0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_esc0_clk =3D { + .halt_reg =3D 0x8044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_esc0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_esc1_clk =3D { + .halt_reg =3D 0x8048, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8048, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_esc1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_esc1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_mdp1_clk =3D { + .halt_reg =3D 0xa004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_mdp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_mdp_clk =3D { + .halt_reg =3D 0x8010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_mdp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_mdp_lut1_clk =3D { + .halt_reg =3D 0xa014, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xa014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_mdp_lut1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_mdp_lut_clk =3D { + .halt_reg =3D 0x8020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x8020, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_mdp_lut_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_non_gdsc_ahb_clk =3D { + .halt_reg =3D 0xc004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0xc004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_non_gdsc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_pclk0_clk =3D { + .halt_reg =3D 0x8004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_pclk0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_pclk1_clk =3D { + .halt_reg =3D 0x8008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_pclk1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_pclk1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_pclk2_clk =3D { + .halt_reg =3D 0x800c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x800c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_pclk2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_pclk2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_vsync1_clk =3D { + .halt_reg =3D 0xa024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0xa024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_vsync1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_1_disp_cc_mdss_vsync_clk =3D { + .halt_reg =3D 0x8030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "mdss_1_disp_cc_mdss_vsync_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &mdss_1_disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_1_disp_cc_mdss_core_gdsc =3D { + .gdscr =3D 0x9000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "mdss_1_disp_cc_mdss_core_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc mdss_1_disp_cc_mdss_core_int2_gdsc =3D { + .gdscr =3D 0xb000, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "mdss_1_disp_cc_mdss_core_int2_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *disp_cc_1_nord_clocks[] =3D { + [MDSS_DISP_CC_MDSS_ACCU_SHIFT_CLK] =3D &mdss_1_disp_cc_mdss_accu_shift_cl= k.clkr, + [MDSS_DISP_CC_MDSS_AHB1_CLK] =3D &mdss_1_disp_cc_mdss_ahb1_clk.clkr, + [MDSS_DISP_CC_MDSS_AHB_CLK] =3D &mdss_1_disp_cc_mdss_ahb_clk.clkr, + [MDSS_DISP_CC_MDSS_AHB_CLK_SRC] =3D &mdss_1_disp_cc_mdss_ahb_clk_src.clkr, + [MDSS_DISP_CC_MDSS_BYTE0_CLK] =3D &mdss_1_disp_cc_mdss_byte0_clk.clkr, + [MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC] =3D &mdss_1_disp_cc_mdss_byte0_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] =3D &mdss_1_disp_cc_mdss_byte0_div_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK] =3D &mdss_1_disp_cc_mdss_byte0_intf_cl= k.clkr, + [MDSS_DISP_CC_MDSS_BYTE1_CLK] =3D &mdss_1_disp_cc_mdss_byte1_clk.clkr, + [MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC] =3D &mdss_1_disp_cc_mdss_byte1_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =3D &mdss_1_disp_cc_mdss_byte1_div_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK] =3D &mdss_1_disp_cc_mdss_byte1_intf_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_aux_clk.= clkr, + [MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_aux_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_crypt= o_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_link_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_lin= k_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] =3D + &mdss_1_disp_cc_mdss_dptx0_link_div_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_li= nk_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_pixel= 0_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_p= ixel0_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_pixel= 1_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_p= ixel1_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_pixel= 2_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_p= ixel2_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK] =3D &mdss_1_disp_cc_mdss_dptx0_pixel= 3_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx0_p= ixel3_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =3D + &mdss_1_disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_aux_clk.= clkr, + [MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx1_aux_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_crypt= o_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_link_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx1_lin= k_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] =3D + &mdss_1_disp_cc_mdss_dptx1_link_div_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_li= nk_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_pixel= 0_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx1_p= ixel0_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_pixel= 1_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx1_p= ixel1_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_pixel= 2_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL2_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx1_p= ixel2_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK] =3D &mdss_1_disp_cc_mdss_dptx1_pixel= 3_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_PIXEL3_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx1_p= ixel3_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =3D + &mdss_1_disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK] =3D &mdss_1_disp_cc_mdss_dptx2_aux_clk.= clkr, + [MDSS_DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx2_aux_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_CRYPTO_CLK] =3D &mdss_1_disp_cc_mdss_dptx2_crypt= o_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK] =3D &mdss_1_disp_cc_mdss_dptx2_link_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx2_lin= k_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] =3D + &mdss_1_disp_cc_mdss_dptx2_link_div_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] =3D &mdss_1_disp_cc_mdss_dptx2_li= nk_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK] =3D &mdss_1_disp_cc_mdss_dptx2_pixel= 0_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx2_p= ixel0_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK] =3D &mdss_1_disp_cc_mdss_dptx2_pixel= 1_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx2_p= ixel1_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK] =3D &mdss_1_disp_cc_mdss_dptx3_aux_clk.= clkr, + [MDSS_DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx3_aux_= clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_CRYPTO_CLK] =3D &mdss_1_disp_cc_mdss_dptx3_crypt= o_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK] =3D &mdss_1_disp_cc_mdss_dptx3_link_cl= k.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx3_lin= k_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] =3D + &mdss_1_disp_cc_mdss_dptx3_link_div_clk_src.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] =3D &mdss_1_disp_cc_mdss_dptx3_li= nk_intf_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK] =3D &mdss_1_disp_cc_mdss_dptx3_pixel= 0_clk.clkr, + [MDSS_DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] =3D &mdss_1_disp_cc_mdss_dptx3_p= ixel0_clk_src.clkr, + [MDSS_DISP_CC_MDSS_ESC0_CLK] =3D &mdss_1_disp_cc_mdss_esc0_clk.clkr, + [MDSS_DISP_CC_MDSS_ESC0_CLK_SRC] =3D &mdss_1_disp_cc_mdss_esc0_clk_src.cl= kr, + [MDSS_DISP_CC_MDSS_ESC1_CLK] =3D &mdss_1_disp_cc_mdss_esc1_clk.clkr, + [MDSS_DISP_CC_MDSS_ESC1_CLK_SRC] =3D &mdss_1_disp_cc_mdss_esc1_clk_src.cl= kr, + [MDSS_DISP_CC_MDSS_MDP1_CLK] =3D &mdss_1_disp_cc_mdss_mdp1_clk.clkr, + [MDSS_DISP_CC_MDSS_MDP_CLK] =3D &mdss_1_disp_cc_mdss_mdp_clk.clkr, + [MDSS_DISP_CC_MDSS_MDP_CLK_SRC] =3D &mdss_1_disp_cc_mdss_mdp_clk_src.clkr, + [MDSS_DISP_CC_MDSS_MDP_LUT1_CLK] =3D &mdss_1_disp_cc_mdss_mdp_lut1_clk.cl= kr, + [MDSS_DISP_CC_MDSS_MDP_LUT_CLK] =3D &mdss_1_disp_cc_mdss_mdp_lut_clk.clkr, + [MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK] =3D &mdss_1_disp_cc_mdss_non_gdsc_ah= b_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK0_CLK] =3D &mdss_1_disp_cc_mdss_pclk0_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC] =3D &mdss_1_disp_cc_mdss_pclk0_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_PCLK1_CLK] =3D &mdss_1_disp_cc_mdss_pclk1_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC] =3D &mdss_1_disp_cc_mdss_pclk1_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_PCLK2_CLK] =3D &mdss_1_disp_cc_mdss_pclk2_clk.clkr, + [MDSS_DISP_CC_MDSS_PCLK2_CLK_SRC] =3D &mdss_1_disp_cc_mdss_pclk2_clk_src.= clkr, + [MDSS_DISP_CC_MDSS_VSYNC1_CLK] =3D &mdss_1_disp_cc_mdss_vsync1_clk.clkr, + [MDSS_DISP_CC_MDSS_VSYNC_CLK] =3D &mdss_1_disp_cc_mdss_vsync_clk.clkr, + [MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC] =3D &mdss_1_disp_cc_mdss_vsync_clk_src.= clkr, + [MDSS_DISP_CC_PLL0] =3D &mdss_1_disp_cc_pll0.clkr, + [MDSS_DISP_CC_PLL1] =3D &mdss_1_disp_cc_pll1.clkr, + [MDSS_DISP_CC_PLL2] =3D &mdss_1_disp_cc_pll2.clkr, + [MDSS_DISP_CC_PLL3] =3D &mdss_1_disp_cc_pll3.clkr, + [MDSS_DISP_CC_SLEEP_CLK_SRC] =3D &mdss_1_disp_cc_sleep_clk_src.clkr, + [MDSS_DISP_CC_XO_CLK_SRC] =3D &mdss_1_disp_cc_xo_clk_src.clkr, +}; + +static struct gdsc *disp_cc_1_nord_gdscs[] =3D { + [MDSS_DISP_CC_MDSS_CORE_GDSC] =3D &mdss_1_disp_cc_mdss_core_gdsc, + [MDSS_DISP_CC_MDSS_CORE_INT2_GDSC] =3D &mdss_1_disp_cc_mdss_core_int2_gds= c, +}; + +static const struct qcom_reset_map disp_cc_1_nord_resets[] =3D { + [MDSS_DISP_CC_MDSS_CORE_BCR] =3D { 0x8000 }, + [MDSS_DISP_CC_MDSS_CORE_INT2_BCR] =3D { 0xa000 }, + [MDSS_DISP_CC_MDSS_RSCC_BCR] =3D { 0xc000 }, +}; + +static struct clk_alpha_pll *disp_cc_1_nord_plls[] =3D { + &mdss_1_disp_cc_pll0, + &mdss_1_disp_cc_pll1, + &mdss_1_disp_cc_pll2, + &mdss_1_disp_cc_pll3, +}; + +static const u32 disp_cc_1_nord_critical_cbcrs[] =3D { + 0xc00c, /* MDSS_DISP_CC_RSCC_AHB_CLK */ + 0xc008, /* MDSS_DISP_CC_RSCC_VSYNC CLK */ + 0xe07c, /* MDSS_DISP_CC_SLEEP_CLK */ + 0xe05c, /* MDSS_DISP_CC_XO_CLK */ +}; + +static const struct regmap_config disp_cc_1_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1a00c, + .fast_io =3D true, +}; + +static const struct qcom_cc_driver_data disp_cc_1_nord_driver_data =3D { + .alpha_plls =3D disp_cc_1_nord_plls, + .num_alpha_plls =3D ARRAY_SIZE(disp_cc_1_nord_plls), + .clk_cbcrs =3D disp_cc_1_nord_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(disp_cc_1_nord_critical_cbcrs), +}; + +static const struct qcom_cc_desc disp_cc_1_nord_desc =3D { + .config =3D &disp_cc_1_nord_regmap_config, + .clks =3D disp_cc_1_nord_clocks, + .num_clks =3D ARRAY_SIZE(disp_cc_1_nord_clocks), + .resets =3D disp_cc_1_nord_resets, + .num_resets =3D ARRAY_SIZE(disp_cc_1_nord_resets), + .gdscs =3D disp_cc_1_nord_gdscs, + .num_gdscs =3D ARRAY_SIZE(disp_cc_1_nord_gdscs), + .use_rpm =3D true, + .driver_data =3D &disp_cc_1_nord_driver_data, +}; + +static const struct of_device_id disp_cc_1_nord_match_table[] =3D { + { .compatible =3D "qcom,nord-dispcc1" }, + { } +}; +MODULE_DEVICE_TABLE(of, disp_cc_1_nord_match_table); + +static int disp_cc_1_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &disp_cc_1_nord_desc); +} + +static struct platform_driver disp_cc_1_nord_driver =3D { + .probe =3D disp_cc_1_nord_probe, + .driver =3D { + .name =3D "dispcc1-nord", + .of_match_table =3D disp_cc_1_nord_match_table, + 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with ESMTPSA id d2e1a72fcca58-84c2adcc74csm7080833b3a.18.2026.07.21.00.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2026 00:08:00 -0700 (PDT) From: Taniya Das Date: Tue, 21 Jul 2026 12:37:20 +0530 Subject: [PATCH v2 5/6] dt-bindings: clock: qcom: Document Nord GPU clock controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260721-nords_mm_v1-v2-5-17e5a445a512@oss.qualcomm.com> References: <20260721-nords_mm_v1-v2-0-17e5a445a512@oss.qualcomm.com> In-Reply-To: <20260721-nords_mm_v1-v2-0-17e5a445a512@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Shawn Guo , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , 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controllers on the Qualcomm Nord platform. The platform includes two GPU clock controller instances, GPUCC and GPUCC2. Document the compatible strings for both controllers. Signed-off-by: Taniya Das Reviewed-by: Alexandre Mergnat Reviewed-by: Krzysztof Kozlowski Reviewed-by: Shawn Guo --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 3 ++ include/dt-bindings/clock/qcom,nord-gpu2cc.h | 47 ++++++++++++++++++= +++ include/dt-bindings/clock/qcom,nord-gpucc.h | 48 ++++++++++++++++++= ++++ 3 files changed, 98 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index fdbdf605ee695637512ce4f98c9b6fcfacb9154f..ba85692240e07a4ed8e69c6b618= 47c5601b32fa0 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -18,6 +18,7 @@ description: | include/dt-bindings/clock/qcom,glymur-gpucc.h include/dt-bindings/clock/qcom,kaanapali-gpucc.h include/dt-bindings/clock/qcom,milos-gpucc.h + include/dt-bindings/clock/qcom,nord-gpucc.h include/dt-bindings/clock/qcom,sar2130p-gpucc.h include/dt-bindings/clock/qcom,sm4450-gpucc.h include/dt-bindings/clock/qcom,sm8450-gpucc.h @@ -33,6 +34,8 @@ properties: - qcom,glymur-gpucc - qcom,kaanapali-gpucc - qcom,milos-gpucc + - qcom,nord-gpu2cc + - qcom,nord-gpucc - qcom,sar2130p-gpucc - qcom,sm4450-gpucc - qcom,sm8450-gpucc diff --git a/include/dt-bindings/clock/qcom,nord-gpu2cc.h b/include/dt-bind= ings/clock/qcom,nord-gpu2cc.h new file mode 100644 index 0000000000000000000000000000000000000000..3886af669c61003f71e2da28f93= 9f273e761c653 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-gpu2cc.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_2_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_GPU_2_CC_NORD_H + +/* GPU_2_CC clocks */ +#define GPU_2_CC_AHB_CLK 0 +#define GPU_2_CC_CRC_AHB_CLK 1 +#define GPU_2_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_2_CC_CX_FF_CLK 3 +#define GPU_2_CC_CX_GMU_CLK 4 +#define GPU_2_CC_CXO_AON_CLK 5 +#define GPU_2_CC_CXO_CLK 6 +#define GPU_2_CC_DEMET_CLK 7 +#define GPU_2_CC_FF_CLK_SRC 8 +#define GPU_2_CC_FREQ_MEASURE_CLK 9 +#define GPU_2_CC_GMU_CLK_SRC 10 +#define GPU_2_CC_GPU_SMMU_VOTE_CLK 11 +#define GPU_2_CC_HUB_AON_CLK 12 +#define GPU_2_CC_HUB_CLK_SRC 13 +#define GPU_2_CC_HUB_CX_INT_CLK 14 +#define GPU_2_CC_MEMNOC_GFX_CLK 15 +#define GPU_2_CC_MND1X_0_GFX3D_CLK 16 +#define GPU_2_CC_MND1X_1_GFX3D_CLK 17 +#define GPU_2_CC_PLL0 18 +#define GPU_2_CC_PLL1 19 +#define GPU_2_CC_SLEEP_CLK 20 + +/* GPU_2_CC power domains */ +#define GPU_2_CC_CX_GDSC 0 +#define GPU_2_CC_GX_GDSC 1 + +/* GPU_2_CC resets */ +#define GPU_2_CC_ACD_BCR 0 +#define GPU_2_CC_CB_BCR 1 +#define GPU_2_CC_CX_BCR 2 +#define GPU_2_CC_FAST_HUB_BCR 3 +#define GPU_2_CC_FF_BCR 4 +#define GPU_2_CC_GFX3D_AON_BCR 5 +#define GPU_2_CC_GMU_BCR 6 +#define GPU_2_CC_GX_BCR 7 +#define GPU_2_CC_XO_BCR 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-gpucc.h b/include/dt-bindi= ngs/clock/qcom,nord-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..3cc348be5668b309a151665fc29= bdcb30c480740 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-gpucc.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_NORD_H + +/* GPU_CC clocks */ +#define GPU_CC_ACD_GFX3D_CLK 0 +#define GPU_CC_ACMU_CLK 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CRC_AHB_CLK 3 +#define GPU_CC_CX_ACCU_SHIFT_CLK 4 +#define GPU_CC_CX_FF_CLK 5 +#define GPU_CC_CX_GMU_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_DEMET_CLK 9 +#define GPU_CC_DPM_CLK 10 +#define GPU_CC_FF_CLK_SRC 11 +#define GPU_CC_FREQ_MEASURE_CLK 12 +#define GPU_CC_GMU_CLK_SRC 13 +#define GPU_CC_GPU_SMMU_VOTE_CLK 14 +#define GPU_CC_HUB_AON_CLK 15 +#define GPU_CC_HUB_CLK_SRC 16 +#define GPU_CC_HUB_CX_INT_CLK 17 +#define GPU_CC_HUB_DIV_CLK_SRC 18 +#define GPU_CC_MEMNOC_GFX_CLK 19 +#define GPU_CC_MND1X_GFX3D_CLK 20 +#define GPU_CC_PLL0 21 +#define GPU_CC_PLL1 22 +#define GPU_CC_SLEEP_CLK 23 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_ACD_BCR 0 +#define GPU_CC_CB_BCR 1 +#define GPU_CC_CX_BCR 2 +#define GPU_CC_FAST_HUB_BCR 3 +#define GPU_CC_GFX3D_AON_BCR 4 +#define GPU_CC_GX_BCR 5 +#define GPU_CC_XO_BCR 6 + +#endif --=20 2.34.1 From nobody Sat Jul 25 01:40:44 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85229432BEE for ; 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Tue, 21 Jul 2026 00:08:07 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84c2adcc74csm7080833b3a.18.2026.07.21.00.08.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2026 00:08:06 -0700 (PDT) From: Taniya Das Date: Tue, 21 Jul 2026 12:37:21 +0530 Subject: [PATCH v2 6/6] clk: qcom: gpucc: Add Nord graphics clock controller support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260721-nords_mm_v1-v2-6-17e5a445a512@oss.qualcomm.com> References: <20260721-nords_mm_v1-v2-0-17e5a445a512@oss.qualcomm.com> In-Reply-To: <20260721-nords_mm_v1-v2-0-17e5a445a512@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Shawn Guo , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA3MyBTYWx0ZWRfX9vB7XnmsfVfH vEL7asATwq7EozMEaEq7EeO5lfkcGtaKhpcYwOGEZwEh1aS3ZV24+wmtGPI4C5bPKFIANtnjMiL ZFQp/9MWK4xx4l4QZzz/U+/MWUSxwDo4crLFk/JAdEnOAUKrPrP3AtYntFZ1WTTZsaOMpU15LVZ AvpI3MgVJyLgSzncVDjkjqjsYcrVOozOeY7aqqf8dSZo8O1PakA89OM/dpT2Z8o3nqteBfQolzn qSWZGkJsF7RL0VNcBE62xmIy3VMc8akGniJrDOKgibfdGyUzdptIyBsglDKTNcHzBHrFou6Icr4 aGgTUriRDDWz5duafVIuL0noG2J0q/K6dc4Jxv7nr+v/kt7YeGpxu1nPu3dAOP/4LPgixH79Q0Z LVBUy69k345hk1Zu4aeFi3zQZ+XbioAckEx4G9p6Zp1SS9rmBVCXEIOpmcVp3g/28BunvCddEy5 1dMkXIoRtmsByNjFLYg== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA3MyBTYWx0ZWRfX1DN62KCiBOX6 sgXW3Ind0YKd2YF0gp/2+k/I9CH9/RWEphNPBidqpFSkoqnbPsK66l9gwIdurX56jgR+8IRc155 B6kCKU/MDUfjQIKjsh94kUZstllUGx0= X-Authority-Analysis: v=2.4 cv=DoFmPm/+ c=1 sm=1 tr=0 ts=6a5f1ad8 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=F3NrMrZ0Zf_nGyolyosA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: gl7TAF-h2ljAezwXXLJIfRI_Wu9MacEU X-Proofpoint-ORIG-GUID: gl7TAF-h2ljAezwXXLJIfRI_Wu9MacEU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 suspectscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210073 Add support for the GPU clock controllers (GPUCC) on the Qualcomm Nord platform. The platform includes two GPU clock controller instances,GPUCC and GPU2CC. Register support for both controllers, which provide clocks required for the graphics subsystem. Signed-off-by: Taniya Das Reviewed-by: Alexandre Mergnat Reviewed-by: Shawn Guo --- drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpu2cc-nord.c | 545 +++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/gpucc-nord.c | 593 +++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 1150 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 874136a2ad9aaa117df2c7ad5c8abc5280b76339..10dcfa72a0bd3bdd70e2bee0596= 4e8c275ceb07d 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -166,6 +166,17 @@ config CLK_NORD_GCC SPI, I2C, USB, SD/UFS, PCIe etc. The clock controller is a combination of GCC, SE_GCC, NE_GCC and NW_GCC. =20 +config CLK_NORD_GPUCC + tristate "Nord Graphics Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_NORD_GCC + default m if ARCH_QCOM + help + Support for the graphics clock controllers on Nord devices. There are t= wo + graphics clock controllers on Nord SoC. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config CLK_X1E80100_CAMCC tristate "X1E80100 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 4282f43e7078f1fe0dde6f942040eb6bd122d7ce..fb0a5bc94e32b2dc1d56268aa87= f455b20d779eb 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o obj-$(CONFIG_CLK_NORD_DISPCC) +=3D dispcc0-nord.o dispcc1-nord.o obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o +obj-$(CONFIG_CLK_NORD_GPUCC) +=3D gpucc-nord.o gpu2cc-nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o diff --git a/drivers/clk/qcom/gpu2cc-nord.c b/drivers/clk/qcom/gpu2cc-nord.c new file mode 100644 index 0000000000000000000000000000000000000000..a05ff9fa1506e9d63b789127866= ea5c37e5a1e2f --- /dev/null +++ b/drivers/clk/qcom/gpu2cc-nord.c @@ -0,0 +1,545 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_2_CC_PLL0_OUT_MAIN, + P_GPU_2_CC_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +/* 934.0 MHz Configuration */ +static const struct alpha_pll_config gpu_2_cc_pll0_config =3D { + .l =3D 0x30, + .alpha =3D 0xa555, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll gpu_2_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &gpu_2_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1100.0 MHz Configuration */ +static const struct alpha_pll_config gpu_2_cc_pll1_config =3D { + .l =3D 0x39, + .alpha =3D 0x4aaa, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll gpu_2_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &gpu_2_cc_pll1_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gpu_2_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_2_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_2_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_2_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_2_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_2_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_2_cc_pll0.clkr.hw }, + { .hw =3D &gpu_2_cc_pll1.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_2_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_2_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_2_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_2_cc_pll1.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct freq_tbl ftbl_gpu_2_cc_ff_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_2_cc_ff_clk_src =3D { + .cmd_rcgr =3D 0x91c4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_2_cc_parent_map_0, + .freq_tbl =3D ftbl_gpu_2_cc_ff_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_ff_clk_src", + .parent_data =3D gpu_2_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gpu_2_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_2_cc_gmu_clk_src[] =3D { + F(550000000, P_GPU_2_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_2_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x9174, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_2_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_2_cc_gmu_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_gmu_clk_src", + .parent_data =3D gpu_2_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_2_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gpu_2_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x91a8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_2_cc_parent_map_2, + .freq_tbl =3D ftbl_gpu_2_cc_ff_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_hub_clk_src", + .parent_data =3D gpu_2_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gpu_2_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch gpu_2_cc_ahb_clk =3D { + .halt_reg =3D 0x90cc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_2_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_crc_ahb_clk =3D { + .halt_reg =3D 0x90d0, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_crc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_2_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x9114, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9114, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_cx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_cx_ff_clk =3D { + .halt_reg =3D 0x9100, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9100, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_cx_ff_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_2_cc_ff_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x90e8, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90e8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_2_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_cxo_clk =3D { + .halt_reg =3D 0x90f8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x90f8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_cxo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_freq_measure_clk =3D { + .halt_reg =3D 0x9008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_freq_measure_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_gpu_smmu_vote_clk =3D { + .halt_reg =3D 0x7000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_gpu_smmu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_hub_aon_clk =3D { + .halt_reg =3D 0x91a4, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x91a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_2_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x90fc, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x90fc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_2_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_memnoc_gfx_clk =3D { + .halt_reg =3D 0x9104, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9104, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_mnd1x_0_gfx3d_clk =3D { + .halt_reg =3D 0x9164, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9164, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_mnd1x_0_gfx3d_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_mnd1x_1_gfx3d_clk =3D { + .halt_reg =3D 0x9168, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9168, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_mnd1x_1_gfx3d_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_2_cc_sleep_clk =3D { + .halt_reg =3D 0x90e0, + .halt_check =3D BRANCH_HALT_SKIP, + .clkr =3D { + .enable_reg =3D 0x90e0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_2_cc_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_2_cc_cx_gdsc =3D { + .gdscr =3D 0x9090, + .gds_hw_ctrl =3D 0x90a4, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gpu_2_cc_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE | RETAIN_FF_ENABLE, +}; + +static struct gdsc gpu_2_cc_gx_gdsc =3D { + .gdscr =3D 0x9034, + .clamp_io_ctrl =3D 0x9504, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gpu_2_cc_gx_gdsc", + .power_on =3D gdsc_gx_do_nothing_enable, + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gpu_2_cc_nord_clocks[] =3D { + [GPU_2_CC_AHB_CLK] =3D &gpu_2_cc_ahb_clk.clkr, + [GPU_2_CC_CRC_AHB_CLK] =3D &gpu_2_cc_crc_ahb_clk.clkr, + [GPU_2_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_2_cc_cx_accu_shift_clk.clkr, + [GPU_2_CC_CX_FF_CLK] =3D &gpu_2_cc_cx_ff_clk.clkr, + [GPU_2_CC_CX_GMU_CLK] =3D &gpu_2_cc_cx_gmu_clk.clkr, + [GPU_2_CC_CXO_CLK] =3D &gpu_2_cc_cxo_clk.clkr, + [GPU_2_CC_FF_CLK_SRC] =3D &gpu_2_cc_ff_clk_src.clkr, + [GPU_2_CC_FREQ_MEASURE_CLK] =3D &gpu_2_cc_freq_measure_clk.clkr, + [GPU_2_CC_GMU_CLK_SRC] =3D &gpu_2_cc_gmu_clk_src.clkr, + [GPU_2_CC_GPU_SMMU_VOTE_CLK] =3D &gpu_2_cc_gpu_smmu_vote_clk.clkr, + [GPU_2_CC_HUB_AON_CLK] =3D &gpu_2_cc_hub_aon_clk.clkr, + [GPU_2_CC_HUB_CLK_SRC] =3D &gpu_2_cc_hub_clk_src.clkr, + [GPU_2_CC_HUB_CX_INT_CLK] =3D &gpu_2_cc_hub_cx_int_clk.clkr, + [GPU_2_CC_MEMNOC_GFX_CLK] =3D &gpu_2_cc_memnoc_gfx_clk.clkr, + [GPU_2_CC_MND1X_0_GFX3D_CLK] =3D &gpu_2_cc_mnd1x_0_gfx3d_clk.clkr, + [GPU_2_CC_MND1X_1_GFX3D_CLK] =3D &gpu_2_cc_mnd1x_1_gfx3d_clk.clkr, + [GPU_2_CC_PLL0] =3D &gpu_2_cc_pll0.clkr, + [GPU_2_CC_PLL1] =3D &gpu_2_cc_pll1.clkr, + [GPU_2_CC_SLEEP_CLK] =3D &gpu_2_cc_sleep_clk.clkr, +}; + +static struct gdsc *gpu_2_cc_nord_gdscs[] =3D { + [GPU_2_CC_CX_GDSC] =3D &gpu_2_cc_cx_gdsc, + [GPU_2_CC_GX_GDSC] =3D &gpu_2_cc_gx_gdsc, +}; + +static const struct qcom_reset_map gpu_2_cc_nord_resets[] =3D { + [GPU_2_CC_ACD_BCR] =3D { 0x918c }, + [GPU_2_CC_CB_BCR] =3D { 0x9198 }, + [GPU_2_CC_CX_BCR] =3D { 0x908c }, + [GPU_2_CC_FAST_HUB_BCR] =3D { 0x91a0 }, + [GPU_2_CC_FF_BCR] =3D { 0x91c0 }, + [GPU_2_CC_GFX3D_AON_BCR] =3D { 0x9118 }, + [GPU_2_CC_GMU_BCR] =3D { 0x9170 }, + [GPU_2_CC_GX_BCR] =3D { 0x9030 }, + [GPU_2_CC_XO_BCR] =3D { 0x9000 }, +}; + +static struct clk_alpha_pll *gpu_2_cc_nord_plls[] =3D { + &gpu_2_cc_pll0, + &gpu_2_cc_pll1, +}; + +static const u32 gpu_2_cc_nord_critical_cbcrs[] =3D { + 0x9004, /* GPU_2_CC_CXO_AON_CLK */ + 0x900c, /* GPU_2_CC_DEMET_CLK */ +}; + +static const struct regmap_config gpu_2_cc_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9ff0, + .fast_io =3D true, +}; + +static const struct qcom_cc_driver_data gpu_2_cc_nord_driver_data =3D { + .alpha_plls =3D gpu_2_cc_nord_plls, + .num_alpha_plls =3D ARRAY_SIZE(gpu_2_cc_nord_plls), + .clk_cbcrs =3D gpu_2_cc_nord_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gpu_2_cc_nord_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_2_cc_nord_desc =3D { + .config =3D &gpu_2_cc_nord_regmap_config, + .clks =3D gpu_2_cc_nord_clocks, + .num_clks =3D ARRAY_SIZE(gpu_2_cc_nord_clocks), + .resets =3D gpu_2_cc_nord_resets, + .num_resets =3D ARRAY_SIZE(gpu_2_cc_nord_resets), + .gdscs =3D gpu_2_cc_nord_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_2_cc_nord_gdscs), + .use_rpm =3D true, + .driver_data =3D &gpu_2_cc_nord_driver_data, +}; + +static const struct of_device_id gpu_2_cc_nord_match_table[] =3D { + { .compatible =3D "qcom,nord-gpu2cc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_2_cc_nord_match_table); + +static int gpu_2_cc_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_2_cc_nord_desc); +} + +static struct platform_driver gpu_2_cc_nord_driver =3D { + .probe =3D gpu_2_cc_nord_probe, + .driver =3D { + .name =3D "gpu2cc-nord", + .of_match_table =3D gpu_2_cc_nord_match_table, + }, +}; + +module_platform_driver(gpu_2_cc_nord_driver); + +MODULE_DESCRIPTION("QTI GPU2CC Nord Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/gpucc-nord.c b/drivers/clk/qcom/gpucc-nord.c new file mode 100644 index 0000000000000000000000000000000000000000..f37bc32e80ff66915108c241fc0= e46b2e8a5f8bb --- /dev/null +++ b/drivers/clk/qcom/gpucc-nord.c @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GPLL0_OUT_MAIN, + DT_GPLL0_OUT_MAIN_DIV, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static const struct pll_vco lucid_ole_vco[] =3D { + { 249600000, 2300000000, 0 }, +}; + +/* 936.0 MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll0_config =3D { + .l =3D 0x30, + .alpha =3D 0xc000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll gpu_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &gpu_cc_pll0_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1250.0 MHz Configuration */ +static const struct alpha_pll_config gpu_cc_pll1_config =3D { + .l =3D 0x41, + .alpha =3D 0x1aaa, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00182261, + .config_ctl_hi1_val =3D 0x82aa299c, + .test_ctl_val =3D 0x00000000, + .test_ctl_hi_val =3D 0x00000003, + .test_ctl_hi1_val =3D 0x00009000, + .test_ctl_hi2_val =3D 0x00000034, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00400005, +}; + +static struct clk_alpha_pll gpu_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &gpu_cc_pll1_config, + .vco_table =3D lucid_ole_vco, + .num_vco =3D ARRAY_SIZE(lucid_ole_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll0.clkr.hw }, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct parent_map gpu_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpu_cc_pll1.clkr.hw }, + { .index =3D DT_GPLL0_OUT_MAIN }, + { .index =3D DT_GPLL0_OUT_MAIN_DIV }, +}; + +static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_ff_clk_src =3D { + .cmd_rcgr =3D 0x93d4, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_0, + .freq_tbl =3D ftbl_gpu_cc_ff_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_ff_clk_src", + .parent_data =3D gpu_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] =3D { + F(416666667, P_GPU_CC_PLL1_OUT_MAIN, 3, 0, 0), + F(625000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src =3D { + .cmd_rcgr =3D 0x92b8, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_1, + .freq_tbl =3D ftbl_gpu_cc_gmu_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gmu_clk_src", + .parent_data =3D gpu_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] =3D { + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src =3D { + .cmd_rcgr =3D 0x938c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gpu_cc_parent_map_2, + .freq_tbl =3D ftbl_gpu_cc_hub_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_clk_src", + .parent_data =3D gpu_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gpu_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_div_clk_src =3D { + .reg =3D 0x93cc, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_div_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_acd_gfx3d_clk =3D { + .halt_reg =3D 0x92a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x92a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_acd_gfx3d_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_acmu_clk =3D { + .halt_reg =3D 0x9294, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9294, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_acmu_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk =3D { + .halt_reg =3D 0x9150, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x9150, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk =3D { + .halt_reg =3D 0x9154, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9154, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_crc_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_div_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_accu_shift_clk =3D { + .halt_reg =3D 0x91a4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x91a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_accu_shift_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_ff_clk =3D { + .halt_reg =3D 0x9184, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9184, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_ff_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk =3D { + .halt_reg =3D 0x916c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x916c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cx_gmu_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk =3D { + .halt_reg =3D 0x917c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x917c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_cxo_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_dpm_clk =3D { + .halt_reg =3D 0x91a8, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x91a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_dpm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_freq_measure_clk =3D { + .halt_reg =3D 0x9008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x9008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_freq_measure_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gpu_smmu_vote_clk =3D { + .halt_reg =3D 0x7000, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_gpu_smmu_vote_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk =3D { + .halt_reg =3D 0x9388, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9388, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_aon_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk =3D { + .halt_reg =3D 0x9180, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9180, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_hub_cx_int_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk =3D { + .halt_reg =3D 0x9188, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9188, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_memnoc_gfx_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_mnd1x_gfx3d_clk =3D { + .halt_reg =3D 0x92ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x92ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_mnd1x_gfx3d_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk =3D { + .halt_reg =3D 0x9164, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9164, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpu_cc_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cc_cx_gdsc =3D { + .gdscr =3D 0x90e8, + .gds_hw_ctrl =3D 0x9128, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gpu_cc_cx_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D VOTABLE | RETAIN_FF_ENABLE, +}; + +static struct gdsc gpu_cc_gx_gdsc =3D { + .gdscr =3D 0x905c, + .clamp_io_ctrl =3D 0x9504, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gpu_cc_gx_gdsc", + .power_on =3D gdsc_gx_do_nothing_enable, + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D CLAMP_IO | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gpu_cc_nord_clocks[] =3D { + [GPU_CC_ACD_GFX3D_CLK] =3D &gpu_cc_acd_gfx3d_clk.clkr, + [GPU_CC_ACMU_CLK] =3D &gpu_cc_acmu_clk.clkr, + [GPU_CC_AHB_CLK] =3D &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] =3D &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_ACCU_SHIFT_CLK] =3D &gpu_cc_cx_accu_shift_clk.clkr, + [GPU_CC_CX_FF_CLK] =3D &gpu_cc_cx_ff_clk.clkr, + [GPU_CC_CX_GMU_CLK] =3D &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CXO_CLK] =3D &gpu_cc_cxo_clk.clkr, + [GPU_CC_DPM_CLK] =3D &gpu_cc_dpm_clk.clkr, + [GPU_CC_FF_CLK_SRC] =3D &gpu_cc_ff_clk_src.clkr, + [GPU_CC_FREQ_MEASURE_CLK] =3D &gpu_cc_freq_measure_clk.clkr, + [GPU_CC_GMU_CLK_SRC] =3D &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GPU_SMMU_VOTE_CLK] =3D &gpu_cc_gpu_smmu_vote_clk.clkr, + [GPU_CC_HUB_AON_CLK] =3D &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] =3D &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] =3D &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_DIV_CLK_SRC] =3D &gpu_cc_hub_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] =3D &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_MND1X_GFX3D_CLK] =3D &gpu_cc_mnd1x_gfx3d_clk.clkr, + [GPU_CC_PLL0] =3D &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] =3D &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] =3D &gpu_cc_sleep_clk.clkr, +}; + +static struct gdsc *gpu_cc_nord_gdscs[] =3D { + [GPU_CC_CX_GDSC] =3D &gpu_cc_cx_gdsc, + [GPU_CC_GX_GDSC] =3D &gpu_cc_gx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_nord_resets[] =3D { + [GPU_CC_ACD_BCR] =3D { 0x92f8 }, + [GPU_CC_CB_BCR] =3D { 0x9340 }, + [GPU_CC_CX_BCR] =3D { 0x90e4 }, + [GPU_CC_FAST_HUB_BCR] =3D { 0x9384 }, + [GPU_CC_GFX3D_AON_BCR] =3D { 0x91ac }, + [GPU_CC_GX_BCR] =3D { 0x9058 }, + [GPU_CC_XO_BCR] =3D { 0x9000 }, +}; + +static struct clk_alpha_pll *gpu_cc_nord_plls[] =3D { + &gpu_cc_pll0, + &gpu_cc_pll1, +}; + +static const u32 gpu_cc_nord_critical_cbcrs[] =3D { + 0x9004, /* GPU_CC_CXO_AON_CLK */ + 0x900c, /* GPU_CC_DEMET_CLK */ +}; + +static const struct regmap_config gpu_cc_nord_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x9660, + .fast_io =3D true, +}; + +static const struct qcom_cc_driver_data gpu_cc_nord_driver_data =3D { + .alpha_plls =3D gpu_cc_nord_plls, + .num_alpha_plls =3D ARRAY_SIZE(gpu_cc_nord_plls), + .clk_cbcrs =3D gpu_cc_nord_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(gpu_cc_nord_critical_cbcrs), +}; + +static const struct qcom_cc_desc gpu_cc_nord_desc =3D { + .config =3D &gpu_cc_nord_regmap_config, + .clks =3D gpu_cc_nord_clocks, + .num_clks =3D ARRAY_SIZE(gpu_cc_nord_clocks), + .resets =3D gpu_cc_nord_resets, + .num_resets =3D ARRAY_SIZE(gpu_cc_nord_resets), + .gdscs =3D gpu_cc_nord_gdscs, + .num_gdscs =3D ARRAY_SIZE(gpu_cc_nord_gdscs), + .use_rpm =3D true, + .driver_data =3D &gpu_cc_nord_driver_data, +}; + +static const struct of_device_id gpu_cc_nord_match_table[] =3D { + { .compatible =3D "qcom,nord-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_nord_match_table); + +static int gpu_cc_nord_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gpu_cc_nord_desc); +} + +static struct platform_driver gpu_cc_nord_driver =3D { + .probe =3D gpu_cc_nord_probe, + .driver =3D { + .name =3D "gpucc-nord", + .of_match_table =3D gpu_cc_nord_match_table, + }, +}; + +module_platform_driver(gpu_cc_nord_driver); + +MODULE_DESCRIPTION("QTI GPUCC Nord Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1