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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38e9232c388sm1358096a91.6.2026.07.21.04.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2026 04:15:55 -0700 (PDT) From: Chandana Kishori Chiluveru Date: Tue, 21 Jul 2026 04:15:46 -0700 Subject: [PATCH v2] dmaengine: qcom: gpi: Fix SE ID and SE Protocol fields widths in SCRATCH_0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260721-fix_se_id_and_se_protocol_fields-v2-1-ee1d63d6c549@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAOFUX2oC/42OQQ6CMBBFr0K6tqRttA2uvIchDbRTqUGKHSAaw t1t0QO4mcxL/vw3K0GIHpCci5VEWDz6MCQQh4KYrhluQL1NTAQTkinOqPMvjaC91c1g8zbGMAU Teu089BapVY45kFyeKklSzRgh3eyKa/1lnNs7mCn35kTncQrxvf+w8Jz76cQfuoVTTuHIbdtyp mylLgGxfM5Nb8LjUaZB6m3bPqgvAI/pAAAA X-Change-ID: 20260710-fix_se_id_and_se_protocol_fields-d7f0fe616596 To: konrad.dybcio@oss.qualcomm.com, Vinod Koul , Frank Li , bjorn.andersson@oss.qualcomm.com Cc: praveen.talari@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, mukesh.savaliya@oss.qualcomm.com, Chandana Kishori Chiluveru X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784632554; l=2400; i=chandana.chiluveru@oss.qualcomm.com; s=20260716; h=from:subject:message-id; bh=NEBTq2qMO+3a3T1pVwTZ2uHZNFbfvbkcYWMWPDjDQVA=; b=Qe4keT7HCz1AgMg/XDMgDqta4qcDs6+JohgeQSgDZVnpPoKXa92NyHuS7BN8df8wZHLD1VvxS 6YXlugjjUiuAXhZoPi6NYlN6vX+eDJiLTa7nv7Udel7aV57zovLq3tR X-Developer-Key: i=chandana.chiluveru@oss.qualcomm.com; a=ed25519; pk=JOK6siShQPtXwMyPXnFlFIPPNGXclzVFIJL1EuyLmy4= X-Proofpoint-GUID: _Y_ZEEXuTOV5ki4VcfX0ztNiC_dwywwJ X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDExOCBTYWx0ZWRfX8xxoMhNwZpcI h9vdLGofdLwcpPU+9MtK0dZw4POwXaST2Tv1X7v+5IHqAwf9VYTHJWGlFT0M1zaJlg5GOA9uwYi rVUODP3QvoJX6+k0yCA7OVDf/6bNNpY= X-Authority-Analysis: v=2.4 cv=ZJjnX37b c=1 sm=1 tr=0 ts=6a5f54ed cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=bC-a23v3AAAA:8 a=EUspDBNiAAAA:8 a=ptTHJtPLR270ybZWXd8A:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 a=FO4_E8m0qiDe52t0p3_H:22 X-Proofpoint-ORIG-GUID: _Y_ZEEXuTOV5ki4VcfX0ztNiC_dwywwJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDExOCBTYWx0ZWRfX/JfgMWY0AcQt cXv+IW59GXNi/ZbNIeMYb7486uTZ6puvMai9NZlD9yTh0MHaCf4JCXQ0WKO9DmO3qn05KzYaAr5 plTSLquYPA2K3G1A9AKZVmaSpfZsP7eNJInsCqK20jvKp+q4lQavDbsc1hXxaV1eCeZHhJNaX1v wkPSNgNmchYvhHh953IL6YQXGaZ2R+6315iaPeJBODILMuxLS2CC4xD6CMreZQGcBkP6/fONfxS iw7TXARTRh3I+gmQQoHToYYi/9uIEwzazEjea15gDpy5xoV+K4C4ngjgXoOuzHEZ2CNF8hmNsKB zn3PhSfNCmbmIYYwwmIlTFLh3yOPS++eXV5dVkIO1X9ddHzXOzeFAITiU8HgH3MHX/WxGu6IzPO 49EDH2MOTnzuJarXexo6DaHPmfxLqhv4IQ5D/t1ml9K5bX7TdDti5aRxIMVVPcoU4lPYR1ZYm4Q amFjgG1Zd6yq6w6jk0Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-21_01,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210118 GPII_n_CH_k_SCRATCH_0_SEID is currently defined as GENMASK(2, 0), only 3 bits wide. Serial engine indices >=3D 8 get silently truncated by FIELD_PREP()/u32_encode_bits() when written into the scratch register, causing the GPI channel to bind to the wrong serial engine. The channel allocate command still succeeds (it doesn't require the target SE to respond), but the subsequent channel start command times out waiting for hardware to complete the handoff to the (incorrectly bound) SE, and gpi_send_cmd() returns -EIO leading to GSI usecase failures for SE8 and SE9 serial engines. Older documentation, such as the SDM845 hardware programming guide, describes the SE ID field as bits [2:0]. More recent QUP hardware documentation defines the field as bits [3:0]. Use the wider definition to match current hardware documentation while remaining compatible with existing platforms and enabling serial engine IDs greater than 7. Also update the SE Protocol field definition to match the documented register layout and keep both fields correctly packed. Fixes: 5d0c3533a19f ("dmaengine: qcom: Add GPI dma driver") Signed-off-by: Chandana Kishori Chiluveru Reviewed-by: Konrad Dybcio Reviewed-by: Mukesh Kumar Savaliya --- Changes in v2: - Updated the protocol field value properly - Link to v1: https://patch.msgid.link/20260720-fix_se_id_and_se_protocol_f= ields-v1-1-e41dbb107d97@oss.qualcomm.com --- drivers/dma/qcom/gpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index a5055a6273af..fc12cf9122f9 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -207,8 +207,8 @@ enum CNTXT_OFFS { =20 /* Scratch registers */ #define GPII_n_CH_k_SCRATCH_0_OFFS(n, k) (0x20060 + (0x4000 * (n)) + (0x80= * (k))) -#define GPII_n_CH_k_SCRATCH_0_SEID GENMASK(2, 0) -#define GPII_n_CH_k_SCRATCH_0_PROTO GENMASK(7, 4) +#define GPII_n_CH_k_SCRATCH_0_SEID GENMASK(3, 0) +#define GPII_n_CH_k_SCRATCH_0_PROTO GENMASK(8, 4) #define GPII_n_CH_k_SCRATCH_0_PAIR GENMASK(20, 16) #define GPII_n_CH_k_SCRATCH_0(pair, proto, seid) \ (FIELD_PREP(GPII_n_CH_k_SCRATCH_0_PAIR, pair) | \ --- base-commit: 34cf6dafc47441dfb6b356a095b89c3585a93714 change-id: 20260710-fix_se_id_and_se_protocol_fields-d7f0fe616596 Best regards, -- =20 Chandana Kishori Chiluveru