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Add PCIe controller and PHY nodes for both instances, and update the GCC clock references to use the newly added PHY nodes instead of placeholder zeros. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/eliza.dtsi | 412 ++++++++++++++++++++++++++++++++= +++- 1 file changed, 410 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom= /eliza.dtsi index 977de44b816e..b4958954de73 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -640,8 +640,8 @@ gcc: clock-controller@100000 { =20 clocks =3D <&bi_tcxo_div2>, <&sleep_clk>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -1786,6 +1786,368 @@ mmss_noc: interconnect@1780000 { #interconnect-cells =3D <2>; }; =20 + pcie0: pcie@1c00000 { + device_type =3D "pci"; + compatible =3D "qcom,eliza-pcie", "qcom,pcie-sm8550"; + reg =3D <0 0x01c00000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, + <0x02000000 0 0x40300000 0 0x40300000 0 0x3d00000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr", + "cnoc_sf_axi"; + + resets =3D <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + interconnects =3D <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + power-domains =3D <&gcc GCC_PCIE_0_GDSC>; + + operating-points-v2 =3D <&pcie0_opp_table>; + + iommu-map =3D <0 &apps_smmu 0x1480 0x1>, + <0x100 &apps_smmu 0x1481 0x1>; + + interrupt-map =3D <0 0 0 1 &intc 0 0 0 564 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 565 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 566 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 567 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 0x7>; + #interrupt-cells =3D <1>; + + linux,pci-domain =3D <0>; + num-lanes =3D <1>; + bus-range =3D <0 0xff>; + + dma-coherent; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + + pcie0_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* 2.5 GT/s x1 */ + opp-2500000-1 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + opp-level =3D <1>; + }; + + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <2>; + }; + + /* 8 GT/s x1 */ + opp-8000000-3 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + opp-level =3D <3>; + }; + + }; + + pcie0port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + phys =3D <&pcie0_phy>; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible =3D "qcom,eliza-qmp-gen3x1-pcie-phy"; + reg =3D <0 0x01c06000 0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_DIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks =3D <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_0_PHY_BCR>, + <&gcc GCC_PCIE_0_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr"; + + power-domains =3D <&gcc GCC_PCIE_0_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie0_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie1: pcie@1c08000 { + device_type =3D "pci"; + compatible =3D "qcom,eliza-pcie", "qcom,pcie-sm8550"; + reg =3D <0 0x01c08000 0 0x3000>, + <0 0x44000000 0 0xf1d>, + <0 0x44000f20 0 0xa8>, + <0 0x44001000 0 0x1000>, + <0 0x44100000 0 0x100000>, + <0 0x01c0b000 0 0x1000>; + reg-names =3D "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x44200000 0x0 0x100000>, + <0x02000000 0x0 0x44300000 0x0 0x44300000 0x0 0x3d00000>, + <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names =3D "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr", + "cnoc_sf_axi"; + + resets =3D <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names =3D "pci", + "link_down"; + + interconnects =3D <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "pcie-mem", + "cpu-pcie"; + + power-domains =3D <&gcc GCC_PCIE_1_GDSC>; + + operating-points-v2 =3D <&pcie1_opp_table>; + + iommu-map =3D <0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask =3D <0 0 0 0x7>; + #interrupt-cells =3D <1>; + + linux,pci-domain =3D <1>; + num-lanes =3D <2>; + bus-range =3D <0 0xff>; + + dma-coherent; + + pinctrl-0 =3D <&pcie1_default_state>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + + pcie1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + /* 2.5 GT/s x1 */ + opp-2500000-1 { + opp-hz =3D /bits/ 64 <2500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <250000 1>; + opp-level =3D <1>; + }; + + /* 2.5 GT/s x2 */ + opp-5000000-1 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <1>; + }; + + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz =3D /bits/ 64 <5000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <500000 1>; + opp-level =3D <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { + opp-hz =3D /bits/ 64 <10000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1000000 1>; + opp-level =3D <2>; + }; + + /* 8 GT/s x1 */ + opp-8000000-3 { + opp-hz =3D /bits/ 64 <8000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <984500 1>; + opp-level =3D <3>; + }; + + /* 8 GT/s x2 */ + opp-16000000-3 { + opp-hz =3D /bits/ 64 <16000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + opp-peak-kBps =3D <1969000 1>; + opp-level =3D <3>; + }; + + }; + pcie1port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + phys =3D <&pcie1_phy>; + }; + }; + + pcie1_phy: phy@1c0e000 { + compatible =3D "qcom,eliza-qmp-gen3x2-pcie-phy"; + reg =3D <0 0x01c0e000 0 0x2000>; + + clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_DIV2_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks =3D <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates =3D <100000000>; + + resets =3D <&gcc GCC_PCIE_1_PHY_BCR>, + <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; + reset-names =3D "phy", + "phy_nocsr"; + + power-domains =3D <&gcc GCC_PCIE_1_PHY_GDSC>; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie1_pipe_clk"; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + ufs_mem_phy: phy@1d80000 { compatible =3D "qcom,eliza-qmp-ufs-phy", "qcom,sm8650-qmp-ufs-phy"; @@ -2843,6 +3205,52 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 184>; wakeup-parent =3D <&pdc>; =20 + pcie0_default_state: pcie0-default-state { + perst-pins { + pins =3D "gpio78"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + clkreq-pins { + pins =3D "gpio80"; + function =3D "pcie0_clk_req_n"; + drive-strength =3D <2>; + bias-pull-up; + }; + + wake-pins { + pins =3D "gpio114"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins =3D "gpio54"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + clkreq-pins { + pins =3D "gpio52"; + function =3D "pcie1_clk_req_n"; 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Enable the PCIe0 root port and its QMP PHY with the necessary RPMH regulator supplies. The M.2 slot's 3.3V supply rail is GPIO-controlled via a TCA9538 I/O expander on I2C4. The M.2 E key slot hosts a WLAN card connected over PCIe and a Bluetooth device connected over UART. Model the connector using the pcie-m2-e-connector binding, wiring the PCIe root port and UART5 for the respective interfaces. Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/eliza-evk.dtsi | 116 ++++++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/eliza.dtsi | 1 + 2 files changed, 117 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi b/arch/arm64/boot/dts/= qcom/eliza-evk.dtsi index e47b24f8b827..6d76715ccffb 100644 --- a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi @@ -11,6 +11,92 @@ aliases { chosen { stdout-path =3D "serial0:115200n8"; }; + + vreg_pcie_m_3p3: regulator-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vreg_3p3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&gpio_expander1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + connector-0 { + compatible =3D "pcie-m2-e-connector"; + vpcie3v3-supply =3D <&vreg_pcie_m_3p3>; + w-disable1-gpios =3D <&tlmm 35 GPIO_ACTIVE_LOW>; + w-disable2-gpios =3D <&pm8550vs_g_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&m2_w_disable1>, <&m2_w_disable2>; + pinctrl-names =3D "default"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + m2_e_pcie_ep: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&pcieport0_ep>; + }; + }; + + port@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + m2_e_uart_ep: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&uart5_ep>; + }; + }; + }; + }; +}; + +&i2c4 { + pinctrl-0 =3D <&qup_i2c4_data_clk>; + pinctrl-names =3D "default"; + + clock-frequency =3D <400000>; + + status =3D "okay"; + + gpio_expander1: gpio@3c { + compatible =3D "ti,tca9538"; + #gpio-cells =3D <2>; + gpio-controller; + reg =3D <0x3c>; + }; +}; + +&pcie0 { + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1k>; + vdda-pll-supply =3D <&vreg_l3k>; + + status =3D "okay"; +}; + +&pcie0port0 { + wake-gpios =3D <&tlmm 114 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&tlmm 78 GPIO_ACTIVE_LOW>; + + port { + pcieport0_ep: endpoint { + remote-endpoint =3D <&m2_e_pcie_ep>; + }; + }; }; =20 &uart13 { @@ -18,3 +104,33 @@ &uart13 { =20 status =3D "okay"; }; + +&uart5 { + status =3D "okay"; + + port { + uart5_ep: endpoint { + remote-endpoint =3D <&m2_e_uart_ep>; + }; + }; +}; + +&pm8550vs_g_gpios { + m2_w_disable2: m2-w-disable2-state { + pins =3D "gpio4"; + function =3D "normal"; + input-disable; + output-enable; + bias-disable; + power-source =3D <2>; + }; +}; + +&tlmm { + m2_w_disable1: m2-w-disable1-state { + pins =3D "gpio35"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom= /eliza.dtsi index b4958954de73..59b3cf7f168d 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -1909,6 +1909,7 @@ opp-8000000-3 { }; =20 pcie0port0: pcie@0 { + compatible =3D "pciclass,0604"; device_type =3D "pci"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; 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Enable PCIe1 and its QMP PHY nodes. TC9563 uses I2C (at address 0x77 on I2C4) for its management interface. Override the base iommu-map with the expanded set covering all the switch's downstream ports (0x1400-0x1408 SID range). The TC9563 RESX# and PERST# are OR-ed internally to assert reset on the switch. Use TC9563 RESX# pin via a TLMM GPIO and skip wiring PERST# from the PCIe controller. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/eliza-evk.dtsi | 113 ++++++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/eliza.dtsi | 1 + 2 files changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi b/arch/arm64/boot/dts/= qcom/eliza-evk.dtsi index 6d76715ccffb..fb44e7a349a5 100644 --- a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi @@ -12,6 +12,26 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 + vreg_0p9: regulator-0v9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_0P9"; + + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VREG_1P8"; + + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + vreg_pcie_m_3p3: regulator-3p3 { compatible =3D "regulator-fixed"; =20 @@ -99,6 +119,99 @@ pcieport0_ep: endpoint { }; }; =20 +&pcie1 { + iommu-map =3D <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>, + <0x208 &apps_smmu 0x1402 0x1>, + <0x210 &apps_smmu 0x1403 0x1>, + <0x218 &apps_smmu 0x1404 0x1>, + <0x300 &apps_smmu 0x1405 0x1>, + <0x400 &apps_smmu 0x1406 0x1>, + <0x500 &apps_smmu 0x1407 0x1>, + <0x501 &apps_smmu 0x1408 0x1>; + + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l1k>; + vdda-pll-supply =3D <&vreg_l3k>; + + status =3D "okay"; +}; + +&pcie1port0 { + wake-gpios =3D <&tlmm 53 GPIO_ACTIVE_LOW>; + /* Same GPIO is used for both PERST# and resx-gpio */ + + tc9563: pcie@0,0 { + compatible =3D "pci1179,0623"; + reg =3D <0x10000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x2 0xff>; + + vddc-supply =3D <&vreg_0p9>; + vdd18-supply =3D <&vreg_1p8>; + vdd09-supply =3D <&vreg_0p9>; + vddio1-supply =3D <&vreg_1p8>; + vddio2-supply =3D <&vreg_1p8>; + vddio18-supply =3D <&vreg_1p8>; + + i2c-parent =3D <&i2c4 0x77>; + + resx-gpios =3D <&tlmm 54 GPIO_ACTIVE_LOW>; + + pcie@1,0 { + reg =3D <0x20800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x3 0xff>; + }; + + pcie@2,0 { + reg =3D <0x21000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + device_type =3D "pci"; + ranges; + bus-range =3D <0x4 0xff>; + }; + + pcie@3,0 { + reg =3D <0x21800 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + bus-range =3D <0x5 0xff>; + + pci@0,0 { + reg =3D <0x50000 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + + pci@0,1 { + reg =3D <0x50100 0x0 0x0 0x0 0x0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + ranges; + }; + }; + }; +}; + &uart13 { compatible =3D "qcom,geni-debug-uart"; =20 diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom= /eliza.dtsi index 59b3cf7f168d..cdf5decfef48 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -2103,6 +2103,7 @@ opp-16000000-3 { =20 }; pcie1port0: pcie@0 { + compatible =3D "pciclass,0604"; device_type =3D "pci"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; --=20 2.34.1