From nobody Sat Jul 25 00:56:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD96737756E; Tue, 21 Jul 2026 10:35:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784630122; cv=none; b=pTth1u37Xm7zR+U+mTsMsJyQOgHzx4hYpIRBW69Z5No8CA5M0CYJ0O6Ht8LLhef3MH5hf48k0PycSP0F3/PISOfvNffTLMGwPD3xIHlP7R44/gmg7CK3K+A+3CbjVVROBPWU45VcY1hIZ9l4OEx66Ok0PtUR2ltG8GWVQfgyyOs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784630122; c=relaxed/simple; bh=JV00sjmhquXboKON+JjhU41ZdESA0A3y8urFRlEdNU8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dfjlLZzuU2vJIdneLiXK2/vz/+Erih7O+3Y+EcnJZbYjXvv0p6RS29NUSHxw98P7PUO0KfXelN2iqETJ+EGZCEeU8fLA+ufkoD32CBGvSnjx45SkRCaFyyAiDbGcj03ZWN5+BHf5Lr8rFMUcJUrbwt2iQVzHG7jUkq81MPSG9cI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NiO41nuW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NiO41nuW" Received: by smtp.kernel.org (Postfix) with ESMTPS id 748BAC2BCB8; Tue, 21 Jul 2026 10:35:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784630122; bh=JV00sjmhquXboKON+JjhU41ZdESA0A3y8urFRlEdNU8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NiO41nuWWBZngmxJJIEebm1oddpO3QqlHSYM1sBxdafID57RgEdL4vx8h1Ffspx4W ZZoWLk0b7AjMEn/YQuW07XtbfnF2yES6DzD0Or/Ors3QLMNnbBy0ZUaRu7XaTiTJsv eeV4hehdbB0BdgVGcS+Vud8YyKoL0KYa4Eh4jZhR07SgfC1cKKGTBsRMKkd2460mJr rdYv0nExbAhhG9XLt70W71JkLH+2f/gUIRWcQUVxFknE1V4QkdNbGqahuRWKUeRjFe T78uAU6bMiyX9GX6QBJjLhD0Zs7RhpVuwu2+pF9vo7ceaQCWoEJk1gl4q9/8WQ2zy4 RnHRKX6S1g8gw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 638CEC4451C; Tue, 21 Jul 2026 10:35:22 +0000 (UTC) From: Jason Yang via B4 Relay Date: Tue, 21 Jul 2026 18:35:19 +0800 Subject: [PATCH 1/4] dt-bindings: phy: rockchip,rk3588-mipi-dcphy: support per-direction phys Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260721-dcphy-rx-v1-v1-1-4fc83c0ccac9@gmail.com> References: <20260721-dcphy-rx-v1-v1-0-4fc83c0ccac9@gmail.com> In-Reply-To: <20260721-dcphy-rx-v1-v1-0-4fc83c0ccac9@gmail.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Guochun Huang , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jason Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784630121; l=3235; i=jason98166@gmail.com; s=20260721; h=from:subject:message-id; bh=qKIkMZo6/4E4nSFrHbQ73C4ZiCIq+4PFw3ZZsww73IM=; b=geNFFEuGY+1qt+RJXr7yo9Fj8vo+15a4R78etc9erRBw+z48QFkH6TiN426oNaMWSYTA7yfvZ Xkdya/bcYdoA0mT85vIjQ0ZF7sAkM2soLtzXNt1CYE+0YSmOEbRjbGo X-Developer-Key: i=jason98166@gmail.com; a=ed25519; pk=xQmD001Q/ooHl39PxyQtusbUQmgbOsSfpFryRVWZ/k4= X-Endpoint-Received: by B4 Relay for jason98166@gmail.com/20260721 with auth_id=887 X-Original-From: Jason Yang Reply-To: jason98166@gmail.com From: Jason Yang The Samsung MIPI D-/C-PHY block on RK3588 drives a MIPI DSI transmitter and, on the same PHY, can receive a MIPI CSI camera. Describing both as independent consumers of one PHY requires the direction to be expressed in the devicetree. Allow "#phy-cells" to be 1 or 2. The existing single-cell form still selects the PHY type and refers to the transmitter, so shipped DSI device trees stay valid. A second cell adds the direction, letting a DSI (TX) and a CSI (RX) reference the same PHY node as separate consumers. Add include/dt-bindings/phy/phy-rockchip-samsung-dcphy.h for the RK_DCPHY_DIR_TX and RK_DCPHY_DIR_RX direction constants. Signed-off-by: Jason Yang Assisted-by: Claude:claude-opus-4-8 --- .../bindings/phy/rockchip,rk3588-mipi-dcphy.yaml | 22 ++++++++++++++++--= ---- .../dt-bindings/phy/phy-rockchip-samsung-dcphy.h | 13 +++++++++++++ 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcp= hy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.= yaml index c8ff5ba22a86..53d695137566 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-mipi-dcphy.yaml @@ -20,12 +20,22 @@ properties: maxItems: 1 =20 "#phy-cells": - const: 1 + enum: [1, 2] description: | - Argument is mode to operate in. Supported modes are: - - PHY_TYPE_DPHY - - PHY_TYPE_CPHY - See include/dt-bindings/phy/phy.h for constants. + A single cell selects the PHY type and always refers to the + transmitter (DSI) direction. It is kept for backwards compatibility + with existing device trees: + - + - + + Two cells select the PHY type and the direction, so that the + transmitter (DSI) and the receiver (CSI) can be described as + independent consumers of the same PHY: + - + - + + See include/dt-bindings/phy/phy.h and + include/dt-bindings/phy/phy-rockchip-samsung-dcphy.h for constants. =20 clocks: maxItems: 2 @@ -82,6 +92,6 @@ examples: <&cru SRST_S_MIPI_DCPHY0>; reset-names =3D "m_phy", "apb", "grf", "s_phy"; rockchip,grf =3D <&mipidcphy0_grf>; - #phy-cells =3D <1>; + #phy-cells =3D <2>; }; }; diff --git a/include/dt-bindings/phy/phy-rockchip-samsung-dcphy.h b/include= /dt-bindings/phy/phy-rockchip-samsung-dcphy.h new file mode 100644 index 000000000000..60f6630f58b3 --- /dev/null +++ b/include/dt-bindings/phy/phy-rockchip-samsung-dcphy.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2026 Jason Yang + */ + +#ifndef _DT_BINDINGS_PHY_ROCKCHIP_SAMSUNG_DCPHY_H +#define _DT_BINDINGS_PHY_ROCKCHIP_SAMSUNG_DCPHY_H + +/* Direction of a Rockchip Samsung MIPI D-/C-PHY combo block */ +#define RK_DCPHY_DIR_TX 0 +#define RK_DCPHY_DIR_RX 1 + +#endif /* _DT_BINDINGS_PHY_ROCKCHIP_SAMSUNG_DCPHY_H */ --=20 2.43.0 From nobody Sat Jul 25 00:56:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3E6A37B030; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lcXaowgV" Received: by smtp.kernel.org (Postfix) with ESMTPS id 84B51C2BCFB; Tue, 21 Jul 2026 10:35:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784630122; bh=AhRTLnCcwo6Mxg5rxROPb+PhKIVmCT4avAH9ngSVIfg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lcXaowgVVDEmx1GchFtINXI6E6M7xDabymranzZPjF81F0I4h+2PUyfn81YjInh6r IwkGKjajFdomMOsOiCY0reCctIelfPAPNV0WagBV9Fr1dJ5ai5x1fUufMzP7GhPJIn FOy9xEXkP6CvqnnqfUIorRyJRJv5UZv+AIzDb2LAEN2CjJUyeFIT6IX0n5Bl0UkowH KfiAFPFwpZGkdMTR6GimFawNKv5wHfhNJ5HF8lxNhb5kDqh+qm1pbQZP7reN70nydY IQ6y/faq1PvGBMvNYF74fVOmrQPWfLmM0y80C8860ENPYV6FtuyoK0/Wd/PeZBhNei KZ9JD5ahiVkiA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71E5CC44529; Tue, 21 Jul 2026 10:35:22 +0000 (UTC) From: Jason Yang via B4 Relay Date: Tue, 21 Jul 2026 18:35:20 +0800 Subject: [PATCH 2/4] phy: rockchip-samsung-dcphy: factor MIPI D-PHY power on/off into helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260721-dcphy-rx-v1-v1-2-4fc83c0ccac9@gmail.com> References: <20260721-dcphy-rx-v1-v1-0-4fc83c0ccac9@gmail.com> In-Reply-To: <20260721-dcphy-rx-v1-v1-0-4fc83c0ccac9@gmail.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Guochun Huang , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jason Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784630121; l=2365; i=jason98166@gmail.com; s=20260721; h=from:subject:message-id; bh=4GcNX0JppuDhi+PdI+Mfy3wrN0LmkfCuqWcPPnXARtM=; b=WyxM8NMEq4WZ7Ic0mfu0q9LQ7+49eB9EWcUg16azkFqHpHAFyZA/o9RvVzdZ+BT8wBxYDPhV+ oG2R5dmESqPClHCersw+Wwrvfe7joPZxI6oS5eJSMXh5jKL235KWGVR X-Developer-Key: i=jason98166@gmail.com; a=ed25519; pk=xQmD001Q/ooHl39PxyQtusbUQmgbOsSfpFryRVWZ/k4= X-Endpoint-Received: by B4 Relay for jason98166@gmail.com/20260721 with auth_id=887 X-Original-From: Jason Yang Reply-To: jason98166@gmail.com From: Jason Yang To prepare for adding a receiver (CSI) direction next to the existing transmitter (DSI) one, rename the transmitter power-on helper to samsung_mipi_dphy_tx_power_on() and gather its teardown into a new samsung_mipi_dphy_tx_power_off(), so both directions can later be powered on and off through symmetric helpers. No functional change intended. Signed-off-by: Jason Yang Assisted-by: Claude:claude-opus-4-8 --- drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-dcphy.c index cbd780556da8..d0d77421bd4b 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c @@ -1332,7 +1332,7 @@ samsung_mipi_dphy_data_lane_timing_init(struct samsun= g_mipi_dcphy *samsung) regmap_write(samsung->regmap, DPHY_MD3_TIME_CON4, 0x1f4); } =20 -static int samsung_mipi_dphy_power_on(struct samsung_mipi_dcphy *samsung) +static int samsung_mipi_dphy_tx_power_on(struct samsung_mipi_dcphy *samsun= g) { int ret; =20 @@ -1358,6 +1358,14 @@ static int samsung_mipi_dphy_power_on(struct samsung= _mipi_dcphy *samsung) return 0; } =20 +static int samsung_mipi_dphy_tx_power_off(struct samsung_mipi_dcphy *samsu= ng) +{ + samsung_mipi_dphy_lane_disable(samsung); + samsung_mipi_dcphy_pll_disable(samsung); + + return 0; +} + static int samsung_mipi_dcphy_power_on(struct phy *phy) { struct samsung_mipi_dcphy *samsung =3D phy_get_drvdata(phy); @@ -1368,7 +1376,7 @@ static int samsung_mipi_dcphy_power_on(struct phy *ph= y) =20 switch (samsung->type) { case PHY_TYPE_DPHY: - return samsung_mipi_dphy_power_on(samsung); + return samsung_mipi_dphy_tx_power_on(samsung); default: /* CPHY part to be implemented later */ return -EOPNOTSUPP; @@ -1383,16 +1391,11 @@ static int samsung_mipi_dcphy_power_off(struct phy = *phy) =20 switch (samsung->type) { case PHY_TYPE_DPHY: - samsung_mipi_dphy_lane_disable(samsung); - break; + return samsung_mipi_dphy_tx_power_off(samsung); default: /* CPHY part to be implemented later */ return -EOPNOTSUPP; } - - samsung_mipi_dcphy_pll_disable(samsung); - - return 0; } =20 static int --=20 2.43.0 From nobody Sat Jul 25 00:56:33 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3CE43783D8; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260721-dcphy-rx-v1-v1-3-4fc83c0ccac9@gmail.com> References: <20260721-dcphy-rx-v1-v1-0-4fc83c0ccac9@gmail.com> In-Reply-To: <20260721-dcphy-rx-v1-v1-0-4fc83c0ccac9@gmail.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Guochun Huang , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jason Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784630121; l=9415; i=jason98166@gmail.com; s=20260721; h=from:subject:message-id; bh=bDL/0FuA2Gt8MlOhFoc43fxl634cUhUTxUySC20Qynk=; b=/6jOtuu5/ccM9L5VVyQBxlYwc1HFFD9m5G5oqIDp5jY7T4wrS+BftOZ0YCtnp9Zb9+dq9mf6y QJYsvp3TN9bC5PhoJn4qWsfmBxPkhGdJQw6xj2xwjtLCWmZZ+CnNlg/ X-Developer-Key: i=jason98166@gmail.com; a=ed25519; pk=xQmD001Q/ooHl39PxyQtusbUQmgbOsSfpFryRVWZ/k4= X-Endpoint-Received: by B4 Relay for jason98166@gmail.com/20260721 with auth_id=887 X-Original-From: Jason Yang Reply-To: jason98166@gmail.com From: Jason Yang The DC-PHY drives a MIPI DSI transmitter and a MIPI CSI receiver, and on RK3588 both can be wired to the same PHY as independent consumers. The PHY core reference-counts power_on() per struct phy, so a single struct phy cannot bring the two directions up independently. Register one struct phy per direction and move the per-direction state (direction and PHY type) into its own driver data. of_xlate() accepts the legacy single cell as the transmitter and an optional second cell that selects the direction, so existing single-cell DSI device trees keep resolving to the transmitter. The shared BIAS block must be programmed only once for the whole block. Whichever direction powers on first enables it, checking the peer phy's power_count under a per-provider mutex so that powering one direction on does not disturb an already running one. The APB reset is issued on the transmitter bring-up path. The receiver bring-up itself is added in a later change. Signed-off-by: Jason Yang Assisted-by: Claude:claude-opus-4-8 --- drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c | 133 +++++++++++++++---= ---- 1 file changed, 95 insertions(+), 38 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-dcphy.c index d0d77421bd4b..0248424929bb 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c @@ -5,6 +5,7 @@ * Guochun Huang */ =20 +#include #include #include #include @@ -13,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -280,6 +282,16 @@ struct samsung_mipi_dcphy_plat_data { u32 dphy_tx_max_lane_kbps; }; =20 +struct samsung_mipi_dcphy; + +/* One PHY per direction: transmitter (DSI) and receiver (CSI). */ +struct samsung_mipi_dcphy_dir { + struct phy *phy; + struct samsung_mipi_dcphy *parent; + u8 dir; + u8 type; +}; + struct samsung_mipi_dcphy { struct device *dev; struct clk *ref_clk; @@ -291,8 +303,9 @@ struct samsung_mipi_dcphy { struct reset_control *apb_rst; struct reset_control *grf_apb_rst; unsigned int lanes; - struct phy *phy; - u8 type; + struct samsung_mipi_dcphy_dir phys[2]; + /* Serialises the two directions' access to the shared PHY state. */ + struct mutex lock; =20 const struct samsung_mipi_dcphy_plat_data *pdata; struct { @@ -1332,13 +1345,26 @@ samsung_mipi_dphy_data_lane_timing_init(struct sams= ung_mipi_dcphy *samsung) regmap_write(samsung->regmap, DPHY_MD3_TIME_CON4, 0x1f4); } =20 -static int samsung_mipi_dphy_tx_power_on(struct samsung_mipi_dcphy *samsun= g) +static int samsung_mipi_dphy_tx_power_on(struct samsung_mipi_dcphy *samsun= g, + struct phy *peer) { + bool first =3D peer->power_count =3D=3D 0; int ret; =20 + /* + * The shared BIAS block is brought up by whichever direction powers + * on first, leaving an already active peer undisturbed. + */ + if (first) { + reset_control_assert(samsung->apb_rst); + udelay(1); + reset_control_deassert(samsung->apb_rst); + } + reset_control_assert(samsung->m_phy_rst); =20 - samsung_mipi_dcphy_bias_block_enable(samsung); + if (first) + samsung_mipi_dcphy_bias_block_enable(samsung); samsung_mipi_dcphy_pll_configure(samsung); samsung_mipi_dphy_clk_lane_timing_init(samsung); samsung_mipi_dphy_data_lane_timing_init(samsung); @@ -1368,34 +1394,41 @@ static int samsung_mipi_dphy_tx_power_off(struct sa= msung_mipi_dcphy *samsung) =20 static int samsung_mipi_dcphy_power_on(struct phy *phy) { - struct samsung_mipi_dcphy *samsung =3D phy_get_drvdata(phy); - - reset_control_assert(samsung->apb_rst); - udelay(1); - reset_control_deassert(samsung->apb_rst); + struct samsung_mipi_dcphy_dir *pd =3D phy_get_drvdata(phy); + struct samsung_mipi_dcphy *samsung =3D pd->parent; + struct phy *peer =3D samsung->phys[!pd->dir].phy; + int ret; =20 - switch (samsung->type) { - case PHY_TYPE_DPHY: - return samsung_mipi_dphy_tx_power_on(samsung); - default: - /* CPHY part to be implemented later */ + if (pd->type !=3D PHY_TYPE_DPHY) return -EOPNOTSUPP; - } =20 - return 0; + mutex_lock(&samsung->lock); + if (pd->dir =3D=3D RK_DCPHY_DIR_RX) + ret =3D -EOPNOTSUPP; + else + ret =3D samsung_mipi_dphy_tx_power_on(samsung, peer); + mutex_unlock(&samsung->lock); + + return ret; } =20 static int samsung_mipi_dcphy_power_off(struct phy *phy) { - struct samsung_mipi_dcphy *samsung =3D phy_get_drvdata(phy); + struct samsung_mipi_dcphy_dir *pd =3D phy_get_drvdata(phy); + struct samsung_mipi_dcphy *samsung =3D pd->parent; + int ret; =20 - switch (samsung->type) { - case PHY_TYPE_DPHY: - return samsung_mipi_dphy_tx_power_off(samsung); - default: - /* CPHY part to be implemented later */ + if (pd->type !=3D PHY_TYPE_DPHY) return -EOPNOTSUPP; - } + + if (pd->dir =3D=3D RK_DCPHY_DIR_RX) + return -EOPNOTSUPP; + + mutex_lock(&samsung->lock); + ret =3D samsung_mipi_dphy_tx_power_off(samsung); + mutex_unlock(&samsung->lock); + + return ret; } =20 static int @@ -1488,11 +1521,15 @@ samsung_mipi_dcphy_pll_calc_rate(struct samsung_mip= i_dcphy *samsung, static int samsung_mipi_dcphy_configure(struct phy *phy, union phy_configure_opts *opts) { - struct samsung_mipi_dcphy *samsung =3D phy_get_drvdata(phy); + struct samsung_mipi_dcphy_dir *pd =3D phy_get_drvdata(phy); + struct samsung_mipi_dcphy *samsung =3D pd->parent; unsigned long long target_rate =3D opts->mipi_dphy.hs_clk_rate; =20 samsung->lanes =3D opts->mipi_dphy.lanes > 4 ? 4 : opts->mipi_dphy.lanes; =20 + if (pd->dir =3D=3D RK_DCPHY_DIR_RX) + return -EOPNOTSUPP; + samsung_mipi_dcphy_pll_calc_rate(samsung, target_rate); opts->mipi_dphy.hs_clk_rate =3D samsung->pll.rate; =20 @@ -1501,16 +1538,16 @@ static int samsung_mipi_dcphy_configure(struct phy = *phy, =20 static int samsung_mipi_dcphy_init(struct phy *phy) { - struct samsung_mipi_dcphy *samsung =3D phy_get_drvdata(phy); + struct samsung_mipi_dcphy_dir *pd =3D phy_get_drvdata(phy); =20 - return pm_runtime_resume_and_get(samsung->dev); + return pm_runtime_resume_and_get(pd->parent->dev); } =20 static int samsung_mipi_dcphy_exit(struct phy *phy) { - struct samsung_mipi_dcphy *samsung =3D phy_get_drvdata(phy); + struct samsung_mipi_dcphy_dir *pd =3D phy_get_drvdata(phy); =20 - pm_runtime_put(samsung->dev); + pm_runtime_put(pd->parent->dev); =20 return 0; } @@ -1536,19 +1573,29 @@ static struct phy *samsung_mipi_dcphy_xlate(struct = device *dev, const struct of_phandle_args *args) { struct samsung_mipi_dcphy *samsung =3D dev_get_drvdata(dev); + struct samsung_mipi_dcphy_dir *pd; + u8 dir =3D RK_DCPHY_DIR_TX; =20 - if (args->args_count !=3D 1) { + if (args->args_count < 1 || args->args_count > 2) { dev_err(dev, "invalid number of arguments\n"); return ERR_PTR(-EINVAL); } =20 - if (samsung->type !=3D PHY_NONE && samsung->type !=3D args->args[0]) - dev_warn(dev, "phy type select %d overwriting type %d\n", - args->args[0], samsung->type); + if (args->args_count =3D=3D 2) { + if (args->args[1] > RK_DCPHY_DIR_RX) { + dev_err(dev, "invalid direction %u\n", args->args[1]); + return ERR_PTR(-EINVAL); + } + dir =3D args->args[1]; + } =20 - samsung->type =3D args->args[0]; + pd =3D &samsung->phys[dir]; + if (pd->type !=3D PHY_NONE && pd->type !=3D args->args[0]) + dev_warn(dev, "phy type select %u overwriting type %u\n", + args->args[0], pd->type); + pd->type =3D args->args[0]; =20 - return samsung->phy; + return pd->phy; } =20 static int samsung_mipi_dcphy_probe(struct platform_device *pdev) @@ -1559,6 +1606,7 @@ static int samsung_mipi_dcphy_probe(struct platform_d= evice *pdev) struct phy_provider *phy_provider; struct resource *res; void __iomem *regs; + unsigned int i; int ret; =20 samsung =3D devm_kzalloc(dev, sizeof(*samsung), GFP_KERNEL); @@ -1568,6 +1616,7 @@ static int samsung_mipi_dcphy_probe(struct platform_d= evice *pdev) samsung->dev =3D dev; samsung->pdata =3D device_get_match_data(dev); platform_set_drvdata(pdev, samsung); + mutex_init(&samsung->lock); =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); regs =3D devm_ioremap_resource(dev, res); @@ -1613,11 +1662,19 @@ static int samsung_mipi_dcphy_probe(struct platform= _device *pdev) return dev_err_probe(dev, PTR_ERR(samsung->grf_apb_rst), "Failed to get system grf_apb_rst control\n"); =20 - samsung->phy =3D devm_phy_create(dev, NULL, &samsung_mipi_dcphy_ops); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260721-dcphy-rx-v1-v1-4-4fc83c0ccac9@gmail.com> References: <20260721-dcphy-rx-v1-v1-0-4fc83c0ccac9@gmail.com> In-Reply-To: <20260721-dcphy-rx-v1-v1-0-4fc83c0ccac9@gmail.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Guochun Huang , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Jason Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784630121; l=15752; i=jason98166@gmail.com; s=20260721; h=from:subject:message-id; bh=4heJCCdi5iavR7+5kCcKRUgdSrhQYNmzwtayiKxNNeQ=; b=Whd7z5N9jhuhrDzDRaCWDmdXv/nJ+H3Du0ihKyPIfJCE9d6FBPEQwd4PQ49IVpxMPjOXK9+Wg +5gpxLyUNWwDK6M8X3+yciIMY1RixOayAFnJvL9y1Unw6F2U5vQ+EzY X-Developer-Key: i=jason98166@gmail.com; a=ed25519; pk=xQmD001Q/ooHl39PxyQtusbUQmgbOsSfpFryRVWZ/k4= X-Endpoint-Received: by B4 Relay for jason98166@gmail.com/20260721 with auth_id=887 X-Original-From: Jason Yang Reply-To: jason98166@gmail.com From: Jason Yang Implement the receiver (CSI) direction of the D-PHY. Add the RX register layout and the HS-frequency settle table, and hook the receiver bring-up and teardown into the per-direction power_on(), power_off() and configure() paths, all serialized on the provider mutex alongside the transmitter. Only the D-PHY receiver is implemented, with fixed RK3588 tuning defaults. The RX register layout and field definitions follow the RK3588 TRM (section 22.4); what the TRM does not publish are the per-data-rate HS settle values (it points to a separate timing-table supplement and gives only a single example point) and the analog tuning values, both of which are taken from the Rockchip vendor kernel. The PLL is left untouched on the receive path: the sensor supplies the link clock, and the TRM start-up sequence (figure 22-8) allows the PLL sequence to be skipped when only the receiver (slave) lanes are used. configure() only records the incoming rate so the settle table can be indexed. Signed-off-by: Jason Yang Assisted-by: Claude:claude-opus-4-8 --- drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c | 330 ++++++++++++++++++= +++- 1 file changed, 320 insertions(+), 10 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-dcphy.c index 0248424929bb..49243ba93bd0 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c @@ -237,6 +237,63 @@ #define DPHY_MD3_TIME_CON4 0x0740 #define DPHY_MD3_DATA_CON0 0x0744 =20 +/* D-PHY receiver direction registers (clock lane + four data lanes) */ +#define DPHY_SC_GNR_CON0 0x0b00 +#define DPHY_SC_GNR_CON1 0x0b04 +#define DPHY_SC_ANA_CON1 0x0b0c +#define HS_RX_BIAS_CON(x) FIELD_PREP(GENMASK(15, 11), x) +#define DPHY_SC_ANA_CON2 0x0b10 +#define HS_TERM_SW(x) FIELD_PREP(GENMASK(2, 0), x) +#define DPHY_SC_ANA_CON3 0x0b14 +#define ULPS_HYS_SW_DPHY(x) FIELD_PREP(GENMASK(10, 8), x) +#define DPHY_SC_TIME_CON0 0x0b30 +#define T_CLK_SETTLE(x) FIELD_PREP(GENMASK(7, 0), x) +#define T_CLK_MISS(x) FIELD_PREP(GENMASK(11, 8), x) +#define COMBO_SD0_GNR_CON0 0x0c00 +#define COMBO_SD0_GNR_CON1 0x0c04 +#define COMBO_SD0_ANA_CON1 0x0c0c +#define COMBO_SD0_ANA_CON2 0x0c10 +#define SKEW_DLYSEL(x) FIELD_PREP(GENMASK(9, 8), x) +#define RX_TERM_SW(x) FIELD_PREP(GENMASK(2, 0), x) +#define COMBO_SD0_ANA_CON3 0x0c14 +#define SEL_ESCPOL BIT(11) +#define LP_HYS_SW(x) FIELD_PREP(GENMASK(5, 4), x) +#define COMBO_SD0_ANA_CON7 0x0c24 +#define CLK_DBL_CTRL(x) FIELD_PREP(GENMASK(7, 6), x) +#define COMBO_SD0_TIME_CON0 0x0c30 +#define T_HS_SETTLE(x) FIELD_PREP(GENMASK(7, 0), x) +#define SETTLE_CLK_SEL BIT(8) +#define COMBO_SD0_TIME_CON1 0x0c34 +#define T_ERR_SOT_SYNC(x) FIELD_PREP(GENMASK(7, 0), x) +#define COMBO_SD0_DESKEW_CON2 0x0c48 +#define SKEW_CAL_CLK_COARSE_SET(x) FIELD_PREP(GENMASK(4, 0), x) +#define COMBO_SD1_GNR_CON0 0x0d00 +#define COMBO_SD1_GNR_CON1 0x0d04 +#define COMBO_SD1_ANA_CON1 0x0d0c +#define COMBO_SD1_ANA_CON2 0x0d10 +#define COMBO_SD1_ANA_CON3 0x0d14 +#define COMBO_SD1_ANA_CON7 0x0d24 +#define COMBO_SD1_TIME_CON0 0x0d30 +#define COMBO_SD1_TIME_CON1 0x0d34 +#define COMBO_SD1_DESKEW_CON2 0x0d48 +#define COMBO_SD2_GNR_CON0 0x0e00 +#define COMBO_SD2_GNR_CON1 0x0e04 +#define COMBO_SD2_ANA_CON1 0x0e0c +#define COMBO_SD2_ANA_CON2 0x0e10 +#define COMBO_SD2_ANA_CON3 0x0e14 +#define COMBO_SD2_ANA_CON7 0x0e24 +#define COMBO_SD2_TIME_CON0 0x0e30 +#define COMBO_SD2_TIME_CON1 0x0e34 +#define COMBO_SD2_DESKEW_CON2 0x0e48 +#define DPHY_SD3_GNR_CON0 0x0f00 +#define DPHY_SD3_GNR_CON1 0x0f04 +#define DPHY_SD3_ANA_CON1 0x0f0c +#define DPHY_SD3_ANA_CON2 0x0f10 +#define DPHY_SD3_ANA_CON3 0x0f14 +#define DPHY_SD3_TIME_CON0 0x0f30 +#define DPHY_SD3_TIME_CON1 0x0f34 +#define DPHY_SD3_DESKEW_CON2 0x0f48 + #define T_LP_EXIT_SKEW(x) FIELD_PREP(GENMASK(3, 2), x) #define T_LP_ENTRY_SKEW(x) FIELD_PREP(GENMASK(1, 0), x) #define T_HS_ZERO(x) FIELD_PREP(GENMASK(15, 8), x) @@ -303,6 +360,7 @@ struct samsung_mipi_dcphy { struct reset_control *apb_rst; struct reset_control *grf_apb_rst; unsigned int lanes; + unsigned long long hs_clk_rate; struct samsung_mipi_dcphy_dir phys[2]; /* Serialises the two directions' access to the shared PHY state. */ struct mutex lock; @@ -986,6 +1044,210 @@ struct samsung_mipi_dphy_timing samsung_mipi_dphy_ti= ming_table[] =3D { { 80, 2, 0, 0, 28, 5, 0, 22, 2, 0, 5}, }; =20 +/* D-PHY receiver HS-RX configuration lookup */ +struct samsung_mipi_dphy_rx_hsfreq_range { + u32 range_h_mbps; + u16 cfg_bit; +}; + +/* + * HS RX settle values taken from the rk3588 vendor kernel. The TRM + * defines these fields but does not publish the per-data-rate table + * (it defers to a separate timing-table supplement). Each cfg_bit is a + * pre-combined SETTLE_CLK_SEL | T_HS_SETTLE value written to the + * data-lane TIME_CON0. Sorted by .range_h_mbps ascending. + */ +static const struct samsung_mipi_dphy_rx_hsfreq_range samsung_mipi_dphy_rx= _hsfreq_ranges[] =3D { + { 80, 0x105 }, { 100, 0x106 }, { 120, 0x107 }, { 140, 0x108 }, + { 160, 0x109 }, { 180, 0x10a }, { 200, 0x10b }, { 220, 0x10c }, + { 240, 0x10d }, { 270, 0x10e }, { 290, 0x10f }, { 310, 0x110 }, + { 330, 0x111 }, { 350, 0x112 }, { 370, 0x113 }, { 390, 0x114 }, + { 410, 0x115 }, { 430, 0x116 }, { 450, 0x117 }, { 470, 0x118 }, + { 490, 0x119 }, { 510, 0x11a }, { 540, 0x11b }, { 560, 0x11c }, + { 580, 0x11d }, { 600, 0x11e }, { 620, 0x11f }, { 640, 0x120 }, + { 660, 0x121 }, { 680, 0x122 }, { 700, 0x123 }, { 720, 0x124 }, + { 740, 0x125 }, { 760, 0x126 }, { 790, 0x127 }, { 810, 0x128 }, + { 830, 0x129 }, { 850, 0x12a }, { 870, 0x12b }, { 890, 0x12c }, + { 910, 0x12d }, { 930, 0x12e }, { 950, 0x12f }, { 970, 0x130 }, + { 990, 0x131 }, { 1010, 0x132 }, { 1030, 0x133 }, { 1060, 0x134 }, + { 1080, 0x135 }, { 1100, 0x136 }, { 1120, 0x137 }, { 1140, 0x138 }, + { 1160, 0x139 }, { 1180, 0x13a }, { 1200, 0x13b }, { 1220, 0x13c }, + { 1240, 0x13d }, { 1260, 0x13e }, { 1280, 0x13f }, { 1310, 0x140 }, + { 1330, 0x141 }, { 1350, 0x142 }, { 1370, 0x143 }, { 1390, 0x144 }, + { 1410, 0x145 }, { 1430, 0x146 }, { 1450, 0x147 }, { 1470, 0x148 }, + { 1490, 0x149 }, { 1580, 0x007 }, { 1740, 0x008 }, { 1910, 0x009 }, + { 2070, 0x00a }, { 2240, 0x00b }, { 2410, 0x00c }, { 2570, 0x00d }, + { 2740, 0x00e }, { 2910, 0x00f }, { 3070, 0x010 }, { 3240, 0x011 }, + { 3410, 0x012 }, { 3570, 0x013 }, { 3740, 0x014 }, { 3890, 0x015 }, + { 4070, 0x016 }, { 4240, 0x017 }, { 4400, 0x018 }, { 4500, 0x019 }, +}; + +static int samsung_mipi_dphy_rx_lookup_hsfreq(u32 lane_mbps, u16 *cfg_bit) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(samsung_mipi_dphy_rx_hsfreq_ranges); i++) { + if (lane_mbps <=3D samsung_mipi_dphy_rx_hsfreq_ranges[i].range_h_mbps) { + *cfg_bit =3D samsung_mipi_dphy_rx_hsfreq_ranges[i].cfg_bit; + return 0; + } + } + + return -ERANGE; +} + +/* SKEW_DLYSEL per data rate, from the RK3588 TRM ANA_CON2 description */ +static u32 samsung_mipi_dphy_rx_data_lane_dlysel(u32 lane_mbps) +{ + if (lane_mbps < 1500) + return 0; + if (lane_mbps < 2000) + return SKEW_DLYSEL(3); + if (lane_mbps < 3000) + return SKEW_DLYSEL(2); + if (lane_mbps < 4000) + return SKEW_DLYSEL(1); + return 0; +} + +/* + * Per-data-lane register bases, indexed by lane number. The clock lane is + * programmed separately; its enable/settle registers do not follow this + * regular spacing. + */ +static const u32 rx_data_lane_gnr_con0[] =3D { + COMBO_SD0_GNR_CON0, COMBO_SD1_GNR_CON0, + COMBO_SD2_GNR_CON0, DPHY_SD3_GNR_CON0, +}; + +static const u32 rx_lane_time_con0[] =3D { + COMBO_SD0_TIME_CON0, COMBO_SD1_TIME_CON0, + COMBO_SD2_TIME_CON0, DPHY_SD3_TIME_CON0, +}; + +static const u32 rx_lane_time_con1[] =3D { + COMBO_SD0_TIME_CON1, COMBO_SD1_TIME_CON1, + COMBO_SD2_TIME_CON1, DPHY_SD3_TIME_CON1, +}; + +/* + * These RX analog tuning values come from the vendor BSP; the + * termination (RX_TERM_SW/HS_TERM_SW =3D 2, 96.6 ohm) additionally + * matches the TRM ANA_CON2 default. + */ +static void samsung_mipi_dphy_rx_config_common(struct samsung_mipi_dcphy *= samsung) +{ + u32 dlysel =3D samsung_mipi_dphy_rx_data_lane_dlysel(div_u64(samsung->hs_= clk_rate, + 1000000)); + u32 ana_con2_common =3D dlysel | RX_TERM_SW(2); + + /* Clock lane */ + regmap_write(samsung->regmap, DPHY_SC_GNR_CON1, T_PHY_READY(0x1450)); + regmap_write(samsung->regmap, DPHY_SC_ANA_CON1, HS_RX_BIAS_CON(0x10)); + regmap_write(samsung->regmap, DPHY_SC_ANA_CON2, HS_TERM_SW(2)); + regmap_write(samsung->regmap, DPHY_SC_ANA_CON3, ULPS_HYS_SW_DPHY(6)); + + /* Data lane 0 */ + if (samsung->lanes > 0) { + regmap_write(samsung->regmap, COMBO_SD0_GNR_CON1, T_PHY_READY(0x1450)); + regmap_write(samsung->regmap, COMBO_SD0_ANA_CON1, HS_RX_BIAS_CON(0x10)); + regmap_write(samsung->regmap, COMBO_SD0_ANA_CON2, ana_con2_common); + regmap_write(samsung->regmap, COMBO_SD0_ANA_CON3, + ULPS_HYS_SW_DPHY(6) | LP_HYS_SW(3) | SEL_ESCPOL); + regmap_write(samsung->regmap, COMBO_SD0_ANA_CON7, CLK_DBL_CTRL(1)); + regmap_write(samsung->regmap, COMBO_SD0_DESKEW_CON2, SKEW_CAL_CLK_COARSE= _SET(0)); + } + + /* Data lane 1 */ + if (samsung->lanes > 1) { + regmap_write(samsung->regmap, COMBO_SD1_GNR_CON1, T_PHY_READY(0x1450)); + regmap_write(samsung->regmap, COMBO_SD1_ANA_CON1, HS_RX_BIAS_CON(0x10)); + regmap_write(samsung->regmap, COMBO_SD1_ANA_CON2, ana_con2_common); + regmap_write(samsung->regmap, COMBO_SD1_ANA_CON3, ULPS_HYS_SW_DPHY(6)); + regmap_write(samsung->regmap, COMBO_SD1_ANA_CON7, CLK_DBL_CTRL(1)); + regmap_write(samsung->regmap, COMBO_SD1_DESKEW_CON2, SKEW_CAL_CLK_COARSE= _SET(3)); + } + + /* Data lane 2 */ + if (samsung->lanes > 2) { + regmap_write(samsung->regmap, COMBO_SD2_GNR_CON1, T_PHY_READY(0x1450)); + regmap_write(samsung->regmap, COMBO_SD2_ANA_CON1, HS_RX_BIAS_CON(0x10)); + regmap_write(samsung->regmap, COMBO_SD2_ANA_CON2, ana_con2_common); + regmap_write(samsung->regmap, COMBO_SD2_ANA_CON3, ULPS_HYS_SW_DPHY(6)); + regmap_write(samsung->regmap, COMBO_SD2_ANA_CON7, CLK_DBL_CTRL(1)); + regmap_write(samsung->regmap, COMBO_SD2_DESKEW_CON2, SKEW_CAL_CLK_COARSE= _SET(3)); + } + + /* Data lane 3 */ + if (samsung->lanes > 3) { + regmap_write(samsung->regmap, DPHY_SD3_GNR_CON1, T_PHY_READY(0x1450)); + regmap_write(samsung->regmap, DPHY_SD3_ANA_CON1, HS_RX_BIAS_CON(0x10)); + regmap_write(samsung->regmap, DPHY_SD3_ANA_CON2, ana_con2_common); + regmap_write(samsung->regmap, DPHY_SD3_ANA_CON3, ULPS_HYS_SW_DPHY(6)); + regmap_write(samsung->regmap, DPHY_SD3_DESKEW_CON2, SKEW_CAL_CLK_COARSE_= SET(3)); + } +} + +static int samsung_mipi_dphy_rx_config_settle(struct samsung_mipi_dcphy *s= amsung) +{ + u32 lane_mbps =3D div_u64(samsung->hs_clk_rate, 1000000); + u16 cfg_bit; + int ret, i; + + ret =3D samsung_mipi_dphy_rx_lookup_hsfreq(lane_mbps, &cfg_bit); + if (ret) { + dev_err(samsung->dev, + "no RX hsfreq cfg for %u Mbps (limit ~4500 Mbps)\n", + lane_mbps); + return ret; + } + + /* + * Clock-lane settle uses the fixed value from the TRM RX bring-up + * example, unlike the per-rate data-lane settle below. + */ + regmap_write(samsung->regmap, DPHY_SC_TIME_CON0, + T_CLK_SETTLE(0x01) | T_CLK_MISS(0x03)); + + for (i =3D 0; i < samsung->lanes; i++) { + regmap_update_bits(samsung->regmap, rx_lane_time_con0[i], + T_HS_SETTLE(0xff) | SETTLE_CLK_SEL, cfg_bit); + regmap_update_bits(samsung->regmap, rx_lane_time_con1[i], + T_ERR_SOT_SYNC(0xff), T_ERR_SOT_SYNC(0x03)); + } + + return 0; +} + +static int samsung_mipi_dphy_rx_lane_enable(struct samsung_mipi_dcphy *sam= sung) +{ + u32 sts; + int ret, i; + + regmap_update_bits(samsung->regmap, DPHY_SC_GNR_CON0, PHY_ENABLE, PHY_ENA= BLE); + for (i =3D 0; i < samsung->lanes; i++) + regmap_update_bits(samsung->regmap, rx_data_lane_gnr_con0[i], + PHY_ENABLE, PHY_ENABLE); + + ret =3D regmap_read_poll_timeout(samsung->regmap, DPHY_SC_GNR_CON0, + sts, sts & PHY_READY, 200, 4000); + if (ret) { + dev_err(samsung->dev, "RX clock lane not ready\n"); + return ret; + } + + for (i =3D 0; i < samsung->lanes; i++) { + ret =3D regmap_read_poll_timeout(samsung->regmap, rx_data_lane_gnr_con0[= i], + sts, sts & PHY_READY, 200, 2000); + if (ret) { + dev_err(samsung->dev, "RX data lane %d not ready\n", i); + return ret; + } + } + + return 0; +} + static void samsung_mipi_dcphy_bias_block_enable(struct samsung_mipi_dcphy= *samsung) { regmap_write(samsung->regmap, BIAS_CON0, I_DEV_DIV_6 | I_RES_100_2UA); @@ -1002,6 +1264,50 @@ static void samsung_mipi_dcphy_bias_block_enable(str= uct samsung_mipi_dcphy *sams I_MUX_SEL_MASK, I_MUX_400MV); } =20 +static int samsung_mipi_dphy_rx_power_on(struct samsung_mipi_dcphy *samsun= g, + struct phy *peer) +{ + bool first =3D peer->power_count =3D=3D 0; + int ret; + + if (!samsung->hs_clk_rate) + return -EINVAL; + + reset_control_assert(samsung->s_phy_rst); + + if (first) + samsung_mipi_dcphy_bias_block_enable(samsung); + samsung_mipi_dphy_rx_config_common(samsung); + + ret =3D samsung_mipi_dphy_rx_config_settle(samsung); + if (ret) + goto out_deassert; + + ret =3D samsung_mipi_dphy_rx_lane_enable(samsung); + +out_deassert: + reset_control_deassert(samsung->s_phy_rst); + + return ret; +} + +static int samsung_mipi_dphy_rx_power_off(struct samsung_mipi_dcphy *samsu= ng) +{ + int i; + + reset_control_assert(samsung->s_phy_rst); + + regmap_update_bits(samsung->regmap, DPHY_SC_GNR_CON0, PHY_ENABLE, 0); + for (i =3D 0; i < samsung->lanes; i++) + regmap_update_bits(samsung->regmap, rx_data_lane_gnr_con0[i], + PHY_ENABLE, 0); + + reset_control_deassert(samsung->s_phy_rst); + usleep_range(500, 1000); + + return 0; +} + static void samsung_mipi_dphy_lane_enable(struct samsung_mipi_dcphy *samsu= ng) { regmap_write(samsung->regmap, DPHY_MC_GNR_CON1, T_PHY_READY(0x2000)); @@ -1404,7 +1710,7 @@ static int samsung_mipi_dcphy_power_on(struct phy *ph= y) =20 mutex_lock(&samsung->lock); if (pd->dir =3D=3D RK_DCPHY_DIR_RX) - ret =3D -EOPNOTSUPP; + ret =3D samsung_mipi_dphy_rx_power_on(samsung, peer); else ret =3D samsung_mipi_dphy_tx_power_on(samsung, peer); mutex_unlock(&samsung->lock); @@ -1421,11 +1727,11 @@ static int samsung_mipi_dcphy_power_off(struct phy = *phy) if (pd->type !=3D PHY_TYPE_DPHY) return -EOPNOTSUPP; =20 - if (pd->dir =3D=3D RK_DCPHY_DIR_RX) - return -EOPNOTSUPP; - mutex_lock(&samsung->lock); - ret =3D samsung_mipi_dphy_tx_power_off(samsung); + if (pd->dir =3D=3D RK_DCPHY_DIR_RX) + ret =3D samsung_mipi_dphy_rx_power_off(samsung); + else + ret =3D samsung_mipi_dphy_tx_power_off(samsung); mutex_unlock(&samsung->lock); =20 return ret; @@ -1525,13 +1831,17 @@ static int samsung_mipi_dcphy_configure(struct phy = *phy, struct samsung_mipi_dcphy *samsung =3D pd->parent; unsigned long long target_rate =3D opts->mipi_dphy.hs_clk_rate; =20 + mutex_lock(&samsung->lock); samsung->lanes =3D opts->mipi_dphy.lanes > 4 ? 4 : opts->mipi_dphy.lanes; =20 - if (pd->dir =3D=3D RK_DCPHY_DIR_RX) - return -EOPNOTSUPP; - - samsung_mipi_dcphy_pll_calc_rate(samsung, target_rate); - opts->mipi_dphy.hs_clk_rate =3D samsung->pll.rate; + if (pd->dir =3D=3D RK_DCPHY_DIR_RX) { + /* The sensor supplies the link clock; the PLL stays off. */ + samsung->hs_clk_rate =3D target_rate; + } else { + samsung_mipi_dcphy_pll_calc_rate(samsung, target_rate); + opts->mipi_dphy.hs_clk_rate =3D samsung->pll.rate; + } + mutex_unlock(&samsung->lock); =20 return 0; } --=20 2.43.0