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[87.0.90.136]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f63ed244bsm2918310f8f.20.2026.07.21.06.24.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2026 06:24:56 -0700 (PDT) From: Carlo Caione Date: Tue, 21 Jul 2026 15:24:46 +0200 Subject: [PATCH] arm64: dts: mediatek: mt8390-genio-700: Add boot phase tags Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260721-ccaione-upstream-mt8390-bootph-v1-1-5642198f979d@baylibre.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/yXN0QrCMAyF4VcZuTbQxeKcryK76GJ0EbaWphNh7 N2tevnB4T8bmGQVg0uzQZaXmsaloj00wFNYHoJ6qwZydHIdtcgc6kRwTVayhBnncj72DscYS5p QQhfIe089MdRIynLX9+/gOvxt6/gULt8q7PsHCWa3c4IAAAA= X-Change-ID: 20260721-ccaione-upstream-mt8390-bootph-ea7a2444292c To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, David Lechner , Julien Stephan , Carlo Caione X-Mailer: b4 0.15.2 U-Boot SPL runs after the platform DDR loader has initialized DRAM. It needs the debug UART and eMMC controller, together with their clock, syscon, pinctrl, interrupt and watchdog providers, to load the firmware FIT. Mark the nodes consumed by the current SPL configuration with 'bootph-pre-ram' so that the canonical devicetree carries the boot-phase information and bootloaders do not need local overrides. Signed-off-by: Carlo Caione --- .../boot/dts/mediatek/mt8390-genio-700-evk.dts | 81 ++++++++++++++++++= ++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/a= rm64/boot/dts/mediatek/mt8390-genio-700-evk.dts index 0d5a75efb2ee..83f2d10fd28d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts @@ -16,11 +16,20 @@ / { "mediatek,mt8188"; =20 memory@40000000 { + bootph-pre-ram; device_type =3D "memory"; reg =3D <0 0x40000000 0x2 0x00000000>; }; }; =20 +&apmixedsys { + bootph-pre-ram; +}; + +&clk26m { + bootph-pre-ram; +}; + &cpu4 { cpu-supply =3D <&mt6359_vcore_buck_reg>; }; @@ -28,3 +37,75 @@ &cpu4 { &cpu5 { cpu-supply =3D <&mt6359_vcore_buck_reg>; }; + +&gic { + bootph-pre-ram; +}; + +&infracfg_ao { + bootph-pre-ram; +}; + +&mmc0 { + bootph-pre-ram; +}; + +&mmc0_default_pins { + bootph-pre-ram; + + pins-clk { + bootph-pre-ram; + }; + + pins-cmd-dat { + bootph-pre-ram; + }; + + pins-rst { + bootph-pre-ram; + }; +}; + +&mmc0_uhs_pins { + bootph-pre-ram; + + pins-clk { + bootph-pre-ram; + }; + + pins-cmd-dat { + bootph-pre-ram; + }; + + pins-ds { + bootph-pre-ram; + }; + + pins-rst { + bootph-pre-ram; + }; +}; + +&pio { + bootph-pre-ram; +}; + +&topckgen { + bootph-pre-ram; +}; + +&uart0 { + bootph-pre-ram; +}; + +&uart0_pins { + bootph-pre-ram; + + pins { + bootph-pre-ram; + }; +}; + +&watchdog { + bootph-pre-ram; +}; --- base-commit: b95f03f04d475aa6719d15a636ddf32222d55657 change-id: 20260721-ccaione-upstream-mt8390-bootph-ea7a2444292c Best regards, -- =20 Carlo Caione