From nobody Sat Jul 25 00:56:37 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 512664BC018; Tue, 21 Jul 2026 10:29:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629747; cv=none; b=f0ogxd1cXuAhvszzCCd4E/o4joTAsgfwNFGNx1Gujkofb6qbPbPsnKn14HGb/LPGGZXkD9TVJJ/L2rY6GarD8dFCs1SuQzgrWHRqSEC81lcPExd+Tkay7Y8775cuVoa45Csz4qSXCtMgz3dteFzJQ2siuY17qSgNqLcyZGvbMmg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629747; c=relaxed/simple; bh=rGwNdljfUqpsoyHEnEHB/eMCZkpIPirWx5+5+J1bEYQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=cPq7EemjPYYQ6ZluGA3/f6x22Ur6+9d/jL9RLE4b7JKKVr/Rk4bg+txlZgZvwq0h7mJpWI7P489nSQTvGTD8pUeNl3lHjmMlruURB3V9RZ38Ibi/tK9FYD10NZ8LFjUXh6EqXkecFfdSN3XkRaBoO0G6ATPyx+/8QsjY18dauHo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=0TYqbv6w; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="0TYqbv6w" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1784629745; x=1816165745; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=rGwNdljfUqpsoyHEnEHB/eMCZkpIPirWx5+5+J1bEYQ=; b=0TYqbv6w054x3hEYMr122wlAl+b1jiNJBMRK751HKRqy0nsUyNdlTwF7 yAMRmmitaeL1/4e8nHkWR3Y/n17IY1w2nSyQYALHJfOWYzqOZgIomVfvs sZXRO4bF+gg8YLsmq22Fdq9GLcvc+1NhK6h60047VNwNf/iW4A/8bRTsl 5s8F6fEyae9YFLyV/epLuBegvkURFDeXMGhIzIqljbrfDCzKHlpldwOKy t2v1VoftSqTt6i2BO11LTxggPuKa6ihS6fEW3z6F8Hpwv0KMLob0dhU8T hKlyEhN63c74rUJRCCdItChmsLHsxWYcyxi2J3yZ/p34bSH/CrK63PMHG Q==; X-CSE-ConnectionGUID: uoxf5opsQI+ASVhY5cugPA== X-CSE-MsgGUID: DwHQARPJROOo2BH/ejpIOw== X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="60065784" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Jul 2026 03:29:04 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 21 Jul 2026 03:29:03 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 21 Jul 2026 03:29:00 -0700 From: Balakrishnan Sambath Date: Tue, 21 Jul 2026 15:58:55 +0530 Subject: [PATCH v3 01/10] media: microchip-isc: fix awb_mutex and lock lifecycle Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260721-balki-isc-prefix-fixes-v1-v3-1-ffe10640a2d9@microchip.com> References: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> In-Reply-To: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab CC: Hans Verkuil , Sakari Ailus , , , Balakrishnan Sambath , X-Mailer: b4 0.14.3 isc_async_complete() initialised awb_mutex and isc->lock only after an early error return, and the teardown was inconsistent: - isc_async_unbind() destroyed awb_mutex before cancelling awb_work, which takes it; - a failed .complete() destroyed both locks, then the v4l2-async core unbinds the subdev and isc_async_unbind() destroyed awb_mutex again; - isc->lock was destroyed only on the .complete() error path, so the normal unbind path leaked it. Initialise both locks before the first error return, make unbind the single teardown site (cancel the work, then destroy both locks) and drop the destroys from the .complete() error path. Fixes: 314c96e5203d ("media: atmel: atmel-isc-base: use mutex to lock awb w= orkq from streaming") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath Reviewed-by. --- drivers/media/platform/microchip/microchip-isc-base.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index a7cdc743fda7..45a7af779323 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -1703,10 +1703,11 @@ static void isc_async_unbind(struct v4l2_async_noti= fier *notifier, { struct isc_device *isc =3D container_of(notifier->v4l2_dev, struct isc_device, v4l2_dev); - mutex_destroy(&isc->awb_mutex); cancel_work_sync(&isc->awb_work); + mutex_destroy(&isc->awb_mutex); video_unregister_device(&isc->video_dev); v4l2_ctrl_handler_free(&isc->ctrls.handler); + mutex_destroy(&isc->lock); } =20 struct isc_format *isc_find_format_by_code(struct isc_device *isc, @@ -1758,6 +1759,8 @@ static int isc_async_complete(struct v4l2_async_notif= ier *notifier) int ret =3D 0; =20 INIT_WORK(&isc->awb_work, isc_awb_work); + mutex_init(&isc->lock); + mutex_init(&isc->awb_mutex); =20 ret =3D v4l2_device_register_subdev_nodes(&isc->v4l2_dev); if (ret < 0) { @@ -1767,8 +1770,6 @@ static int isc_async_complete(struct v4l2_async_notif= ier *notifier) =20 isc->current_subdev =3D container_of(notifier, struct isc_subdev_entity, notifier); - mutex_init(&isc->lock); - mutex_init(&isc->awb_mutex); =20 init_completion(&isc->comp); =20 @@ -1841,8 +1842,6 @@ static int isc_async_complete(struct v4l2_async_notif= ier *notifier) video_unregister_device(vdev); =20 isc_async_complete_err: - mutex_destroy(&isc->awb_mutex); - mutex_destroy(&isc->lock); return ret; } =20 --=20 2.34.1 From nobody Sat Jul 25 00:56:37 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAF064BCAC9; Tue, 21 Jul 2026 10:29:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629750; cv=none; b=IEU/F/hdr6MIxIoRbshgUV+4QimF8ZAEQ6DMAN0kM9NwOi2OcdR9BRtJ01kvngItqtF6RYlF7jgYmYQz1HamzGzsQDuRuYYeWrg81hmNBKUp4NBbYQpRmHed+KzzhKxA5nx8Z5a2DBB7m5Uy2/q3D3KLcYQzZRan138PN4CtkwE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629750; c=relaxed/simple; bh=agcXhHZQfY9GSymiB+S4S7qoSlSq70hKgrCm9xXkH+c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=I5U+xX28M/UGexl7E5MX2BlPsWSYVsvy/Ei3E7+2PZxy+tQKxS6SemBhbModZ7+3HG1bivZaRXYHM5RpnVz5pnDX8a5Eq8U9gKjjToiiT0vNdciJj2GrFI+f9PYAAx6GE00fswK1L9UdhfuU0BkUx6LyNMta/ycuT+U5Fr7RwwI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=aG9Ogqmb; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="aG9Ogqmb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1784629748; x=1816165748; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=agcXhHZQfY9GSymiB+S4S7qoSlSq70hKgrCm9xXkH+c=; b=aG9OgqmbcolOkd3oCL9vOsPqnq7xTVAWCTciOKtgk8MYqxuIjluPW1Em ZhTskclqCAknFi5Twutz4bia3aCpc52htXaNNlKz8xQZivcZhXJzz8twJ viE5q2amFLrx2I4T9PA8C0QwqphVVZ33WNs9TVOOy1Uegs6/Xj/FSqHLh dwafOPRkd0HXwya9pAcpOU85b78593G8bqW2adnLF6g90dqsPJdRRVMAO PlvNXF1H2opKnmKVcuulB9ty54moNAbmSjidT6l9//ZdcW5aILc6dG0jN fRCipj53Clg7MHzOliy5GWf7M/tspY705IPyCIn0JSMPLC81Hu6vPyTsu g==; X-CSE-ConnectionGUID: z0MTQ9PWRtKBXwPtwDIG6w== X-CSE-MsgGUID: zxVoJSAuRRKY0UQ1uUnxqg== X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="228086565" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Jul 2026 03:29:07 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 21 Jul 2026 03:29:07 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 21 Jul 2026 03:29:04 -0700 From: Balakrishnan Sambath Date: Tue, 21 Jul 2026 15:58:56 +0530 Subject: [PATCH v3 02/10] media: microchip-isc: take a reference on the parsed endpoints Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260721-balki-isc-prefix-fixes-v1-v3-2-ffe10640a2d9@microchip.com> References: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> In-Reply-To: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab CC: Hans Verkuil , Sakari Ailus , , , Balakrishnan Sambath , X-Mailer: b4 0.14.3 for_each_endpoint_of_node() drops the reference on the current node as it advances. xisc_parse_dt() and isc_parse_dt() store the node in subdev_entity->epn and release it later with of_node_put(), but never took their own reference, so the stored pointer refers to an already-released node. This underflows the refcount and can use-after-free, reachable through the camera device tree overlay. Take a reference with of_node_get() when storing the node, and drop it in microchip_isc_subdev_cleanup() so the entities the bind loop never reaches on an early exit do not leak it. Fixes: c9aa973884a1 ("media: atmel: atmel-isc: add microchip-xisc driver") Fixes: d6701f13bd07 ("media: atmel: Use v4l2_async_notifier_add_fwnode_remo= te_subdev") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath Reviewed-by. --- drivers/media/platform/microchip/microchip-isc-base.c | 6 ++++++ .../media/platform/microchip/microchip-sama5d2-isc.c | 18 ++++++++++++--= ---- .../media/platform/microchip/microchip-sama7g5-isc.c | 18 ++++++++++++--= ---- 3 files changed, 30 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 45a7af779323..4079c79cb668 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -1859,6 +1859,12 @@ void microchip_isc_subdev_cleanup(struct isc_device = *isc) list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { v4l2_async_nf_unregister(&subdev_entity->notifier); v4l2_async_nf_cleanup(&subdev_entity->notifier); + /* + * Release the endpoint reference taken while parsing. It is + * NULL for entities the bind loop already consumed, so this + * only drops the ones left over on an early exit. + */ + of_node_put(subdev_entity->epn); } =20 INIT_LIST_HEAD(&isc->subdev_entities); diff --git a/drivers/media/platform/microchip/microchip-sama5d2-isc.c b/dri= vers/media/platform/microchip/microchip-sama5d2-isc.c index 66d3d7891991..97752eca6d6b 100644 --- a/drivers/media/platform/microchip/microchip-sama5d2-isc.c +++ b/drivers/media/platform/microchip/microchip-sama5d2-isc.c @@ -356,28 +356,28 @@ static int isc_parse_dt(struct device *dev, struct is= c_device *isc) struct device_node *epn; struct isc_subdev_entity *subdev_entity; unsigned int flags; + int ret; =20 INIT_LIST_HEAD(&isc->subdev_entities); =20 for_each_endpoint_of_node(np, epn) { struct v4l2_fwnode_endpoint v4l2_epn =3D { .bus_type =3D 0 }; - int ret; =20 ret =3D v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn), &v4l2_epn); if (ret) { - of_node_put(epn); dev_err(dev, "Could not parse the endpoint\n"); - return -EINVAL; + ret =3D -EINVAL; + goto err_put; } =20 subdev_entity =3D devm_kzalloc(dev, sizeof(*subdev_entity), GFP_KERNEL); if (!subdev_entity) { - of_node_put(epn); - return -ENOMEM; + ret =3D -ENOMEM; + goto err_put; } - subdev_entity->epn =3D epn; + subdev_entity->epn =3D of_node_get(epn); =20 flags =3D v4l2_epn.bus.parallel.flags; =20 @@ -398,6 +398,12 @@ static int isc_parse_dt(struct device *dev, struct isc= _device *isc) } =20 return 0; + +err_put: + of_node_put(epn); + list_for_each_entry(subdev_entity, &isc->subdev_entities, list) + of_node_put(subdev_entity->epn); + return ret; } =20 static int microchip_isc_probe(struct platform_device *pdev) diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index b0302dfc3278..1f5debb74f18 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -340,6 +340,7 @@ static int xisc_parse_dt(struct device *dev, struct isc= _device *isc) struct isc_subdev_entity *subdev_entity; unsigned int flags; bool mipi_mode; + int ret; =20 INIT_LIST_HEAD(&isc->subdev_entities); =20 @@ -347,23 +348,22 @@ static int xisc_parse_dt(struct device *dev, struct i= sc_device *isc) =20 for_each_endpoint_of_node(np, epn) { struct v4l2_fwnode_endpoint v4l2_epn =3D { .bus_type =3D 0 }; - int ret; =20 ret =3D v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn), &v4l2_epn); if (ret) { - of_node_put(epn); dev_err(dev, "Could not parse the endpoint\n"); - return -EINVAL; + ret =3D -EINVAL; + goto err_put; } =20 subdev_entity =3D devm_kzalloc(dev, sizeof(*subdev_entity), GFP_KERNEL); if (!subdev_entity) { - of_node_put(epn); - return -ENOMEM; + ret =3D -ENOMEM; + goto err_put; } - subdev_entity->epn =3D epn; + subdev_entity->epn =3D of_node_get(epn); =20 flags =3D v4l2_epn.bus.parallel.flags; =20 @@ -387,6 +387,12 @@ static int xisc_parse_dt(struct device *dev, struct is= c_device *isc) } =20 return 0; + +err_put: + of_node_put(epn); + list_for_each_entry(subdev_entity, &isc->subdev_entities, list) + of_node_put(subdev_entity->epn); + return ret; } =20 static int microchip_xisc_probe(struct platform_device *pdev) --=20 2.34.1 From nobody Sat Jul 25 00:56:37 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 370E348094A; Tue, 21 Jul 2026 10:29:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629753; cv=none; b=JNPhJ5+JFC7Sb9+1YT9JMIwFUWO7nyxQmwYnqQaoVRMhMzc1qKLwDzb6zYsirPkQrrX6M4PR+3ODuRDXDR5ma3y/IAwOZB5VaNcJfAZSQidScIcK6ZOGwmO8BaodwniJbMOMrvZhu80IS82R/GWlUfMH4YBsdHi2WqIVugf7ceQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629753; c=relaxed/simple; bh=QjMhShKxO3OGwWri1KKz/lfCQ4br/t2CuT6xsbob8cw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=HOYSXAU6cSeQd6cVIlSu7V3xc42eoXgEfD1VVRCJn+dn68v1darDC7FUQYbRiOhPLskbGZmHUBH+WOIv65qrAW9KC+T8QxPlcCc4A7wmL93zYwsBA2az+hZJ0NRipuf3Mt9rxLcbR3bmM6TtFQ0MKDwt95I9YHCgndGbNABrA00= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=JAXQhJcL; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="JAXQhJcL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1784629754; x=1816165754; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=QjMhShKxO3OGwWri1KKz/lfCQ4br/t2CuT6xsbob8cw=; b=JAXQhJcLhmn6IGQUN8RxgA+TCN3MspjNQnvLvyGMspwm8awaLwdxz5yZ Ze17p6eSXg2cvTTtQVVW3TpEklIqJ6eKDQpZmbFZmoMdqJbVh/MoK3STE k71VsKM/FD59SMD4ENHmATUQIfqb6EvjNGfgPCzYFuNDLixvZj+lHjFfX O1ZcIAWSOmfwvhZtfBR2j1He1hqtaeVCVME2Wo5yFHVP9d9famAi93GY9 smNGYGkiYZ/mulXGI6vcBEAsq0Np8zisqOR14XG93jOR8MOLMrR26n3/O XIKJFFIf9c7y0fQnHW+Fjyy7DCGHC056PDFeL2LgDLCD1KoAV875jwPac g==; X-CSE-ConnectionGUID: /K1VPm7KQJy0aVhXlOXhzA== X-CSE-MsgGUID: xCacKeDEQ/aCSNRIhayFVQ== X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="61253554" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2026 03:29:14 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 21 Jul 2026 03:29:11 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 21 Jul 2026 03:29:07 -0700 From: Balakrishnan Sambath Date: Tue, 21 Jul 2026 15:58:57 +0530 Subject: [PATCH v3 03/10] media: microchip-isc: synchronize the IRQ before disabling clocks on stop Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260721-balki-isc-prefix-fixes-v1-v3-3-ffe10640a2d9@microchip.com> References: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> In-Reply-To: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab CC: Hans Verkuil , Sakari Ailus , , , Balakrishnan Sambath , X-Mailer: b4 0.14.3 isc_stop_streaming() masks the DMA interrupt and then drops the runtime PM reference, which disables the ISC clocks. microchip_isc_interrupt() may still be executing on another CPU at that point; it reads ISC_INTSR over regmap, and touching the unclocked registers triggers an external abort. Store the IRQ number at probe and call synchronize_irq() after masking the interrupt, before dropping the PM reference. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath Reviewed-by: Eugen Hristev Reviewed-by. --- drivers/media/platform/microchip/microchip-isc-base.c | 3 +++ drivers/media/platform/microchip/microchip-isc.h | 1 + drivers/media/platform/microchip/microchip-sama5d2-isc.c | 2 ++ drivers/media/platform/microchip/microchip-sama7g5-isc.c | 2 ++ 4 files changed, 8 insertions(+) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 4079c79cb668..3245dd7cb980 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -425,6 +425,9 @@ static void isc_stop_streaming(struct vb2_queue *vq) /* Disable DMA interrupt */ regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE); =20 + /* let a running IRQ handler finish before the clock is disabled */ + synchronize_irq(isc->irq); + pm_runtime_put_sync(isc->dev); =20 /* Disable stream on the sub device */ diff --git a/drivers/media/platform/microchip/microchip-isc.h b/drivers/med= ia/platform/microchip/microchip-isc.h index ad4e98a1dd8f..f5e322c2e36b 100644 --- a/drivers/media/platform/microchip/microchip-isc.h +++ b/drivers/media/platform/microchip/microchip-isc.h @@ -287,6 +287,7 @@ struct isc_device { u32 dcfg; =20 struct device *dev; + int irq; struct v4l2_device v4l2_dev; struct video_device video_dev; =20 diff --git a/drivers/media/platform/microchip/microchip-sama5d2-isc.c b/dri= vers/media/platform/microchip/microchip-sama5d2-isc.c index 97752eca6d6b..5d49b9d48f57 100644 --- a/drivers/media/platform/microchip/microchip-sama5d2-isc.c +++ b/drivers/media/platform/microchip/microchip-sama5d2-isc.c @@ -438,6 +438,8 @@ static int microchip_isc_probe(struct platform_device *= pdev) if (irq < 0) return irq; =20 + isc->irq =3D irq; + ret =3D devm_request_irq(dev, irq, microchip_isc_interrupt, 0, "microchip-sama5d2-isc", isc); if (ret < 0) { diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index 1f5debb74f18..4f9e9a5ed4d1 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -427,6 +427,8 @@ static int microchip_xisc_probe(struct platform_device = *pdev) if (irq < 0) return irq; =20 + isc->irq =3D irq; + ret =3D devm_request_irq(dev, irq, microchip_isc_interrupt, 0, "microchip-sama7g5-xisc", isc); if (ret < 0) { --=20 2.34.1 From nobody Sat Jul 25 00:56:37 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A366F4C6F16; Tue, 21 Jul 2026 10:29:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629757; cv=none; b=nyb8tFXWFcMLxjYmNLgw5RzzIiQEsV75/gbYdaJjhrPj82c7IwJjHv12XrTL9mtje4+48v1H69UbmoDHFwjTvV6Yg3i1sbWmcFtpWnJKCdo6ARhn4kfe/TU/csWKgWkQCp3qku/BoAuKjGWF+zeEuTwXxmb6BLiFxu914jDEzdU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629757; c=relaxed/simple; bh=esMQmpoz+9HrMhUVsd3LDBeCJbI/0R/M4IlECi5M2E8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=sYZ+rSLWPmaB6fWVRnE/P1ME+4wU+unWU5bX8Z5xyCNPz4/5zZEMFQk37RWwwNe1qDiLzGg98xuwyWQcfCULzOdxKKhvth366t2GaRt1sRz2m2i4L+emrdLL+5oQUYC+c1z7ftnjQR6esMiA3PtzQgS9uU8hyLSLArC+rJ8DKXs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=jS80dxPy; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="jS80dxPy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1784629755; x=1816165755; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=esMQmpoz+9HrMhUVsd3LDBeCJbI/0R/M4IlECi5M2E8=; b=jS80dxPy01HeAI7iP7HkDGs89yujnHgWPhZs7kbihgris9uUskETuxKI r7mXQnCTUJdtVjuHWqnx+Nwg1MHtyJlKlBDF4hXx4PlMt7KFQXCT8FEVt kv43F0w6KqJWBkQxf5jc5oiYuPFYlFWAw4hEg+L77oPG/D5d9K5rgNrEd NvtMAJ5lVTvDy9TdFkQCZEyl/Ff8o3Bhu1X9fAqE11w0al/JD0taxbNse 8+VWZdNzWLc6vwVmpTzFb/GqNvsdzCIaq/opSkWaPpJ6z7I6fCyFi45xX mPm3mSZSqmuIjwJrxxlVNK1TTCmPnLGduocg0FWnhLXeiRfDXbxMDBgiU g==; X-CSE-ConnectionGUID: 24S+yiX3RuO97D4RBF7AxA== X-CSE-MsgGUID: MU3U0l5fTOOM/GZfBDnsjg== X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="228086570" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Jul 2026 03:29:15 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 21 Jul 2026 03:29:15 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 21 Jul 2026 03:29:11 -0700 From: Balakrishnan Sambath Date: Tue, 21 Jul 2026 15:58:58 +0530 Subject: [PATCH v3 04/10] media: microchip-isc: disable histogram and flush AWB work on teardown Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260721-balki-isc-prefix-fixes-v1-v3-4-ffe10640a2d9@microchip.com> References: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> In-Reply-To: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab CC: Hans Verkuil , Sakari Ailus , , , Balakrishnan Sambath , X-Mailer: b4 0.14.3 isc_stop_streaming() and the isc_start_streaming() error path dropped the runtime PM reference with the histogram still enabled. A HISDONE firing just before the stop, or a failed isc_update_profile() on the start path, can queue isc_awb_work(), which reads the histogram registers before taking its own PM reference and faults on the unclocked device. Disable the histogram, synchronize the IRQ and flush the work before dropping the PM reference on both paths. synchronize_irq() must come before cancel_work_sync(), so an in-flight handler cannot re-queue awb_work after it is cancelled. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath Reviewed-by. --- drivers/media/platform/microchip/microchip-isc-base.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 3245dd7cb980..f7fbd3cd8edc 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -382,6 +382,13 @@ static int isc_start_streaming(struct vb2_queue *vq, u= nsigned int count) return 0; =20 err_configure: + isc_set_histogram(isc, false); + + /* let a running IRQ handler finish before the clock is disabled */ + synchronize_irq(isc->irq); + + cancel_work_sync(&isc->awb_work); + pm_runtime_put_sync(isc->dev); err_pm_get: v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0); @@ -425,9 +432,13 @@ static void isc_stop_streaming(struct vb2_queue *vq) /* Disable DMA interrupt */ regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE); =20 + isc_set_histogram(isc, false); + /* let a running IRQ handler finish before the clock is disabled */ synchronize_irq(isc->irq); =20 + cancel_work_sync(&isc->awb_work); + pm_runtime_put_sync(isc->dev); =20 /* Disable stream on the sub device */ --=20 2.34.1 From nobody Sat Jul 25 00:56:37 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E822748A2AF; Tue, 21 Jul 2026 10:29:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629761; cv=none; b=YmmfmpIxg2XIaUBQANqiFM9eLG+sJlGqghhnwCZMAwH6gN5u1fLtxtfnf+/qS0qvEbafQTsKI8CYLzV+NTmpbnT3jC7EJ1iNblnK0jM5vFHmEMFfsFt7y7O2PCjfyhiq789QVyuX8mdiuxHN02wkmBrvZCQ26nCCwFO+MGWIiZY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629761; c=relaxed/simple; bh=13gOV7y53/OaFfLIEPAL0LSpK9N+zhp4tOFZKUoPAFE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Sq6+Mpar0vAz4UkNKmc77Io9CtFDRm++qa4CHMOZ+QjefDRIcPvoaK64ELj7DD26+s0yBD5i4afa6xxyrGwaClm2bILmjHzc/7HC4/sm9VvgiOZhJMH9I5795j+a3pIifgYRWDAtgX2BTg1mTUhOtGrEmRjeNAqasjfcRXbE+Bc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ThANb/37; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ThANb/37" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1784629760; x=1816165760; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=13gOV7y53/OaFfLIEPAL0LSpK9N+zhp4tOFZKUoPAFE=; b=ThANb/37mk1V+bE+dhLOo3VyhEFyLNuaItUyzOr4srwJuivsRJKLCf4C ty5ovXtgc42Yd3OmICwLstmB4gPHXTJcSBO73V5uo8VBsi9GTFsG3oR82 tET1xWUQsRYw4EVWnX+825ZHCc8Lm94Rp3o8s/BEIAXl+xS8q6Q+wUQGv wWCdIjkfS5Ocn4UictUTWvBe2vE5qR6hWlHhhqbQYtYQQlRYHHh1FttHh zXKLdC99zVf9tbUftHlmnx61XMBgJkdRJD4A38ZRPQ1cQBtdgAJfilIML IhCJDLg+xqvuJdA2gHBAl6aDDUwCOGLctmdWXVwcxFXT5taFAY66SGdAB g==; X-CSE-ConnectionGUID: F5bjUNzqSS2gSXWCTp9ktw== X-CSE-MsgGUID: HMefnoYWTSeQRmMSEMkQ3g== X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="60936717" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2026 03:29:19 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 21 Jul 2026 03:29:18 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 21 Jul 2026 03:29:15 -0700 From: Balakrishnan Sambath Date: Tue, 21 Jul 2026 15:58:59 +0530 Subject: [PATCH v3 05/10] media: microchip-isc: do not touch WB registers when not streaming Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260721-balki-isc-prefix-fixes-v1-v3-5-ffe10640a2d9@microchip.com> References: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> In-Reply-To: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab CC: Hans Verkuil , Sakari Ailus , , , Balakrishnan Sambath , X-Mailer: b4 0.14.3 isc_s_awb_ctrl() called isc_update_awb_ctrls() unconditionally, writing the white balance registers even when the device is runtime suspended; on many ARM platforms accessing the unclocked registers is an external abort. The write was also done without awb_lock, racing isc_awb_work(), which holds it so the DMA done IRQ cannot latch a half-updated pipeline. Write the registers only while streaming and not stopping, under awb_lock, and update the profile there. The isc->stop check covers the window where isc_stop_streaming() has gated the clocks but vb2 still reports streaming. Otherwise the new values stay cached and isc_configure() programs them at the next stream start. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath Reviewed-by. --- .../media/platform/microchip/microchip-isc-base.c | 20 ++++++++++++----= ---- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index f7fbd3cd8edc..a2f7035f4418 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -1509,20 +1509,24 @@ static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl) if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new) ctrls->offset[ISC_HIS_CFG_MODE_GB] =3D isc->gb_off_ctrl->val; =20 - isc_update_awb_ctrls(isc); - mutex_lock(&isc->awb_mutex); - if (vb2_is_streaming(&isc->vb2_vidq)) { + if (vb2_is_streaming(&isc->vb2_vidq) && !isc->stop) { + unsigned long flags; + /* - * If we are streaming, we can update profile to - * have the new settings in place. + * awb_lock keeps the DMA done IRQ from latching a + * partially written WB pipeline. */ + spin_lock_irqsave(&isc->awb_lock, flags); + isc_update_awb_ctrls(isc); + spin_unlock_irqrestore(&isc->awb_lock, flags); + isc_update_profile(isc); } else { /* - * The auto cluster will activate automatically this - * control. This has to be deactivated when not - * streaming. + * Not streaming: keep the cached values for the next + * stream start and deactivate the cluster-activated + * do_white_balance button. */ v4l2_ctrl_activate(isc->do_wb_ctrl, false); } --=20 2.34.1 From nobody Sat Jul 25 00:56:37 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35B764C8FF1; Tue, 21 Jul 2026 10:29:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629764; cv=none; b=PgEanipS4pjlPtTaiPJT6ylmEPfmI/4MPcfKLyu7jY9AsHWH4KEBvEl8At1oCbq6wNrgP5wYtkrdP/Z4bTCpKQN9yJMkw66hcL8zGuC4hIK9t2sPkqJEu+HOCePWK500UkA8r8B5FtjOuuDE9auKagiVIpKsLKoD+nfIsLat1pk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629764; c=relaxed/simple; bh=LanOpCefh0Wq2uHg0qXYII9bpZ1K1bt7uvzQK1nc7FU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=XCXicZbJZmZhDqSwwju10Hfc9JSuKlDRf/lLJr7oAYkewacUTmKcvmDh4PZqqhyW1PMe5/EMneQTyZq07NdAvSNAgo2mNidK0cIaFjpq7ZoRjC7Ulf6DGm4q3R4C4h75yp8vBRJvbCgeWtGVLhMYUkM1x9YvKvXjZK5ElO6BAbE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=awUidSnl; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="awUidSnl" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1784629763; x=1816165763; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=LanOpCefh0Wq2uHg0qXYII9bpZ1K1bt7uvzQK1nc7FU=; b=awUidSnl1jO0bf2Vkgg0SYN183C9Ustkm1z/bgWHdF8/YAceUD92ZxE5 +LfVRXObP2tO0QzgLeMyn7/sXnvROaTkVFNZzYYcZNRQMnkbAsVX1mdk9 JfAgUIJgALQ5JDwLmCRJzQfmzyxAOKjfSWFmbGNk8U65gKrM9W5tXwtxL fWtWqFFmII5GunjBdQuvZwuO+zeDJzd/y2VNPe0ifKTt496a8yLtOrhP8 ZmLoXxgYqRl1kLzxIVJ+DPEUDOluqn9aIjWt1wv5gx7u4Ec+c3qHeCW7q YMQ10Tg/d42o9iOhJAzjRRG3LiH6hNPk32PGdMPefZfOMQue0VRwOpjUK Q==; X-CSE-ConnectionGUID: 4nG4VtqbSY+OFCNA9iqRDQ== X-CSE-MsgGUID: +SE+v8i0R3arcB3mRGgO3w== X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="60936724" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2026 03:29:23 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 21 Jul 2026 03:29:22 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 21 Jul 2026 03:29:19 -0700 From: Balakrishnan Sambath Date: Tue, 21 Jul 2026 15:59:00 +0530 Subject: [PATCH v3 06/10] media: microchip-isc: store the unshifted PFE_CFG0 BPS value Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260721-balki-isc-prefix-fixes-v1-v3-6-ffe10640a2d9@microchip.com> References: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> In-Reply-To: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab CC: Hans Verkuil , Sakari Ailus , , , Balakrishnan Sambath X-Mailer: b4 0.14.3 pfe_cfg0_bps held a pre-shifted BPS value (ISC_PFE_CFG0_BPS_EIGHT was 0x4 << 28) ORed straight into the register. The other format selectors like cfa_baycfg store the bare field value and position it at the write, so this one was inconsistent. Store the bare BPS value and apply it with FIELD_PREP() at the PFE_CFG0 write, and fix the pfe_cfg0_bps comment to match. No functional change. Suggested-by: Eugen Hristev Reviewed-by: Eugen Hristev Signed-off-by: Balakrishnan Sambath Reviewed-by. --- drivers/media/platform/microchip/microchip-isc-base.c | 4 +++- drivers/media/platform/microchip/microchip-isc-regs.h | 10 +++++----- drivers/media/platform/microchip/microchip-isc.h | 4 +++- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index a2f7035f4418..4e87e5f45ac4 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -8,6 +8,7 @@ * Author: Eugen Hristev * */ +#include #include #include #include @@ -290,7 +291,8 @@ static int isc_configure(struct isc_device *isc) u32 pfe_cfg0, dcfg, mask, pipeline; struct isc_subdev_entity *subdev =3D isc->current_subdev; =20 - pfe_cfg0 =3D isc->config.sd_format->pfe_cfg0_bps; + pfe_cfg0 =3D FIELD_PREP(ISC_PFE_CFG0_BPS_MASK, + isc->config.sd_format->pfe_cfg0_bps); pipeline =3D isc->config.bits_pipeline; =20 dcfg =3D isc->config.dcfg_imode | isc->dcfg; diff --git a/drivers/media/platform/microchip/microchip-isc-regs.h b/driver= s/media/platform/microchip/microchip-isc-regs.h index e77e1d9a1db8..185ef0eab7ad 100644 --- a/drivers/media/platform/microchip/microchip-isc-regs.h +++ b/drivers/media/platform/microchip/microchip-isc-regs.h @@ -31,11 +31,11 @@ #define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4) #define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4) =20 -#define ISC_PFE_CFG0_BPS_EIGHT (0x4 << 28) -#define ISC_PFG_CFG0_BPS_NINE (0x3 << 28) -#define ISC_PFG_CFG0_BPS_TEN (0x2 << 28) -#define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28) -#define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28) +#define ISC_PFE_CFG0_BPS_EIGHT 0x4 +#define ISC_PFG_CFG0_BPS_NINE 0x3 +#define ISC_PFG_CFG0_BPS_TEN 0x2 +#define ISC_PFG_CFG0_BPS_ELEVEN 0x1 +#define ISC_PFG_CFG0_BPS_TWELVE 0x0 #define ISC_PFE_CFG0_BPS_MASK GENMASK(30, 28) =20 #define ISC_PFE_CFG0_COLEN BIT(12) diff --git a/drivers/media/platform/microchip/microchip-isc.h b/drivers/med= ia/platform/microchip/microchip-isc.h index f5e322c2e36b..d7bcd74efff9 100644 --- a/drivers/media/platform/microchip/microchip-isc.h +++ b/drivers/media/platform/microchip/microchip-isc.h @@ -62,7 +62,9 @@ struct isc_subdev_entity { * @mbus_code: V4L2 media bus format code. * @cfa_baycfg: If this format is RAW BAYER, indicate the type of bayer. this is either BGBG, RGRG, etc. - * @pfe_cfg0_bps: Number of hardware data lines connected to the ISC + * @pfe_cfg0_bps: ISC_PFE_CFG0 BPS field value (e.g. ISC_PFE_CFG0_BPS_EIGH= T), + written into PFE_CFG0 with FIELD_PREP(ISC_PFE_CFG0_BPS_MASK) + at configure time. * @raw: If the format is raw bayer. */ =20 --=20 2.34.1 From nobody Sat Jul 25 00:56:37 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C9154C954F; Tue, 21 Jul 2026 10:29:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629768; cv=none; b=BLo55PHSOjaVo+tFy4HUSy5v7wj9MOuAxkghaMJ6m5XTzicmp2QYQCmiirkERAjk0YcVUWgcITa1GxJtvn/GZcIV+vS0iAcYy0sMF4x+H+fewJLl6IOm71GCHBy0f/hsN8ahocfrZwWapdZ6j2ngbBeoDz63KGR5pE7A3LQns4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629768; c=relaxed/simple; bh=j0KXHVhA9Nk3Zu437OiBALAmlzFLPYeLHG9ejmycSoY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=uZ8ZMsr11VTj6bE4iIXiKTwxDGNzo116PfE9irT8q33GmhgdTnsgLfyBRoRIwXW35CW+Efs4hlIrb/sKEmZdju4S5T10cwIP8DkaiRpfaZXzw+MR4eDBmdpvXTCmmd1O/QoLx7UkhualQzXUCiUaqBMVOXyp5B717WLvN6RX2UM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=sc0yJ17F; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="sc0yJ17F" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1784629769; x=1816165769; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=j0KXHVhA9Nk3Zu437OiBALAmlzFLPYeLHG9ejmycSoY=; b=sc0yJ17FvceawoYwz9goXIDYVLQok11GRVPVcRC/WZvSINRw992KScFI z9VG91h++oduI+rEQL5DxMxDUr6Q3muPU7FZaMV26rJFNGT12qfq1ryCf qB8lj8+1WDjedgbtXejLUTnpnHdD/YVogkVq4L47MgcnnTHI7z//DeFCj IeQx/yxpP3JfFoJ2862LiRTdkltjzIDdZmie8yve8PaRHo9viCHl1Jab+ PgQuR0lN4qDqa+ERp0blhq8CKreg+BlG1mS7n+XyaLCjIPM9swbuxt2eT G6pTBQ8T+pLETyAWxlfvc4iEL7c6+CRQNiodjtBbJX4s+kQGTc6bZCS0y w==; X-CSE-ConnectionGUID: tbhQ8VSlQLSDmZv37VHgYQ== X-CSE-MsgGUID: EiIDMRKQRWy3wOY25oC9Ow== X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="61253563" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Jul 2026 03:29:29 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 21 Jul 2026 03:29:26 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 21 Jul 2026 03:29:22 -0700 From: Balakrishnan Sambath Date: Tue, 21 Jul 2026 15:59:01 +0530 Subject: [PATCH v3 07/10] media: microchip-isc: fix ISC_PFG_CFG0_BPS macro name typo Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260721-balki-isc-prefix-fixes-v1-v3-7-ffe10640a2d9@microchip.com> References: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> In-Reply-To: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab CC: Hans Verkuil , Sakari Ailus , , , Balakrishnan Sambath X-Mailer: b4 0.14.3 The BPS field macros for ISC_PFE_CFG0 were spelled ISC_PFG_CFG0_BPS_* (NINE, TEN, ELEVEN, TWELVE). The register is PFE, not PFG. Rename them to ISC_PFE_CFG0_BPS_* to match the register and the EIGHT and MASK macros. No functional change. Reviewed-by: Eugen Hristev Signed-off-by: Balakrishnan Sambath Reviewed-by. --- drivers/media/platform/microchip/microchip-isc-regs.h | 8 ++++---- .../media/platform/microchip/microchip-sama5d2-isc.c | 18 +++++++++-----= ---- .../media/platform/microchip/microchip-sama7g5-isc.c | 18 +++++++++-----= ---- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-regs.h b/driver= s/media/platform/microchip/microchip-isc-regs.h index 185ef0eab7ad..9ddbbb6dd68b 100644 --- a/drivers/media/platform/microchip/microchip-isc-regs.h +++ b/drivers/media/platform/microchip/microchip-isc-regs.h @@ -32,10 +32,10 @@ #define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4) =20 #define ISC_PFE_CFG0_BPS_EIGHT 0x4 -#define ISC_PFG_CFG0_BPS_NINE 0x3 -#define ISC_PFG_CFG0_BPS_TEN 0x2 -#define ISC_PFG_CFG0_BPS_ELEVEN 0x1 -#define ISC_PFG_CFG0_BPS_TWELVE 0x0 +#define ISC_PFE_CFG0_BPS_NINE 0x3 +#define ISC_PFE_CFG0_BPS_TEN 0x2 +#define ISC_PFE_CFG0_BPS_ELEVEN 0x1 +#define ISC_PFE_CFG0_BPS_TWELVE 0x0 #define ISC_PFE_CFG0_BPS_MASK GENMASK(30, 28) =20 #define ISC_PFE_CFG0_COLEN BIT(12) diff --git a/drivers/media/platform/microchip/microchip-sama5d2-isc.c b/dri= vers/media/platform/microchip/microchip-sama5d2-isc.c index 5d49b9d48f57..5c59a692b30e 100644 --- a/drivers/media/platform/microchip/microchip-sama5d2-isc.c +++ b/drivers/media/platform/microchip/microchip-sama5d2-isc.c @@ -146,49 +146,49 @@ static struct isc_format sama5d2_formats_list[] =3D { { .fourcc =3D V4L2_PIX_FMT_SBGGR10, .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TEN, .cfa_baycfg =3D ISC_BAY_CFG_RGRG, }, { .fourcc =3D V4L2_PIX_FMT_SGBRG10, .mbus_code =3D MEDIA_BUS_FMT_SGBRG10_1X10, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TEN, .cfa_baycfg =3D ISC_BAY_CFG_GBGB, }, { .fourcc =3D V4L2_PIX_FMT_SGRBG10, .mbus_code =3D MEDIA_BUS_FMT_SGRBG10_1X10, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TEN, .cfa_baycfg =3D ISC_BAY_CFG_GRGR, }, { .fourcc =3D V4L2_PIX_FMT_SRGGB10, .mbus_code =3D MEDIA_BUS_FMT_SRGGB10_1X10, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TEN, .cfa_baycfg =3D ISC_BAY_CFG_RGRG, }, { .fourcc =3D V4L2_PIX_FMT_SBGGR12, .mbus_code =3D MEDIA_BUS_FMT_SBGGR12_1X12, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TWELVE, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TWELVE, .cfa_baycfg =3D ISC_BAY_CFG_BGBG, }, { .fourcc =3D V4L2_PIX_FMT_SGBRG12, .mbus_code =3D MEDIA_BUS_FMT_SGBRG12_1X12, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TWELVE, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TWELVE, .cfa_baycfg =3D ISC_BAY_CFG_GBGB, }, { .fourcc =3D V4L2_PIX_FMT_SGRBG12, .mbus_code =3D MEDIA_BUS_FMT_SGRBG12_1X12, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TWELVE, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TWELVE, .cfa_baycfg =3D ISC_BAY_CFG_GRGR, }, { .fourcc =3D V4L2_PIX_FMT_SRGGB12, .mbus_code =3D MEDIA_BUS_FMT_SRGGB12_1X12, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TWELVE, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TWELVE, .cfa_baycfg =3D ISC_BAY_CFG_RGRG, }, { @@ -209,7 +209,7 @@ static struct isc_format sama5d2_formats_list[] =3D { { .fourcc =3D V4L2_PIX_FMT_Y10, .mbus_code =3D MEDIA_BUS_FMT_Y10_1X10, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TEN, }, =20 }; diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index 4f9e9a5ed4d1..5c7a10c9a2a5 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -155,49 +155,49 @@ static struct isc_format sama7g5_formats_list[] =3D { { .fourcc =3D V4L2_PIX_FMT_SBGGR10, .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TEN, .cfa_baycfg =3D ISC_BAY_CFG_RGRG, }, { .fourcc =3D V4L2_PIX_FMT_SGBRG10, .mbus_code =3D MEDIA_BUS_FMT_SGBRG10_1X10, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TEN, .cfa_baycfg =3D ISC_BAY_CFG_GBGB, }, { .fourcc =3D V4L2_PIX_FMT_SGRBG10, .mbus_code =3D MEDIA_BUS_FMT_SGRBG10_1X10, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TEN, .cfa_baycfg =3D ISC_BAY_CFG_GRGR, }, { .fourcc =3D V4L2_PIX_FMT_SRGGB10, .mbus_code =3D MEDIA_BUS_FMT_SRGGB10_1X10, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TEN, .cfa_baycfg =3D ISC_BAY_CFG_RGRG, }, { .fourcc =3D V4L2_PIX_FMT_SBGGR12, .mbus_code =3D MEDIA_BUS_FMT_SBGGR12_1X12, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TWELVE, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TWELVE, .cfa_baycfg =3D ISC_BAY_CFG_BGBG, }, { .fourcc =3D V4L2_PIX_FMT_SGBRG12, .mbus_code =3D MEDIA_BUS_FMT_SGBRG12_1X12, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TWELVE, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TWELVE, .cfa_baycfg =3D ISC_BAY_CFG_GBGB, }, { .fourcc =3D V4L2_PIX_FMT_SGRBG12, .mbus_code =3D MEDIA_BUS_FMT_SGRBG12_1X12, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TWELVE, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TWELVE, .cfa_baycfg =3D ISC_BAY_CFG_GRGR, }, { .fourcc =3D V4L2_PIX_FMT_SRGGB12, .mbus_code =3D MEDIA_BUS_FMT_SRGGB12_1X12, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TWELVE, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TWELVE, .cfa_baycfg =3D ISC_BAY_CFG_RGRG, }, { @@ -223,7 +223,7 @@ static struct isc_format sama7g5_formats_list[] =3D { { .fourcc =3D V4L2_PIX_FMT_Y10, .mbus_code =3D MEDIA_BUS_FMT_Y10_1X10, - .pfe_cfg0_bps =3D ISC_PFG_CFG0_BPS_TEN, + .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TEN, }, }; =20 --=20 2.34.1 From nobody Sat Jul 25 00:56:37 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB80D4C9566; Tue, 21 Jul 2026 10:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629772; cv=none; b=hgXp8afPxz7V3NxpwJqzV3yHVIwdi0r0mBy5f7czd9R+dbkLhGKWaTccuzYBZuJoEMl/15Z8a/PDLGKK/j+Nc3moO7OpPcAdGcF1FEn+zZczSdWNcYd19NSm+sgH18nQF2QU6n4KWrJm24ItyPwshESeR8FsPd406jFl1qVldqw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629772; c=relaxed/simple; bh=qxWdVD0AsoiU45oXdsmwcyX0G+gw2bxgoYJjzFSHfZs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=p8PZn8hEGqccQBCO6KQxSeL4vBVwfnVxGyJRDChb5Njmin91C7eoM5O/gnYdNaKXUvWZk37WPa8TEl2D1897Rv2NuiUTKPexekN1+MIO82r/0M//K6UKgPKFmQy33VqgXK2XlYLbFkOz9nI7YC82aH25aFPs4tzHERZ6XcPZF38= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=WO9VSj5c; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="WO9VSj5c" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1784629773; x=1816165773; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=qxWdVD0AsoiU45oXdsmwcyX0G+gw2bxgoYJjzFSHfZs=; b=WO9VSj5c2n3JG9cjJWJfOdsxbmNxwPtW//JLj4ltnzi7mTRQeeeloQhi mqWBvupeB05pUut5eAPeo/I3qk+gju/XkXDCzTal5OX80Nw0BXdqORWqx 9ORzPL3keWXV/C5Ul8gojHaA3D9+ELUirhrP/NRMg1qerE4cmZNTJBD9V MbP5FWNUYqsDKWvxCqA89CWExHL26OJTDAIj4bSGOzkGmsG5jnrieaJ6I gyZdw1aHpMwzaBQMUw1PWKM9fz0zCwNsmley4LxD1WtoMdqJpBqT1Q6Fm XMeoKpQftlnrA1Chywf3DizHOdROzOpB5M28XDxl5lnin/ljggwYd0u5e Q==; X-CSE-ConnectionGUID: daZRHHOSQpCoww4GMMvSvw== X-CSE-MsgGUID: gBOkENhXQTqVXfaCUw7KZQ== X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="61253565" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Jul 2026 03:29:33 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 21 Jul 2026 03:29:30 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 21 Jul 2026 03:29:26 -0700 From: Balakrishnan Sambath Date: Tue, 21 Jul 2026 15:59:02 +0530 Subject: [PATCH v3 08/10] media: microchip-isc: fix PM runtime leak in AWB work handler Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260721-balki-isc-prefix-fixes-v1-v3-8-ffe10640a2d9@microchip.com> References: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> In-Reply-To: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab CC: Hans Verkuil , Sakari Ailus , , , Balakrishnan Sambath , X-Mailer: b4 0.14.3 Early return when streaming stops skips pm_runtime_put_sync(), leaking the reference and preventing runtime suspend. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath Reviewed-by: Eugen Hristev Reviewed-by. --- drivers/media/platform/microchip/microchip-isc-base.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 4e87e5f45ac4..1a9b97edfa32 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -1432,7 +1432,7 @@ static void isc_awb_work(struct work_struct *w) /* streaming is not active anymore */ if (isc->stop) { mutex_unlock(&isc->awb_mutex); - return; + goto out_pm_put; } =20 isc_update_profile(isc); @@ -1443,6 +1443,7 @@ static void isc_awb_work(struct work_struct *w) if (ctrls->awb) regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ); =20 +out_pm_put: pm_runtime_put_sync(isc->dev); } =20 --=20 2.34.1 From nobody Sat Jul 25 00:56:37 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E51CC4CA285; Tue, 21 Jul 2026 10:29:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629776; cv=none; b=u1dJnwx7v+nQMqY8HxbQ0BK1jj7EsLofSkWYdFd52VPMuJWKZ4V6TFR3I0JxNfGkqlzsSvZYPdQwg0AFoOXnCEIw7zr+eBQdxOw04M5RRFLeOE3suuvn03tyH0HtKe4VaQAg1d5KwD6XxCCsFemEGm3jYPWwtU9uv/c70DqWnAQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629776; c=relaxed/simple; bh=0CEYSN3tOv1b+wP3879Etl0FWT15ojdlVrF40Chgo1k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=paxPoJMm/xSkyAP2iUK5i1wyHFTYS7mDFBNJRzG8AZxhYfUWS4FmK3Zw1flBqXTTREjGFapIOEt7zZ5yVinkpyGJVZrDMYjOxHnlj/3fcknTrIAmhHb5nhW/pZtnVslXaf+vm8jkPi12gSn1WATsGow4+l3Kk66/7VVOE60lVsA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=IzNn2/56; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="IzNn2/56" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1784629774; x=1816165774; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=0CEYSN3tOv1b+wP3879Etl0FWT15ojdlVrF40Chgo1k=; b=IzNn2/56KkuUwQQSbqTNhmvTNfXI3M/nd3xv94IEoUab4ByUFqjQkje6 t4OE23s6HRiOXK3kaLpIbuROqX+0bemlURrV3eTQB2pF9QDZpdJ5rZrB+ RcYkEDUCUJO9TckZ4FDxBt65BHHbOb5TdZyvrizPbdQhlk6d1Lr3hw0lC xENFNPHAsbUNhS1m0qMZ2+k6hOqKUYeu7V/T0WCku1j+eOtEBLUi4AoUD o7ZThqo+bV11AIfDqmtI/jLPDEo2Jlf0WY0HWUyFsZ9kXIZbm9HIVG3P7 l0AR3F0ohoWL/ZYYA1Gv7qroOFgBhrrPMM87invd5Iv53jk9NhAODahck Q==; X-CSE-ConnectionGUID: Cbii2dOCRxWiBZ2KAIw4Tg== X-CSE-MsgGUID: F3FVZ1pvQ/qO1X1/txstFQ== X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="228086577" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2026 03:29:34 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 21 Jul 2026 03:29:33 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 21 Jul 2026 03:29:30 -0700 From: Balakrishnan Sambath Date: Tue, 21 Jul 2026 15:59:03 +0530 Subject: [PATCH v3 09/10] media: microchip-isc: fix SBGGR10 Bayer pattern Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260721-balki-isc-prefix-fixes-v1-v3-9-ffe10640a2d9@microchip.com> References: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> In-Reply-To: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab CC: Hans Verkuil , Sakari Ailus , , , Balakrishnan Sambath , X-Mailer: b4 0.14.3 SBGGR10 was mapped to ISC_BAY_CFG_RGRG instead of ISC_BAY_CFG_BGBG, causing red/blue channel swap. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath Reviewed-by: Eugen Hristev Reviewed-by. --- drivers/media/platform/microchip/microchip-sama5d2-isc.c | 2 +- drivers/media/platform/microchip/microchip-sama7g5-isc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-sama5d2-isc.c b/dri= vers/media/platform/microchip/microchip-sama5d2-isc.c index 5c59a692b30e..99fda1968a32 100644 --- a/drivers/media/platform/microchip/microchip-sama5d2-isc.c +++ b/drivers/media/platform/microchip/microchip-sama5d2-isc.c @@ -147,7 +147,7 @@ static struct isc_format sama5d2_formats_list[] =3D { .fourcc =3D V4L2_PIX_FMT_SBGGR10, .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TEN, - .cfa_baycfg =3D ISC_BAY_CFG_RGRG, + .cfa_baycfg =3D ISC_BAY_CFG_BGBG, }, { .fourcc =3D V4L2_PIX_FMT_SGBRG10, diff --git a/drivers/media/platform/microchip/microchip-sama7g5-isc.c b/dri= vers/media/platform/microchip/microchip-sama7g5-isc.c index 5c7a10c9a2a5..4e1fbb83bc97 100644 --- a/drivers/media/platform/microchip/microchip-sama7g5-isc.c +++ b/drivers/media/platform/microchip/microchip-sama7g5-isc.c @@ -156,7 +156,7 @@ static struct isc_format sama7g5_formats_list[] =3D { .fourcc =3D V4L2_PIX_FMT_SBGGR10, .mbus_code =3D MEDIA_BUS_FMT_SBGGR10_1X10, .pfe_cfg0_bps =3D ISC_PFE_CFG0_BPS_TEN, - .cfa_baycfg =3D ISC_BAY_CFG_RGRG, + .cfa_baycfg =3D ISC_BAY_CFG_BGBG, }, { .fourcc =3D V4L2_PIX_FMT_SGBRG10, --=20 2.34.1 From nobody Sat Jul 25 00:56:37 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8CE747F2F8; Tue, 21 Jul 2026 10:29:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629780; cv=none; b=dS3LXE8QFXLdgB654ET38V5mpgJ3OtiRXrLoTRH7HtEdlDDPLrUpY85TZkdDbTY3JgTaIKdxljaDcLkzaHjq9u7omKW9e8fQxYwTUWrMYkBFm9ZriZzosXDoqKMfh/mBOPy+CE2YjL75vzX1L/K6dSsMAZCvy5pLiXTdv5kHdiI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784629780; c=relaxed/simple; bh=aogjYpbl1dNrqWrEblawQlhCqOx5bUkFeqGH/Mw1oYk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=cx0mMPOdDH1PNxzqFPdupUL41sDie+VTy0NdT+rJUFmOBIVfE8efaiTrcj+JbHUe/VrHKOh7WQem5wVb+EqyDUpUM7Bxrj1H+vZvmcGtdeeO2+MSgHsYibeIQfxoc9HcO2tEirrU4ttFrUEa1NTjukSXk7y6JH7lmDl2eeMSjwE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ff1s0h7/; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ff1s0h7/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1784629781; x=1816165781; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=aogjYpbl1dNrqWrEblawQlhCqOx5bUkFeqGH/Mw1oYk=; b=ff1s0h7/hcK+ojrRgWMY9TT/YE/k40eZj1m6BbdHIRwfHVRTJ1Rud5g7 033D34EGt4fzuByHwqTC9+C9HaGCDSSCpq8eV8nmJfyilIiizvJ6H0JmM xG6uzeMAPasNUtd7FDQyh/DVkQ03M0Pd+mTx1LrImD+AvXiTXleL4hX5W +k1rVHu4wh23b2QexhAMVC9G8IMEuiyoekx5mNIXP+xnwFNikGov2A0XI 2wUp3+skVRQS/b1YtnfRBCrQPie8TxmNducxoAiK7QT9MMha2ISMrvCgh f1O+wnL0NdcAbARftW1iSFq3FAcWQOzjSv/HAPBr6CO+JhCmSMBTgqwzu g==; X-CSE-ConnectionGUID: D2c1vx3nQ1+SdgTrhpwxSg== X-CSE-MsgGUID: jvlARwtjReWEgPS37W3Otw== X-IronPort-AV: E=Sophos;i="6.25,176,1779174000"; d="scan'208";a="61253572" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 21 Jul 2026 03:29:40 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 21 Jul 2026 03:29:37 -0700 Received: from [127.0.0.1] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 21 Jul 2026 03:29:34 -0700 From: Balakrishnan Sambath Date: Tue, 21 Jul 2026 15:59:04 +0530 Subject: [PATCH v3 10/10] media: microchip-isc: fix WB offset and gain register field masking Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260721-balki-isc-prefix-fixes-v1-v3-10-ffe10640a2d9@microchip.com> References: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> In-Reply-To: <20260721-balki-isc-prefix-fixes-v1-v3-0-ffe10640a2d9@microchip.com> To: Eugen Hristev , Mauro Carvalho Chehab CC: Hans Verkuil , Sakari Ailus , , , Balakrishnan Sambath , X-Mailer: b4 0.14.3 ISC_WB_O_* and ISC_WB_G_* each pack two 13-bit fields. A negative offset sign-extends and corrupts the adjacent field. Add masks for the two fields and write them with FIELD_PREP(), which masks each value into its field, so sign extension can no longer bleed across. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath Reviewed-by. --- .../media/platform/microchip/microchip-isc-base.c | 21 +++++++++++++----= ---- .../media/platform/microchip/microchip-isc-regs.h | 6 ++++++ 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index 1a9b97edfa32..3d25d7d28652 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -62,18 +62,23 @@ static inline void isc_update_awb_ctrls(struct isc_devi= ce *isc) =20 /* In here we set our actual hw pipeline config */ =20 + /* + * Each register packs two 13-bit fields. FIELD_PREP() masks every + * value into its field, so sign extension of a negative offset can + * no longer bleed into the adjacent field. + */ regmap_write(isc->regmap, ISC_WB_O_RGR, - ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); + FIELD_PREP(ISC_WB_O_LO, ctrls->offset[ISC_HIS_CFG_MODE_R]) | + FIELD_PREP(ISC_WB_O_HI, ctrls->offset[ISC_HIS_CFG_MODE_GR])); regmap_write(isc->regmap, ISC_WB_O_BGB, - ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); + FIELD_PREP(ISC_WB_O_LO, ctrls->offset[ISC_HIS_CFG_MODE_B]) | + FIELD_PREP(ISC_WB_O_HI, ctrls->offset[ISC_HIS_CFG_MODE_GB])); regmap_write(isc->regmap, ISC_WB_G_RGR, - ctrls->gain[ISC_HIS_CFG_MODE_R] | - (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); + FIELD_PREP(ISC_WB_G_LO, ctrls->gain[ISC_HIS_CFG_MODE_R]) | + FIELD_PREP(ISC_WB_G_HI, ctrls->gain[ISC_HIS_CFG_MODE_GR])); regmap_write(isc->regmap, ISC_WB_G_BGB, - ctrls->gain[ISC_HIS_CFG_MODE_B] | - (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); + FIELD_PREP(ISC_WB_G_LO, ctrls->gain[ISC_HIS_CFG_MODE_B]) | + FIELD_PREP(ISC_WB_G_HI, ctrls->gain[ISC_HIS_CFG_MODE_GB])); } =20 static inline void isc_reset_awb_ctrls(struct isc_device *isc) diff --git a/drivers/media/platform/microchip/microchip-isc-regs.h b/driver= s/media/platform/microchip/microchip-isc-regs.h index 9ddbbb6dd68b..fe145b142b82 100644 --- a/drivers/media/platform/microchip/microchip-isc-regs.h +++ b/drivers/media/platform/microchip/microchip-isc-regs.h @@ -149,6 +149,12 @@ /* ISC White Balance Gain for B, GB Register */ #define ISC_WB_G_BGB 0x0000006c =20 +/* Each WB offset/gain register packs two 13-bit fields, low and high */ +#define ISC_WB_O_LO GENMASK(12, 0) /* R or B offset [12:0] */ +#define ISC_WB_O_HI GENMASK(28, 16) /* GR or GB offset [28:16] */ +#define ISC_WB_G_LO GENMASK(12, 0) /* R or B gain [12:0] */ +#define ISC_WB_G_HI GENMASK(28, 16) /* GR or GB gain [28:16] */ + /* ISC Color Filter Array Control Register */ #define ISC_CFA_CTRL 0x00000070 =20 --=20 2.34.1