From nobody Sat Jul 25 01:52:43 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FFCF41166D for ; Mon, 20 Jul 2026 21:52:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784584328; cv=none; b=Z5XhbP6YfvcuWvLTZZrcs0xR0fGNwgzUyV3BMVWZe9ZTJFL7P7M3peCeJLaQpnUrn3jFsLmCngqsSCPLtfwRTqx1KOUVSljJN3bK36MQvkN25rJ9/vx/awwp2+XMJsIVxBD0xZgmbntfYVTKSRLIbuXMG3zwI+AVG37LvSsZAa8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784584328; c=relaxed/simple; bh=nsWNAjzhGaZ2+5CodHc/2ttpM4veQVjfWfQm2Xmc8jk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I3wvuG+uKH+uk5voIcXEFKj/1e7aUOj5PFY3yhBHeY06TjH7A6dUheTbqxkezTtzwoGMte9C/rRYzunNConJaTWUDw41qsagyqMMPzHDtEnay39MAmH4oQDajuHosGim1sLrCxJFJM2IXj3kGHohSex3e72oyesPQ175sMq+RmM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=UAF26TqW; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="UAF26TqW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1784584325; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BAzHEt/JUKcSSo+NrPYMNWpznNd/HnyKFTRe4NDoHyE=; b=UAF26TqWC9V/EUZuVEYHPsKyOHl9kbnv1AFQDP98XcVke2Lgo2ilmdo95mFfnpBweQwNO2 UyDxqib50JlL9x4m4cc1vnS+3nZXkVVAyEhjTVVGxH41Gt0w0jwC2WBJQ9VA2Q9sSFwhyE MZhTrxNfYsWLe7IOqVKyafkPj94dFzI= Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-132-PGvBqEc6OX6dfgpXMwxmiQ-1; Mon, 20 Jul 2026 17:52:00 -0400 X-MC-Unique: PGvBqEc6OX6dfgpXMwxmiQ-1 X-Mimecast-MFC-AGG-ID: PGvBqEc6OX6dfgpXMwxmiQ_1784584318 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id DCF89195E924; Mon, 20 Jul 2026 21:51:57 +0000 (UTC) Received: from GoldenWind.redhat.com (unknown [10.22.88.114]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 6BEC51800764; Mon, 20 Jul 2026 21:51:55 +0000 (UTC) From: Lyude Paul To: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: "Faith Ekstrand" , "Dave Airlie" , "Leandro Ribeiro" , "Maarten Lankhorst" , "Marco Crivellari" , "Kees Cook" , "Simona Vetter" , "Pekka Paalanen" , "David Airlie" , "Thomas Zimmermann" , "Maxime Ripard" , "Danilo Krummrich" , "Daniel Stone" , "James Jones" , "Lyude Paul" Subject: [PATCH v3 1/3] drm/nouveau/kms/nv50-: Add .blend_modes to nv50_wndw_func Date: Mon, 20 Jul 2026 17:36:16 -0400 Message-ID: <20260720215058.398210-2-lyude@redhat.com> In-Reply-To: <20260720215058.398210-1-lyude@redhat.com> References: <20260720215058.398210-1-lyude@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Content-Type: text/plain; charset="utf-8" At the moment, we currently (incorrectly) only expose a blend property on the plane if we have a nv50_wndw_func->blend_set function for the given wndw type. But we need to expose a blend property for all types of planes that can display color formats with an alpha channel. Prepare for doing this by introducing a way of looking up the supported blend modes for a type of wndw by introducing .blend_modes, which describes all possible blending modes nouveau currently supports for a type of wndw. Signed-off-by: Lyude Paul Fixes: 860e748bddcc ("drm: ensure blend mode supported if pixel format with= alpha exposed") --- V3: * Don't forget to specify .blend_modes for base. drivers/gpu/drm/nouveau/dispnv50/base.h | 6 ++++++ drivers/gpu/drm/nouveau/dispnv50/base507c.c | 1 + drivers/gpu/drm/nouveau/dispnv50/base827c.c | 1 + drivers/gpu/drm/nouveau/dispnv50/base907c.c | 1 + drivers/gpu/drm/nouveau/dispnv50/curs507a.c | 3 +++ drivers/gpu/drm/nouveau/dispnv50/wndw.h | 10 ++++++++++ drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 1 + drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 1 + drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c | 1 + drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c | 1 + 10 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base.h b/drivers/gpu/drm/nouv= eau/dispnv50/base.h index 085bd3aeb40b6..fbfd62d8fc798 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base.h +++ b/drivers/gpu/drm/nouveau/dispnv50/base.h @@ -1,5 +1,7 @@ #ifndef __NV50_KMS_BASE_H__ #define __NV50_KMS_BASE_H__ +#include + #include "wndw.h" =20 int base507c_new(struct nouveau_drm *, int, s32, struct nv50_wndw **); @@ -24,4 +26,8 @@ extern const struct nv50_wndw_func base907c; int base917c_new(struct nouveau_drm *, int, s32, struct nv50_wndw **); =20 int nv50_base_new(struct nouveau_drm *, int head, struct nv50_wndw **); + +/* The only blend mode supported by base channels */ +#define BASE_BLEND_MODES BIT(DRM_MODE_BLEND_PIXEL_NONE) + #endif diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/= nouveau/dispnv50/base507c.c index a431f6c5f6fa9..41b648ab3c5e5 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -297,6 +297,7 @@ base507c =3D { .image_set =3D base507c_image_set, .image_clr =3D base507c_image_clr, .update =3D base507c_update, + .blend_modes =3D BASE_BLEND_MODES, }; =20 int diff --git a/drivers/gpu/drm/nouveau/dispnv50/base827c.c b/drivers/gpu/drm/= nouveau/dispnv50/base827c.c index 4545cc5f3a14b..6c290324b4f3e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base827c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base827c.c @@ -93,6 +93,7 @@ base827c =3D { .image_set =3D base827c_image_set, .image_clr =3D base507c_image_clr, .update =3D base507c_update, + .blend_modes =3D BASE_BLEND_MODES, }; =20 int diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/= nouveau/dispnv50/base907c.c index 4a2d5a259e15b..a94d8350224b6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -205,6 +205,7 @@ base907c =3D { .image_set =3D base907c_image_set, .image_clr =3D base507c_image_clr, .update =3D base507c_update, + .blend_modes =3D BASE_BLEND_MODES, }; =20 int diff --git a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c b/drivers/gpu/drm/= nouveau/dispnv50/curs507a.c index 1a889139cb053..5f2ff40388e7f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c +++ b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c @@ -29,6 +29,7 @@ #include =20 #include +#include #include =20 bool @@ -164,6 +165,8 @@ curs507a_wndw =3D { .acquire =3D curs507a_acquire, .release =3D curs507a_release, .prepare =3D curs507a_prepare, + // TODO: Cursors also support premulti, but we haven't hooked it up anywh= ere yet. + .blend_modes =3D BIT(DRM_MODE_BLEND_COVERAGE), }; =20 int diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouv= eau/dispnv50/wndw.h index 90d100514bef2..81af5c3369d4c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -1,6 +1,8 @@ #ifndef __NV50_KMS_WNDW_H__ #define __NV50_KMS_WNDW_H__ #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane) +#include + #include "disp.h" #include "atom.h" #include "lut.h" @@ -74,6 +76,7 @@ struct nv50_wndw_func { int (*image_clr)(struct nv50_wndw *); int (*scale_set)(struct nv50_wndw *, struct nv50_wndw_atom *); int (*blend_set)(struct nv50_wndw *, struct nv50_wndw_atom *); + unsigned int blend_modes; =20 int (*update)(struct nv50_wndw *, u32 *interlock); }; @@ -139,4 +142,11 @@ int wndwca7e_new(struct nouveau_drm *, enum drm_plane_= type, int, s32, =20 int nv50_wndw_new(struct nouveau_drm *, enum drm_plane_type, int index, struct nv50_wndw **); + +/* A set of blend modes supported by all wndws */ +#define WNDW_BLEND_MODES \ + BIT(DRM_MODE_BLEND_COVERAGE) \ + | BIT(DRM_MODE_BLEND_PREMULTI) \ + | BIT(DRM_MODE_BLEND_PIXEL_NONE) + #endif diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/= nouveau/dispnv50/wndwc37e.c index 554c4f91f8bec..7ab4d532118ee 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -343,6 +343,7 @@ wndwc37e =3D { .image_set =3D wndwc37e_image_set, .image_clr =3D wndwc37e_image_clr, .blend_set =3D wndwc37e_blend_set, + .blend_modes =3D WNDW_BLEND_MODES, .update =3D wndwc37e_update, }; =20 diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/= nouveau/dispnv50/wndwc57e.c index d1ca51aae58cd..e220f43b5bca7 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -231,6 +231,7 @@ wndwc57e =3D { .image_set =3D wndwc57e_image_set, .image_clr =3D wndwc37e_image_clr, .blend_set =3D wndwc37e_blend_set, + .blend_modes =3D WNDW_BLEND_MODES, .update =3D wndwc37e_update, }; =20 diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c b/drivers/gpu/drm/= nouveau/dispnv50/wndwc67e.c index 52af293c98f4a..580cf7abd8193 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c @@ -95,6 +95,7 @@ wndwc67e =3D { .image_set =3D wndwc67e_image_set, .image_clr =3D wndwc37e_image_clr, .blend_set =3D wndwc37e_blend_set, + .blend_modes =3D WNDW_BLEND_MODES, .update =3D wndwc37e_update, }; =20 diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c b/drivers/gpu/drm/= nouveau/dispnv50/wndwca7e.c index 2cec8cfbd5461..d65ec438b434f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c @@ -231,6 +231,7 @@ wndwca7e =3D { .image_set =3D wndwca7e_image_set, .image_clr =3D wndwca7e_image_clr, .blend_set =3D wndwc37e_blend_set, + .blend_modes =3D WNDW_BLEND_MODES, .update =3D wndwc37e_update, }; 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Mon, 20 Jul 2026 17:52:10 -0400 X-MC-Unique: WZdwZoT7NWSdinl9n9f_vA-1 X-Mimecast-MFC-AGG-ID: WZdwZoT7NWSdinl9n9f_vA_1784584328 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 4546C1964CD2; Mon, 20 Jul 2026 21:52:08 +0000 (UTC) Received: from GoldenWind.redhat.com (unknown [10.22.88.114]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id DA1F1180075F; Mon, 20 Jul 2026 21:52:05 +0000 (UTC) From: Lyude Paul To: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: "Faith Ekstrand" , "Dave Airlie" , "Leandro Ribeiro" , "Maarten Lankhorst" , "Marco Crivellari" , "Kees Cook" , "Simona Vetter" , "Pekka Paalanen" , "David Airlie" , "Thomas Zimmermann" , "Maxime Ripard" , "Danilo Krummrich" , "Jani Nikula" , "Daniel Stone" , "James Jones" , "Lyude Paul" Subject: [PATCH v3 2/3] drm/nouveau/kms/nv50-: Introduce nv50_wndw_default_state() Date: Mon, 20 Jul 2026 17:36:17 -0400 Message-ID: <20260720215058.398210-3-lyude@redhat.com> In-Reply-To: <20260720215058.398210-1-lyude@redhat.com> References: <20260720215058.398210-1-lyude@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Content-Type: text/plain; charset="utf-8" While we don't currently read-in the hardware state of planes, now that we're about to start exposing blend properties for all planes that can support alpha channels: We need to make sure that the initial atomic state for a wndw always starts off with a supported value in pixel_blend_mode. The easiest way to do this is to introduce a nv50_wndw_default_state() function, and use it in nv50_display_read_hw_state() - and use that function to enforce a valid value for pixel_blend_mode during driver startup. Signed-off-by: Lyude Paul Fixes: 860e748bddcc ("drm: ensure blend mode supported if pixel format with= alpha exposed") --- V3: * Fix incorrect bitmask checking in nv50_wndw_default_state() drivers/gpu/drm/nouveau/dispnv50/disp.c | 4 ++++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/nouveau/dispnv50/wndw.h | 1 + 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouv= eau/dispnv50/disp.c index 364227f5456f1..2c66e480b5116 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -2768,6 +2768,7 @@ nv50_display_read_hw_state(struct nouveau_drm *drm) { struct drm_device *dev =3D drm->dev; struct drm_encoder *encoder; + struct drm_plane *plane; struct drm_modeset_acquire_ctx ctx; struct nv50_disp *disp =3D nv50_disp(dev); int ret; @@ -2781,6 +2782,9 @@ nv50_display_read_hw_state(struct nouveau_drm *drm) nv50_display_read_hw_or_state(dev, disp, nouveau_encoder(encoder)); } =20 + drm_for_each_plane(plane, dev) + nv50_wndw_default_state(nv50_wndw(plane)); + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); } =20 diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouv= eau/dispnv50/wndw.c index 2635458d52acc..dfa1ba45acd99 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -848,6 +848,28 @@ static const u64 nv50_cursor_format_modifiers[] =3D { DRM_FORMAT_MOD_INVALID, }; =20 +/* + * Setup defaults for the atomic wndw state + */ +void +nv50_wndw_default_state(struct nv50_wndw *wndw) +{ + struct nv50_wndw_atom *armw =3D nv50_wndw_atom(wndw->plane.state); + const unsigned int blend_modes =3D wndw->func->blend_modes; + + drm_modeset_lock_assert_held(&wndw->plane.mutex); + + /* Ensure the plane's atomic state didn't default to a pixel_blend_mode w= e don't support */ + if (blend_modes && (!(BIT(armw->state.pixel_blend_mode) & blend_modes))) { + if (blend_modes & BIT(DRM_MODE_BLEND_COVERAGE)) + armw->state.pixel_blend_mode =3D DRM_MODE_BLEND_COVERAGE; + else if (blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) + armw->state.pixel_blend_mode =3D DRM_MODE_BLEND_PREMULTI; + else if (blend_modes & BIT(DRM_MODE_BLEND_PIXEL_NONE)) + armw->state.pixel_blend_mode =3D DRM_MODE_BLEND_PIXEL_NONE; + } +} + int nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, enum drm_plane_type type, const char *name, int index, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouv= eau/dispnv50/wndw.h index 81af5c3369d4c..13f06b7b67611 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -46,6 +46,7 @@ void nv50_wndw_flush_clr(struct nv50_wndw *, u32 *interlo= ck, bool flush, struct nv50_wndw_atom *); void nv50_wndw_ntfy_enable(struct nv50_wndw *, struct nv50_wndw_atom *); int nv50_wndw_wait_armed(struct nv50_wndw *, struct nv50_wndw_atom *); +void nv50_wndw_default_state(struct nv50_wndw *wndw); =20 struct nv50_wndw_func { int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw, --=20 2.55.0 From nobody Sat Jul 25 01:52:43 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B62441166D for ; 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Mon, 20 Jul 2026 17:52:20 -0400 X-MC-Unique: LrQGC3WCNme6NkFi0q2sSg-1 X-Mimecast-MFC-AGG-ID: LrQGC3WCNme6NkFi0q2sSg_1784584338 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id A7EA71805EC1; Mon, 20 Jul 2026 21:52:18 +0000 (UTC) Received: from GoldenWind.redhat.com (unknown [10.22.88.114]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 39EF2180075F; Mon, 20 Jul 2026 21:52:16 +0000 (UTC) From: Lyude Paul To: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: "Faith Ekstrand" , "Dave Airlie" , "Leandro Ribeiro" , "Maarten Lankhorst" , "Kees Cook" , "Marco Crivellari" , "Simona Vetter" , "Pekka Paalanen" , "David Airlie" , "Thomas Zimmermann" , "Maxime Ripard" , "Danilo Krummrich" , "Jani Nikula" , "Daniel Stone" , "James Jones" , "Lyude Paul" Subject: [PATCH v3 3/3] drm/nouveau/kms/nv50-: Unconditionally create blend_mode prop for wndws Date: Mon, 20 Jul 2026 17:36:18 -0400 Message-ID: <20260720215058.398210-4-lyude@redhat.com> In-Reply-To: <20260720215058.398210-1-lyude@redhat.com> References: <20260720215058.398210-1-lyude@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Content-Type: text/plain; charset="utf-8" Since the commit mentioned down below, it looks like we've been triggering this WARN_ON(): [ 31.477009] ------------[ cut here ]------------ [ 31.477012] [PLANE:66:curs-0] pixel format with alpha exposed but blend mode not setup [ 31.477014] WARNING: drivers/gpu/drm/drm_mode_config.c:872 at drm_mode_config_validate+0x38c/0x4c0, CPU#1: modprobe/1264 [ 31.477125] CPU: 1 UID: 0 PID: 1264 Comm: modprobe Not tainted 7.2.0-rc2Lyude-Test+ #1 PREEMPT(lazy) [ 31.477129] Hardware name: Micro-Star International Co., Ltd. MS-7A39/A320M GAMING PRO (MS-7A39), BIOS 1.M4 05/10/2023 [ 31.477132] RIP: 0010:drm_mode_config_validate+0x394/0x4c0 [ 31.477136] Code: 41 3b 9e 80 00 00 00 73 bd 49 8b 46 78 8b 3c 98 e8 c1 3d ff ff 80 78 14 00 74 e1 48 8d 3d 64 e6 e7 01 49 8b 56 18 41 8b 76 50 <67> 48 0f b9 3a 49 8b 46 08 4c 8d 70 f8 49 39 c5 75 97 8b 95 b8 02 [ 31.477139] RSP: 0018:ffffd48e053bb7f8 EFLAGS: 00010202 [ 31.477143] RAX: ffffffffaf1da9c0 RBX: 0000000000000000 RCX: 000000000= 0000034 [ 31.477145] RDX: ffff8cd883c1feb0 RSI: 0000000000000042 RDI: ffffffffb= 069f840 [ 31.477148] RBP: ffff8cd88ea3d800 R08: 0000000034325241 R09: ffff8cd88= ea3dac0 [ 31.477150] R10: fffffaf5c4043600 R11: ffff8cd88004f600 R12: 000000000= 0000001 [ 31.477152] R13: ffff8cd88ea3da90 R14: ffff8cd88b9ec038 R15: ffff8cd88= ea3dab0 [ 31.477154] FS: 00007fb934898780(0000) GS:ffff8cd9f3a6a000(0000) knlG= S:0000000000000000 [ 31.477157] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 31.477160] CR2: 0000555efff79520 CR3: 0000000122cd5000 CR4: 000000000= 03506f0 [ 31.477162] Call Trace: [ 31.477165] [ 31.477168] ? nouveau_hwmon_init+0x2d6/0x330 [nouveau] [ 31.477346] drm_dev_register+0x19d/0x270 [ 31.477352] nouveau_drm_device_init+0x17a/0x230 [nouveau] [ 31.477523] nouveau_drm_probe+0x13d/0x1e0 [nouveau] [ 31.477690] local_pci_probe+0x3e/0x90 [ 31.477697] pci_call_probe+0x59/0x190 [ 31.477702] ? srso_return_thunk+0x5/0x5f [ 31.477706] ? pci_match_device+0x15a/0x180 [ 31.477710] ? pci_assign_irq+0x2d/0x160 [ 31.477714] pci_device_probe+0x95/0x160 [ 31.477719] call_driver_probe+0x26/0x100 [ 31.477724] ? driver_sysfs_add+0x59/0xd0 [ 31.477738] really_probe+0xcc/0x2c0 [ 31.477743] ? srso_return_thunk+0x5/0x5f [ 31.477749] __driver_probe_device+0x85/0x170 [ 31.477754] driver_probe_device+0x1f/0x90 [ 31.477760] ? __pfx___driver_attach+0x10/0x10 [ 31.477766] __driver_attach+0xcb/0x210 [ 31.477772] bus_for_each_dev+0x85/0xd0 [ 31.477779] bus_add_driver+0x13e/0x220 [ 31.477786] ? __pfx_init_module+0x10/0x10 [nouveau] [ 31.477979] driver_register+0x75/0xe0 [ 31.477984] ? srso_return_thunk+0x5/0x5f [ 31.477990] nouveau_drm_init+0x8b/0xff0 [nouveau] [ 31.478192] do_one_initcall+0x5d/0x300 [ 31.478204] do_init_module+0x86/0x290 [ 31.478212] init_module_from_file+0xd8/0x140 [ 31.478223] idempotent_init_module+0x114/0x310 [ 31.478233] __x64_sys_finit_module+0x71/0xe0 [ 31.478238] do_syscall_64+0xe2/0x630 [ 31.478252] ? srso_return_thunk+0x5/0x5f [ 31.478257] ? vfs_read+0x165/0x390 [ 31.478267] ? srso_return_thunk+0x5/0x5f [ 31.478271] ? srso_return_thunk+0x5/0x5f [ 31.478276] ? switch_fpu_return+0x52/0xe0 [ 31.478282] ? srso_return_thunk+0x5/0x5f [ 31.478286] ? arch_exit_to_user_mode_prepare.isra.0+0x7e/0x90 [ 31.478292] ? srso_return_thunk+0x5/0x5f [ 31.478296] ? do_syscall_64+0x11f/0x630 [ 31.478301] ? srso_return_thunk+0x5/0x5f [ 31.478305] ? arch_exit_to_user_mode_prepare.isra.0+0x7e/0x90 [ 31.478310] ? srso_return_thunk+0x5/0x5f [ 31.478314] ? do_syscall_64+0x11f/0x630 [ 31.478320] ? srso_return_thunk+0x5/0x5f [ 31.478324] ? arch_exit_to_user_mode_prepare.isra.0+0x7e/0x90 [ 31.478329] ? srso_return_thunk+0x5/0x5f [ 31.478334] ? srso_return_thunk+0x5/0x5f [ 31.478338] ? do_syscall_64+0x99/0x630 [ 31.478343] ? exc_page_fault+0x82/0x1c0 [ 31.478350] entry_SYSCALL_64_after_hwframe+0x76/0x7e [ 31.478355] RIP: 0033:0x7fb93410030d [ 31.478372] Code: ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d c3 5a 0f 00 f7 d8 64 89 01 48 [ 31.478375] RSP: 002b:00007ffc587ce738 EFLAGS: 00000246 ORIG_RAX: 0000= 000000000139 [ 31.478381] RAX: ffffffffffffffda RBX: 0000562f5fb3da60 RCX: 00007fb93= 410030d [ 31.478385] RDX: 0000000000000000 RSI: 0000562f5fb40590 RDI: 000000000= 000000d [ 31.478388] RBP: 00007ffc587ce7d0 R08: 0000000000000000 R09: 000000000= 0000000 [ 31.478391] R10: 0000000000000000 R11: 0000000000000246 R12: 0000562f5= fb40590 [ 31.478394] R13: 0000000000040000 R14: 0000562f5fb3db80 R15: 000000000= 0000009 [ 31.478404] [ 31.478407] ---[ end trace 0000000000000000 ]--- Fix it by making sure we unconditionally call drm_plane_create_blend_mode_property for all types of wndws, including those (such as cursors) without a blend_set function. Fixes: 860e748bddcc ("drm: ensure blend mode supported if pixel format with= alpha exposed") Signed-off-by: Lyude Paul --- V2: * Address Sashiko issue regarding pixel_blend_mode defaults * The cursor uses DRM_MODE_BLEND_COVERAGE, not DRM_MODE_BLEND_PIXEL_NONE * Start using the new blend_modes vtable entry Signed-off-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouv= eau/dispnv50/wndw.c index dfa1ba45acd99..15a322422f4e6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -930,13 +930,6 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, stru= ct drm_device *dev, ret =3D drm_plane_create_alpha_property(&wndw->plane); if (ret) return ret; - - ret =3D drm_plane_create_blend_mode_property(&wndw->plane, - BIT(DRM_MODE_BLEND_PIXEL_NONE) | - BIT(DRM_MODE_BLEND_PREMULTI) | - BIT(DRM_MODE_BLEND_COVERAGE)); - if (ret) - return ret; } else { ret =3D drm_plane_create_zpos_immutable_property(&wndw->plane, nv50_wndw_zpos_default(&wndw->plane)); @@ -944,6 +937,17 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, stru= ct drm_device *dev, return ret; } =20 + /* + * DRM requires that we have a blend mode property for any type of plane = that exposes color + * formats with an alpha channel. So do this, even if we don't actually h= ave control for the + * blend property hooked up with blend_set. + */ + if (func->blend_modes) { + ret =3D drm_plane_create_blend_mode_property(&wndw->plane, func->blend_m= odes); + if (ret) + return ret; + } + return 0; } =20 --=20 2.55.0