From nobody Sat Jul 25 01:52:22 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 990DA3B7B70; Mon, 20 Jul 2026 20:14:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784578479; cv=none; b=ga9+zqJ07NHg0yBCNk02bwFRJvGQ85Jc0Sofuj6qnais//B7vQcHgQLAcBJvFyK9Jq8YRI9yGLKiOZHSlrEF/8JJfR9YPF9kjcOIgLAi0FBgiRioDOpbiJOAGjfKL9xv32n0Paoo5UndUb1fB+OWS1x/0PuiMVUkOcYNEpbq7ug= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784578479; c=relaxed/simple; bh=ebhUd/B6oI8gob8xTVXousjvzYIa3YEIfz2b6IXL5pU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XjHHZDcexc2Aq+jkwVAcDPlJG5mUHmfOLARbt0y0K9sZyYYasbO5ToKqOmLZn3kKXw3qzkLcewCJ7q4EZofSHZAdkEqgYnrXD96qnJ3n/qK2/GrEpJ6Ja2oUN2I+vQlzpJx9R2IB1yjmVHlCBLvaVbTSv4rlwgm2jaf5zaZlijA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=g3DJl7kR; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="g3DJl7kR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5D4011F00A3E; Mon, 20 Jul 2026 20:14:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784578477; bh=2KWGX0x3qOioC14dHP2ZBC/2H5Ygy5xXkmlzDj6IWr8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=g3DJl7kR6pIXjGwod0yixQ5XLH7dljYTxTzBoLcR/VbrbO7YeYda9QqTMfyJvWO85 wwNIsHOnwRVHQrFFpP9qM8UTMbv2dDmXquTwzdar8SzobGiwNCPVQA5zS7EYDZBtIy B+rLysrKKdcjxe3ZfSTatsgRpc3Tn66EhLQggGXRTYha8UYynXQyms9/kFDlEGDbkD C8etwMWrwyXMbBPyXNvjuyZyIVavHEMwUEsofm2Xr5Bi4vRD+gZ4STjVSqJQFxcG7b JCuWJPplZ4qkurwXRxSmbHhxI8dszj8qqWVp6556luCxueep9R2p9UIc1Z9QlEqEVU njbB8qhumwlLg== From: Dinh Nguyen To: bp@alien8.de, tony.luck@intel.com Cc: dinguyen@kernel.org, rounakdas2025@gmail.com, niravkumar.l.rabara@altera.com, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: edac: altera: agilex5: document new edac support Date: Mon, 20 Jul 2026 15:14:22 -0500 Message-ID: <20260720201425.1538771-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.42.0.411.g813d9a9188 In-Reply-To: <20260720201425.1538771-1-dinguyen@kernel.org> References: <20260720201425.1538771-1-dinguyen@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Agilex5 EDAC module supports ECC on a few additional peripherals. Along with support for ocram, ethernet and USB, the Agilex5 EDAC adds support for SDM QSPI, CRAM SEU and IO96B. The Agilex5 EDAC also exposes up to 7 named interrupts on the manager node. global_sbe and global_dbe are aggregate single/double-bit error interrupts that fan-out through the manager's IRQ domain to the child peripheral ECCs. The remaining named interrupts are routed directly from dedicated controllers (IO96B memory controllers and Secure Device Manager) to the GIC. Signed-off-by: Dinh Nguyen --- .../edac/altr,socfpga-ecc-manager.yaml | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manage= r.yaml b/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.ya= ml index 136e8fccd429a..2ccb0f2163185 100644 --- a/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml +++ b/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml @@ -22,6 +22,9 @@ properties: - items: - const: altr,socfpga-s10-ecc-manager - const: altr,socfpga-a10-ecc-manager + - items: + - const: altr,socfpga-agilex5-ecc-manager + - const: altr,socfpga-a10-ecc-manager - const: altr,socfpga-a10-ecc-manager - const: altr,socfpga-ecc-manager =20 @@ -33,7 +36,25 @@ properties: =20 interrupts: minItems: 1 - maxItems: 2 + items: + - description: Global single-bit error + - description: Global double-bit error + - description: IO96B0 DRAM controller error + - description: IO96B1 DRAM controller error + - description: SDM QSPI single-bit error + - description: SDM QSPI double-bit error + - description: SDM single-event + + interrupt-names: + minItems: 1 + items: + - const: global_sbe + - const: global_dbe + - const: io96b0 + - const: io96b1 + - const: sdm_qspi_sbe + - const: sdm_qspi_dbe + - const: sdm_seu =20 interrupt-controller: true =20 --=20 2.42.0.411.g813d9a9188 From nobody Sat Jul 25 01:52:22 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BA613B95EC; Mon, 20 Jul 2026 20:14:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784578483; cv=none; b=D5DzKNmK7AQgYuw4zpeOfUa5tTbEI9Aqb31bUnFp3/pvJsHPQWSUpGM1QjQAPpzk6LO6fyDuuZkIsNq4+w+Fh4XS4XNZsa86i5WWLF/R2ib5SJsZ46QqgZB2/QZyCPjxkvEDfPEabryoKtCloWHTC8RtjQW4bcJXey2FSDOIDmM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784578483; c=relaxed/simple; bh=L8iG6rbZSCPRio7i7fsNWkL+mnKxgDZdAddcNP5EZtM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hn7Iqyoyu3tjybaFJH/Pz6YorUVBiYL8/qkz+iRc9VxIW9Gf8zLutbmS14WLodV58rV6zpF+snVCArtNH3tN9Ga9GjQFf/mBkmCVn/1r6t+rwIQV+63FTRtza7n7WMBM6NJoOPFgwatq6Cm/3jYQKNI8eeS73QxJiIBlObhwHKQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NqcZGS22; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NqcZGS22" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5D5851F00A3D; Mon, 20 Jul 2026 20:14:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784578478; bh=k35bPK55M0YqpELHeycgJ3HxdnqxajKxw9PK0VKv+4k=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=NqcZGS228TjNwbNHEi+WpnU+6Kz04beiK/GNQFz0Li1fLuXCXrEJ7cqqflAE2FHDR /Y/d1+N5MFnu3ZlhAVJpcwtgQelisxTuPi9VoBZomwSGLERUytNcAwPB3gX2cINVjJ BnnE3yUz6XPyt6LLHyMuW4oAzbnvzr3E8AlT6LQW5gFNmHedmKZ2TT7vQaxkOugFW9 Y7JM58tSjv/5J0wF23bZn2LAmYwV87aWSaZnXvfmy4fE6nucz2BzOW090XrFtwYGbn 7WbbzzBJMP/Ca+nkCqHrnUTQQsf+aX/vRBBtpF3deXdGupqp/+o7tze1KBq2uhdHxF mI3mDsqOXHARQ== From: Dinh Nguyen To: bp@alien8.de, tony.luck@intel.com Cc: dinguyen@kernel.org, rounakdas2025@gmail.com, niravkumar.l.rabara@altera.com, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/4] EDAC/altera: use flag to differentiate 64-bit platforms Date: Mon, 20 Jul 2026 15:14:23 -0500 Message-ID: <20260720201425.1538771-3-dinguyen@kernel.org> X-Mailer: git-send-email 2.42.0.411.g813d9a9188 In-Reply-To: <20260720201425.1538771-1-dinguyen@kernel.org> References: <20260720201425.1538771-1-dinguyen@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In commit (d4486fc3098e "EDAC/altera: Use ECC manager compatible to select A10/S10 IRQ layout"), it added a way to only differentiate Stratix10 from a 32-bit platform. In preparation to add support for Agilex5, it needs a way = to make a further differentiation. Make use of the driver match data to hold a flag for different platforms, specifically Stratix10 and Agilex5. Signed-off-by: Dinh Nguyen --- drivers/edac/altera_edac.c | 17 +++++++++-------- drivers/edac/altera_edac.h | 5 ++++- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c index 777ba6efcc542..8a5b08e0d0583 100644 --- a/drivers/edac/altera_edac.c +++ b/drivers/edac/altera_edac.c @@ -1507,7 +1507,7 @@ static int altr_portb_setup(struct altr_edac_device_d= ev *device) int edac_idx, rc; struct device_node *np; const struct edac_device_prv_data *prv =3D &a10_sdmmceccb_data; - bool is_s10 =3D device->edac->is_s10; + unsigned long flag =3D {unsigned long)device->edac->flag; =20 rc =3D altr_check_ecc_deps(device); if (rc) @@ -1555,7 +1555,7 @@ static int altr_portb_setup(struct altr_edac_device_d= ev *device) */ =20 /* Using compatibles to determine the IRQ Index */ - if (is_s10) + if (flag =3D=3D SOCFPGA_S10) altdev->sb_irq =3D irq_of_parse_and_map(np, 1); else altdev->sb_irq =3D irq_of_parse_and_map(np, 2); @@ -1573,7 +1573,7 @@ static int altr_portb_setup(struct altr_edac_device_d= ev *device) goto err_release_group_1; } =20 - if (is_s10) { + if (flag =3D=3D SOCFPGA_S10) { /* Use IRQ to determine SError origin instead of assigning IRQ */ rc =3D of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq); if (rc) { @@ -1979,7 +1979,7 @@ static int altr_edac_a10_device_add(struct altr_arria= 10_edac *edac, goto err_release_group1; } =20 - if (edac->is_s10) { + if (edac->flag =3D=3D SOCFPGA_S10) { /* Use IRQ to determine SError origin instead of assigning IRQ */ rc =3D of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq); if (rc) { @@ -2125,7 +2125,7 @@ static int altr_edac_a10_probe(struct platform_device= *pdev) platform_set_drvdata(pdev, edac); INIT_LIST_HEAD(&edac->a10_ecc_devices); =20 - edac->is_s10 =3D !!device_get_match_data(&pdev->dev); + edac->flag =3D (unsigned long)device_get_match_data(&pdev->dev); =20 edac->ecc_mgr_map =3D altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node, @@ -2158,8 +2158,8 @@ static int altr_edac_a10_probe(struct platform_device= *pdev) irq_set_chained_handler_and_data(edac->sb_irq, altr_edac_a10_irq_handler, edac); - if (edac->is_s10) - { + + if (edac->flag =3D=3D SOCFPGA_S10) { int dberror, err_addr; =20 edac->panic_notifier.notifier_call =3D s10_edac_dberr_handler; @@ -2210,7 +2210,8 @@ static int altr_edac_a10_probe(struct platform_device= *pdev) =20 static const struct of_device_id altr_edac_a10_of_match[] =3D { { .compatible =3D "altr,socfpga-a10-ecc-manager" }, - { .compatible =3D "altr,socfpga-s10-ecc-manager", .data =3D (void *)1 }, + { .compatible =3D "altr,socfpga-s10-ecc-manager", + .data =3D (void *)SOCFPGA_S10 }, {}, }; MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match); diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h index 9387056fd65e3..74ab7bfc3e748 100644 --- a/drivers/edac/altera_edac.h +++ b/drivers/edac/altera_edac.h @@ -351,6 +351,9 @@ struct altr_sdram_mc_data { #define ECC_READ_EOVR 0x2 #define ECC_READ_EDOVR 0x3 =20 +#define SOCFPGA_S10 0x1 +#define SOCFPGA_AGILEX5 0x2 + struct altr_edac_device_dev; =20 struct edac_device_prv_data { @@ -394,7 +397,7 @@ struct altr_arria10_edac { struct irq_chip irq_chip; struct list_head a10_ecc_devices; struct notifier_block panic_notifier; - bool is_s10; + unsigned long flag; }; =20 #endif /* #ifndef _ALTERA_EDAC_H */ --=20 2.42.0.411.g813d9a9188 From nobody Sat Jul 25 01:52:22 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19D7E3B95F9; Mon, 20 Jul 2026 20:14:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784578486; cv=none; b=s73i0aACpxQEiSyviHBslY6c47CEP+8wJ3RzY6NBuRRBqlseAIbE2VaPRYqVKHPnYhIZUN7Gb52T0GhDiRpV7NXOBK+dHFAp86GcnF8Gfn8c310fw2/LU9QJ1nNzC7bzxMpRqVm0OPgJKHN/zfz5XI9It8L1qpZ5Lyn6xeQBNmw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784578486; c=relaxed/simple; bh=icODztdovmLFBa/t0SKuz9MvggB1lfQk7cBj97Wthts=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WFBKbwUYYl9KAxqIVX0ovYFHx/CIJJi/sf7ra0hlldoxIbCnRCT/kufq/KP/h95O81Jd9hVwm1rtnN5U7H9M09PamBMUDi08EI2b6gW9dnbG03F7ybr4GOhr4SQcbhngvAeKwIbcFXOOpRCfs+xbFxmB8gVsjhUE5+xJ/OtwgtI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E/1DHAya; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E/1DHAya" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8D1DE1F000E9; Mon, 20 Jul 2026 20:14:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784578479; bh=KBwZxoJtoFvsvhG5z379ZVkA7GMClyopvNaP8IXvXnM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=E/1DHAyaq2xtARE4yGqiA1KWFLvpKwh/TE6XcE85TuviFEo+MRYg39DjFHaAwYohl sl9g8H3wJo5dQVfIjvgFlfd7DmvYEg6DuyvmoGeGYqQzmU5vgyYrBDQO154wCFJymj jF4srqudo/k46ShavFlUtJ656LFsvxicVgo2HndmjnZXjn33XqVtLxk4VyQm+P9hL9 KQ/VsDoneoP0HTJCrEXfdXBaBVSegZs655vgBh1hO39HA3l5uTdsDGTCaJed+woU8g fGtu7m3rzgWvQwMwXzudZggqylEDuIoQdTvTM0uNFTdX69zJAcaUviyHKhFAy2kW8Z naFWrbqBXyeGQ== From: Dinh Nguyen To: bp@alien8.de, tony.luck@intel.com Cc: dinguyen@kernel.org, rounakdas2025@gmail.com, niravkumar.l.rabara@altera.com, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org Subject: [PATCH 3/4] EDAC/altera: Add support for Agilex5 ECC manager Date: Mon, 20 Jul 2026 15:14:24 -0500 Message-ID: <20260720201425.1538771-4-dinguyen@kernel.org> X-Mailer: git-send-email 2.42.0.411.g813d9a9188 In-Reply-To: <20260720201425.1538771-1-dinguyen@kernel.org> References: <20260720201425.1538771-1-dinguyen@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new compatible "altr,socfpga-agilex5-ecc-manager" to the Arria10 EDAC manager driver. Unlike Stratix10/Agilex7, the Agilex5 ECC manager exposes up to 7 named interrupts on its DT node: global_sbe - aggregate single-bit error (chained, drives IRQ domain) global_dbe - aggregate double-bit error (chained; DBE is no longer delivered exclusively through Asynchronous SError) io96b0 - IO96B0 DRAM controller ECC io96b1 - IO96B1 DRAM controller ECC sdm_qspi_sbe - SDM QSPI single-bit error sdm_qspi_dbe - SDM QSPI double-bit error sdm_seu - SDM single-event-upset On Agilex5, retrieve all seven interrupts by name via platform_get_irq_byname_optional() and stash them in a new agilex5_irqs[] array on struct altr_arria10_edac so subsequent peripheral support (IO96B, SDM QSPI, CRAM SEU) can consume them without re-parsing the DT. Only global_sbe is mandatory; the rest are optional. global_sbe is wired up as the chained SBE handler (replacing the legacy index-0 lookup). When present, global_dbe is hooked into the same altr_edac_a10_irq_handler() so that the existing sb_irq/db_irq demux routes DBE events through the manager's IRQ domain. The SError-based panic notifier path is preserved as a fall-back. Legacy A10/S10 probe paths are unchanged. Assisted-by: Cursor:claude-sonnet-4.7 Signed-off-by: Dinh Nguyen --- drivers/edac/altera_edac.c | 85 ++++++++++++++++++++++++++++++++++++-- drivers/edac/altera_edac.h | 29 +++++++++++++ 2 files changed, 110 insertions(+), 4 deletions(-) diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c index 8a5b08e0d0583..44da63ef5d71e 100644 --- a/drivers/edac/altera_edac.c +++ b/drivers/edac/altera_edac.c @@ -1507,7 +1507,7 @@ static int altr_portb_setup(struct altr_edac_device_d= ev *device) int edac_idx, rc; struct device_node *np; const struct edac_device_prv_data *prv =3D &a10_sdmmceccb_data; - unsigned long flag =3D {unsigned long)device->edac->flag; + unsigned long flag =3D (unsigned long)device->edac->flag; =20 rc =3D altr_check_ecc_deps(device); if (rc) @@ -2111,11 +2111,63 @@ static int s10_edac_dberr_handler(struct notifier_b= lock *this, return NOTIFY_DONE; } =20 +/* + * Ordered table of named interrupts published by an + * "altr,socfpga-agilex5-ecc-manager" device tree node. Indices match + * enum altr_agilex5_irq_idx. Only "global_sbe" is mandatory; the rest are + * optional so platforms can omit interrupts for unused subsystems. + */ +static const char * const altr_agilex5_irq_names[ALTR_AGILEX5_NUM_IRQS] = =3D { + [ALTR_AGILEX5_IRQ_GLOBAL_SBE] =3D "global_sbe", + [ALTR_AGILEX5_IRQ_GLOBAL_DBE] =3D "global_dbe", + [ALTR_AGILEX5_IRQ_IO96B0] =3D "io96b0", + [ALTR_AGILEX5_IRQ_IO96B1] =3D "io96b1", + [ALTR_AGILEX5_IRQ_SDM_QSPI_SBE] =3D "sdm_qspi_sbe", + [ALTR_AGILEX5_IRQ_SDM_QSPI_DBE] =3D "sdm_qspi_dbe", + [ALTR_AGILEX5_IRQ_SDM_SEU] =3D "sdm_seu", +}; + +/* + * Populate edac->agilex5_irqs[] from the named interrupts on the manager + * platform device. Missing optional interrupts are stored as a negative + * errno (-ENXIO) so that subsequent feature code can probe whether the + * resource exists. global_sbe is required because it drives the manager's + * IRQ domain dispatch path. + * + * platform_get_irq_byname_optional() can return -EPROBE_DEFER when the + * parent irqchip (e.g. the GIC) is not yet probed. Propagate that error + * up so the kernel re-tries the probe later instead of permanently + * disabling the named interrupt. + */ +static int altr_agilex5_get_named_irqs(struct platform_device *pdev, + struct altr_arria10_edac *edac) +{ + int i, irq; + + for (i =3D 0; i < ALTR_AGILEX5_NUM_IRQS; i++) { + irq =3D platform_get_irq_byname_optional(pdev, + altr_agilex5_irq_names[i]); + if (irq =3D=3D -EPROBE_DEFER) + return -EPROBE_DEFER; + + edac->agilex5_irqs[i] =3D irq > 0 ? irq : -ENXIO; + } + + if (edac->agilex5_irqs[ALTR_AGILEX5_IRQ_GLOBAL_SBE] < 0) { + dev_err(&pdev->dev, + "Agilex5 ECC manager missing required 'global_sbe' interrupt\n"); + return -ENODEV; + } + + return 0; +} + /****************** Arria 10 EDAC Probe Function *********************/ static int altr_edac_a10_probe(struct platform_device *pdev) { struct altr_arria10_edac *edac; struct device_node *child; + int rc; =20 edac =3D devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); if (!edac) @@ -2151,14 +2203,31 @@ static int altr_edac_a10_probe(struct platform_devi= ce *pdev) return -ENOMEM; } =20 - edac->sb_irq =3D platform_get_irq(pdev, 0); - if (edac->sb_irq < 0) - return edac->sb_irq; + if (edac->flag =3D=3D SOCFPGA_AGILEX5) { + rc =3D altr_agilex5_get_named_irqs(pdev, edac); + if (rc) + return rc; + + edac->sb_irq =3D edac->agilex5_irqs[ALTR_AGILEX5_IRQ_GLOBAL_SBE]; + } else { + edac->sb_irq =3D platform_get_irq(pdev, 0); + if (edac->sb_irq < 0) + return edac->sb_irq; + } =20 irq_set_chained_handler_and_data(edac->sb_irq, altr_edac_a10_irq_handler, edac); =20 + /* + * Unlike Stratix10/Agilex7 (which deliver uncorrectable errors as + * Asynchronous SError), Agilex5 routes the global double-bit error + * through a dedicated SPI ("global_dbe"). Hook it into the same + * chained handler so the existing sb_irq/db_irq demux in + * altr_edac_a10_irq_handler() routes DBE events through the manager's + * IRQ domain. The panic notifier below is still registered as a + * fall-back for any DBEs that escape to SError. + */ if (edac->flag =3D=3D SOCFPGA_S10) { int dberror, err_addr; =20 @@ -2181,6 +2250,12 @@ static int altr_edac_a10_probe(struct platform_devic= e *pdev) regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST, 0); } + } else if (edac->flag =3D=3D SOCFPGA_AGILEX5 && + edac->agilex5_irqs[ALTR_AGILEX5_IRQ_GLOBAL_DBE] >=3D 0) { + edac->db_irq =3D edac->agilex5_irqs[ALTR_AGILEX5_IRQ_GLOBAL_DBE]; + irq_set_chained_handler_and_data(edac->db_irq, + altr_edac_a10_irq_handler, + edac); } else { edac->db_irq =3D platform_get_irq(pdev, 1); if (edac->db_irq < 0) @@ -2212,6 +2287,8 @@ static const struct of_device_id altr_edac_a10_of_mat= ch[] =3D { { .compatible =3D "altr,socfpga-a10-ecc-manager" }, { .compatible =3D "altr,socfpga-s10-ecc-manager", .data =3D (void *)SOCFPGA_S10 }, + { .compatible =3D "altr,socfpga-agilex5-ecc-manager", + .data =3D (void *)SOCFPGA_AGILEX5 }, {}, }; MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match); diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h index 74ab7bfc3e748..30e35da7eb6a1 100644 --- a/drivers/edac/altera_edac.h +++ b/drivers/edac/altera_edac.h @@ -326,6 +326,27 @@ struct altr_sdram_mc_data { #define S10_DDR0_IRQ_MASK BIT(16) #define S10_DBE_IRQ_MASK 0x3FFFE =20 +/************* Agilex5 Defines **************/ +/* + * The Agilex5 ECC manager exposes up to 7 named interrupts on the manager + * node. global_sbe and global_dbe are aggregate single/double-bit error + * interrupts that fan-out through the manager's IRQ domain to the child + * peripheral ECCs. The remaining named interrupts are routed directly from + * dedicated controllers (IO96B memory controllers and Secure Device Manag= er) + * to the GIC. + */ +#define ALTR_AGILEX5_NUM_IRQS 7 + +enum altr_agilex5_irq_idx { + ALTR_AGILEX5_IRQ_GLOBAL_SBE, + ALTR_AGILEX5_IRQ_GLOBAL_DBE, + ALTR_AGILEX5_IRQ_IO96B0, + ALTR_AGILEX5_IRQ_IO96B1, + ALTR_AGILEX5_IRQ_SDM_QSPI_SBE, + ALTR_AGILEX5_IRQ_SDM_QSPI_DBE, + ALTR_AGILEX5_IRQ_SDM_SEU, +}; + /* Define ECC Block Offsets for peripherals */ #define ECC_BLK_ADDRESS_OFST 0x40 #define ECC_BLK_RDATA0_OFST 0x44 @@ -398,6 +419,14 @@ struct altr_arria10_edac { struct list_head a10_ecc_devices; struct notifier_block panic_notifier; unsigned long flag; + + /* + * Agilex5 ECC manager supports up to ALTR_AGILEX5_NUM_IRQS named + * interrupts. Entries are indexed by enum altr_agilex5_irq_idx and + * hold the Linux virtual IRQ number, or a negative errno when the + * corresponding interrupt was not provided in the device tree. + */ + int agilex5_irqs[ALTR_AGILEX5_NUM_IRQS]; }; =20 #endif /* #ifndef _ALTERA_EDAC_H */ --=20 2.42.0.411.g813d9a9188 From nobody Sat Jul 25 01:52:22 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E174C3B42EA; Mon, 20 Jul 2026 20:14:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784578486; cv=none; b=DGBgxW3KKVWHBIxUocByYtnY5gx9X/J9n78QMEQ4hib5LBaYrn78AEbnYo4CZwFrdQKXOTqk0eQUqzkjQkAEWqMq2mM+2Jsn1M7rFzzsTdCt445OCXhhaAFhT3rsMXVfHT0I5H5M5Z7OGJND64rk10YmNCWN88lhxEed0sAjo6w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784578486; c=relaxed/simple; bh=G6Jvo8CB73SeI2n+WMYHDaxiePGTID81nBvN5AM0dQ8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ErXInsiFsHYhX/4vMcHGV/ziFYgFsxVhMfqf+cd9J0OiFOLK4N4GStdo5JRzQsI48jMDmmXrVSyyXPGuUvSI7Tgb89vuoOJcDwOhBtVFupZCU04+ouBlrDL0zCg/4i9AADfiBU40K4Tf7q/DjBMVtUFb43dbk6PQefRZrb+EMHg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dPe3/MUt; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dPe3/MUt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8E12D1F00AC4; Mon, 20 Jul 2026 20:14:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784578480; bh=b7Gs+S/7u31vaSIsDabQTTJPkKaDyd0Xqb17szFxsH4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dPe3/MUtocmxiVka5T5Ey1jQRsjy0KBgOMZXeTVbE4DKMFr5QKRsmxsXkYEmwxAp/ l/gus/tZWmUUY7Va0qz0cxCyZmtt+sdqCQXQF5DFAhLeLw6SbNzHNhdDW7fBjPwo+y qbRxelXGBnwElP7ulSfB3QQsNOnVUYP20fpZKXFIBICjcOaL2IfK8fMilrry7sFX5W q1/wkK4ptxHiCImUS0dKVxmhRoJYKa2ffQ7HjrgFNU+4Fviu1DrlwsSb3g3pLmTUsL O2dQm6qj1j1OYWgJXFak8b6/Ft/bO923iEkJ/L1L7PG/lBUcnVIRaV7pOX5Nyc0yHc KXvhJq4UJfB2g== From: Dinh Nguyen To: bp@alien8.de, tony.luck@intel.com Cc: dinguyen@kernel.org, rounakdas2025@gmail.com, niravkumar.l.rabara@altera.com, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: socfpga: agilex5: add support for the ECC manager Date: Mon, 20 Jul 2026 15:14:25 -0500 Message-ID: <20260720201425.1538771-5-dinguyen@kernel.org> X-Mailer: git-send-email 2.42.0.411.g813d9a9188 In-Reply-To: <20260720201425.1538771-1-dinguyen@kernel.org> References: <20260720201425.1538771-1-dinguyen@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the EDAC device to the base Agilex5 platform. Add OCRAM and Ethernet ECC device support to the Agilex5 platform. Signed-off-by: Dinh Nguyen --- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/bo= ot/dts/intel/socfpga_agilex5.dtsi index b06c6d5d60eed..f30d476683b4a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -370,6 +370,74 @@ dmac1: dma-controller@10000 { }; }; =20 + eccmgr { + compatible =3D "altr,socfpga-agilex5-ecc-manager", + "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon =3D <&sysmgr>; + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupts =3D , + , + , + , + , + , + ; + interrupt-names =3D "global_sbe", "global_dbe", "io96b0" , "io96b1", + "sdm_qspi_sbe", "sdm_qspi_dbe", "sdm_seu"; + interrupt-controller; + #interrupt-cells =3D <2>; + ranges; + + ocram-ecc@108cc000 { + compatible =3D "altr,socfpga-a10-ocram-ecc"; + reg =3D <0x108cc000 0x100>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH>, <33 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-rx-ecc@108c0000 { + compatible =3D "altr,socfpga-eth-mac-ecc"; + reg =3D <0x108c0000 0x100>; + altr,ecc-parent =3D <&gmac0>; + interrupts =3D <4 IRQ_TYPE_LEVEL_HIGH>, <38 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-tx-ecc@108c0400 { + compatible =3D "altr,socfpga-eth-mac-ecc"; + reg =3D <0x108c0400 0x100>; + altr,ecc-parent =3D <&gmac0>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH>, <37 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac1-rx-ecc@108c0800 { + compatible =3D "altr,socfpga-eth-mac-ecc"; + reg =3D <0x108c0800 0x100>; + altr,ecc-parent =3D <&gmac1>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH>, <38 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac1-tx-ecc@108c0c00 { + compatible =3D "altr,socfpga-eth-mac-ecc"; + reg =3D <0x108c0c00 0x100>; + altr,ecc-parent =3D <&gmac1>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH>, <39 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac2-rx-ecc@108c1000 { + compatible =3D "altr,socfpga-eth-mac-ecc"; + reg =3D <0x108c1000 0x100>; + altr,ecc-parent =3D <&gmac2>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH>, <40 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac2-tx-ecc@108c1400 { + compatible =3D "altr,socfpga-eth-mac-ecc"; + reg =3D <0x108c1400 0x100>; + altr,ecc-parent =3D <&gmac2>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH>, <41 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + rst: rstmgr@10d11000 { compatible =3D "altr,stratix10-rst-mgr", "altr,rst-mgr"; reg =3D <0x10d11000 0x1000>; --=20 2.42.0.411.g813d9a9188