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Mon, 20 Jul 2026 12:20:46 -0700 (PDT) Received: from PeakBook-Mini.tail8e484.ts.net ([178.197.218.14]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-495653bffefsm9693325e9.9.2026.07.20.12.20.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 20 Jul 2026 12:20:45 -0700 (PDT) From: Doruk Tan Ozturk To: robh@kernel.org, tomeu@tomeuvizoso.net Cc: dri-devel@lists.freedesktop.org, ogabbay@kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH] accel/ethosu: validate all tiles and the packed-channel peak in the cmdstream verifier Date: Mon, 20 Jul 2026 21:20:44 +0200 Message-ID: <20260720192044.19557-1-doruk@0sec.ai> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The command-stream verifier records region_size[], the maximum byte offset the NPU will touch in each buffer object, and the submit path rejects a job whose region_size exceeds the bound BO (region_size[i] > gem->size). feat_matrix_length() computed that maximum by evaluating the touched address at a single presumed-worst corner (x =3D width, y =3D height, c =3D depth). That is the true maximum only when the address is monotonic in x/y/c and the feature matrix occupies a single tile. Neither always holds: - Storage modes 0 and 1 split the feature matrix into up to four tiles, each with an independent, user-supplied base (base[0..3]) into the same region. feat_matrix_length() is evaluated once, so only the tile containing the (max x, max y) corner is bounded; a large offset placed in any other tile base is never accounted for. - In the nhcwb16 packed format the channel term (c / 16) * stride_c + (c & 0xf) * element_size is not monotonic in c when stride_c is small, so the largest offset can lie at an interior channel rather than at c =3D depth. An unprivileged process able to open the accelerator node can therefore craft a cmdstream whose real maximum output offset exceeds the computed region_size, pass the submit check with an undersized output buffer, and have the NPU DMA-write past the end of that buffer (up to ~1 MiB out of bounds in the tiling case). Evaluate the extent at every corner that can bound the populated tiles and at the packed-channel peak, take the maximum, and reject the stream if any reachable tile base is left unset. Well-formed single-tile, monotonic streams are unchanged: the computed size is identical. Found by 0sec automated security-research tooling (https://0sec.ai). Fixes: 5a5e9c0228e6 ("accel: Add Arm Ethos-U NPU driver") Cc: stable@vger.kernel.org Assisted-by: 0sec:multi-model Signed-off-by: Doruk Tan Ozturk --- drivers/accel/ethosu/ethosu_gem.c | 73 +++++++++++++++++++++++++++---- 1 file changed, 65 insertions(+), 8 deletions(-) diff --git a/drivers/accel/ethosu/ethosu_gem.c b/drivers/accel/ethosu/ethos= u_gem.c index 3401883e207f..dfc499d7fb0c 100644 --- a/drivers/accel/ethosu/ethosu_gem.c +++ b/drivers/accel/ethosu/ethosu_gem.c @@ -192,17 +192,19 @@ static u64 dma_length(struct ethosu_validated_cmdstre= am_info *info, return len; } =20 -static u64 feat_matrix_length(struct ethosu_validated_cmdstream_info *info, - struct feat_matrix *fm, - u32 x, u32 y, u32 c) +/* + * Compute the byte offset the NPU addresses for one feature-matrix coordi= nate + * (x, y, c). Storage modes 0 and 1 route disjoint (x, y) sub-rectangles t= o up + * to four independent tile bases; the caller must only pass coordinates w= hose + * tiles it means to bound. Returns U64_MAX if the coordinate lands on a t= ile + * whose base was never set by the command stream. + */ +static u64 feat_matrix_addr(struct feat_matrix *fm, u32 x, u32 y, u32 c) { u32 element_size, storage =3D fm->precision >> 14; int tile =3D 0; u64 addr; =20 - if (fm->region < 0) - return U64_MAX; - switch (storage) { case 0: if (x >=3D fm->width0 + 1) { @@ -240,11 +242,66 @@ static u64 feat_matrix_length(struct ethosu_validated= _cmdstream_info *info, break; } =20 - info->region_size[fm->region] =3D max(info->region_size[fm->region], addr= + 1); - return addr; } =20 +/* + * Bound the region a feature matrix touches over the coordinate box + * [0, x] x [0, y] x [0, c]. + * + * The address is separable and, as the strides are unsigned 40-bit quanti= ties, + * non-decreasing in x and y, so their maxima sit at the box edge and, for= the + * tiled storage modes, just below each split (width0, height[]) where an + * independent tile base takes over. Only nhcwb16 packing is non-monotonic= in c: + * crossing a 16-lane group adds stride_c but resets the in-group term, so= the + * peak may sit at the top of the last full group instead of at c. Evaluat= ing + * every such extremal corner bounds all up-to-four tiles, whereas a single + * presumed-max corner undercounts the other tiles and the channel peak. + */ +static u64 feat_matrix_length(struct ethosu_validated_cmdstream_info *info, + struct feat_matrix *fm, + u32 x, u32 y, u32 c) +{ + u32 storage =3D fm->precision >> 14; + u32 xs[2], ys[3], cs[2]; + int nx =3D 0, ny =3D 0, nc =3D 0, i, j, k; + u64 max_addr =3D 0; + + if (fm->region < 0) + return U64_MAX; + + xs[nx++] =3D x; + if (storage =3D=3D 0) + xs[nx++] =3D min_t(u32, x, fm->width0); + + ys[ny++] =3D y; + if (storage =3D=3D 0 || storage =3D=3D 1) { + ys[ny++] =3D min_t(u32, y, fm->height[0]); + ys[ny++] =3D min_t(u32, y, fm->height[1]); + } + + cs[nc++] =3D c; + if (((fm->precision >> 6) & 0x3) =3D=3D 1 && c >=3D 16) + cs[nc++] =3D (c & ~0xfu) - 1; + + for (i =3D 0; i < nx; i++) { + for (j =3D 0; j < ny; j++) { + for (k =3D 0; k < nc; k++) { + u64 addr =3D feat_matrix_addr(fm, xs[i], ys[j], cs[k]); + + if (addr =3D=3D U64_MAX) + return U64_MAX; + max_addr =3D max(max_addr, addr); + } + } + } + + info->region_size[fm->region] =3D + max(info->region_size[fm->region], max_addr + 1); + + return max_addr; +} + static int calc_sizes(struct drm_device *ddev, struct ethosu_validated_cmdstream_info *info, u16 op, struct cmd_state *st, --=20 2.43.0