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Mon, 20 Jul 2026 09:38:32 -0700 (PDT) From: Fernando Rimoli To: Sakari Ailus , Daniel Scally , linux-media@vger.kernel.org Cc: Mauro Carvalho Chehab , Arsalan Naeem , Jakob Berg Jespersen , linux-kernel@vger.kernel.org, Fernando Rimoli Subject: [PATCH v3 1/4] media: i2c: ov5693: Add OVTI5693 ACPI HID Date: Mon, 20 Jul 2026 18:38:16 +0200 Message-ID: <20260720163819.104130-2-fernandorimoli11@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260720163819.104130-1-fernandorimoli11@gmail.com> References: <20260717132021.18034-1-fernandorimoli11@gmail.com> <20260720163819.104130-1-fernandorimoli11@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ov5693 driver only matches the "INT33BE" ACPI HID. Some Intel IPU6 Surface devices (e.g. Microsoft Surface Pro 9) enumerate the OV5693 front camera with the ACPI HID "OVTI5693" instead, so the i2c core never binds the driver. Add "OVTI5693" to the ACPI match table. Devices that use "INT33BE" (e.g. Surface Go 4) are unaffected. Tested on Surface Pro 9 (IPU6): the sensor enumerates as OVTI5693:00 (ACPI path \_SB_.PC00.I2C3.CAMF) and binds with this change. Link: https://github.com/linux-surface/linux-surface/pull/2171 Signed-off-by: Fernando Rimoli Reviewed-by: Daniel Scally --- drivers/media/i2c/ov5693.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/i2c/ov5693.c b/drivers/media/i2c/ov5693.c index 4cc796bbe..02236f3db 100644 --- a/drivers/media/i2c/ov5693.c +++ b/drivers/media/i2c/ov5693.c @@ -1396,6 +1396,7 @@ static const struct dev_pm_ops ov5693_pm_ops =3D { =20 static const struct acpi_device_id ov5693_acpi_match[] =3D { {"INT33BE"}, + {"OVTI5693"}, {}, }; MODULE_DEVICE_TABLE(acpi, ov5693_acpi_match); --=20 2.43.0 From nobody Sat Jul 25 02:11:44 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6348A43F4B7 for ; Mon, 20 Jul 2026 16:38:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; 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charset="utf-8" The IPU bridge builds the firmware node graph only for sensors listed in ipu_supported_sensors[]. The OV5693 is currently listed only under its legacy "INT33BE" HID, so on Intel IPU6 Surface devices that enumerate it as "OVTI5693" (e.g. Microsoft Surface Pro 9) the bridge never wires up the sensor and the front camera is unusable. Add an "OVTI5693" entry. The link frequency (419200000) matches the existing INT33BE entry, as it is the same sensor. Tested on Surface Pro 9 (IPU6). Link: https://github.com/linux-surface/linux-surface/pull/2171 Signed-off-by: Fernando Rimoli Reviewed-by: Daniel Scally --- drivers/media/pci/intel/ipu-bridge.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/pci/intel/ipu-bridge.c b/drivers/media/pci/intel= /ipu-bridge.c index 88581a4c0..b70d61099 100644 --- a/drivers/media/pci/intel/ipu-bridge.c +++ b/drivers/media/pci/intel/ipu-bridge.c @@ -93,6 +93,8 @@ static const struct ipu_sensor_config ipu_supported_senso= rs[] =3D { IPU_SENSOR_CONFIG("OVTI2680", 1, 331200000), /* Omnivision OV5675 */ IPU_SENSOR_CONFIG("OVTI5675", 1, 450000000), + /* Omnivision OV5693 */ + IPU_SENSOR_CONFIG("OVTI5693", 1, 419200000), /* Omnivision OV8856 */ IPU_SENSOR_CONFIG("OVTI8856", 3, 180000000, 360000000, 720000000), /* Sony IMX471 */ --=20 2.43.0 From nobody Sat Jul 25 02:11:44 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8360395ACA for ; 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Mon, 20 Jul 2026 09:38:35 -0700 (PDT) Received: from localhost.localdomain ([2001:b07:5d3a:fe75:4352:bba7:6d7f:5f92]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49565373608sm2105325e9.6.2026.07.20.09.38.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 09:38:34 -0700 (PDT) From: Fernando Rimoli To: Sakari Ailus , Daniel Scally , linux-media@vger.kernel.org Cc: Mauro Carvalho Chehab , Arsalan Naeem , Jakob Berg Jespersen , linux-kernel@vger.kernel.org, Fernando Rimoli Subject: [PATCH v3 3/4] media: i2c: ov5693: Gate the MIPI clock lane for non-continuous clock Date: Mon, 20 Jul 2026 18:38:18 +0200 Message-ID: <20260720163819.104130-4-fernandorimoli11@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260720163819.104130-1-fernandorimoli11@gmail.com> References: <20260717132021.18034-1-fernandorimoli11@gmail.com> <20260720163819.104130-1-fernandorimoli11@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ov5693 never programs MIPI_CTRL00 (0x4800), leaving it at its 0x00 power-on default (free-running MIPI clock). The IPU3 CSI-2 receiver tolerates this, but the IPU6 receiver (e.g. on Microsoft Surface Pro 8/9 and Surface Go 4) fails to lock onto the link, so the sensor streams but capture times out with "stream stop time out" and no frames arrive. Parse the "clock-noncontinuous" endpoint property (which sets the V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK flag) and, when it is present, gate the clock lane while idle (bit 5) and keep the bus in LP11 (bit 2) at stream on, matching the approach ov5647 already uses for the same register. When the flag is absent the register is left at its reset default, so IPU3 and other users are unaffected. Gating the clock lane was determined to be necessary and sufficient by sweeping the register at runtime on a Surface Pro 9 (IPU6): every value with bit 5 set streams (300/300 frames, steady 28 fps), every value with bit 5 clear fails with the CSI-2 timeout; register read-back confirmed the power-on default is 0x00. Bit 2 (bus idle in LP11) is set as well, matching ov5640's value. Note that unlike ov5647 the line-sync bit (bit 4) is deliberately not set: adding it collapses the IPU6 stream to a couple of frames, so this value differs from ov5647's - the IPU6 D-PHY behaves differently, consistent with these settings being PHY-specific. The "clock-noncontinuous" property is supplied by the ipu-bridge for the affected IPU6 variants in a subsequent patch. Link: https://github.com/linux-surface/linux-surface/pull/2171 Co-developed-by: Arsalan Naeem Signed-off-by: Arsalan Naeem Signed-off-by: Fernando Rimoli Tested-by: Jakob Berg Jespersen Reviewed-by: Daniel Scally --- drivers/media/i2c/ov5693.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/media/i2c/ov5693.c b/drivers/media/i2c/ov5693.c index 02236f3db..5468e89d6 100644 --- a/drivers/media/i2c/ov5693.c +++ b/drivers/media/i2c/ov5693.c @@ -35,6 +35,14 @@ #define OV5693_STOP_STREAMING 0x00 #define OV5693_SW_RESET 0x01 =20 +/* MIPI transmitter control */ +#define OV5693_MIPI_CTRL00_REG CCI_REG8(0x4800) +/* bit 5: gate the clock lane when idle; bit 2: keep the bus in LP11 when = idle */ +#define OV5693_MIPI_CTRL00_CLOCK_LANE_GATE BIT(5) +#define OV5693_MIPI_CTRL00_BUS_IDLE BIT(2) +#define OV5693_MIPI_CTRL00_NCONT_CLOCK (OV5693_MIPI_CTRL00_CLOCK_LANE_GAT= E | \ + OV5693_MIPI_CTRL00_BUS_IDLE) + #define OV5693_REG_CHIP_ID CCI_REG16(0x300a) /* Yes, this is right. The datasheet for the OV5693 gives its ID as 0x5690= */ #define OV5693_CHIP_ID 0x5690 @@ -144,6 +152,9 @@ struct ov5693_device { struct regulator_bulk_data supplies[OV5693_NUM_SUPPLIES]; struct clk *xvclk; =20 + /* Gate the MIPI clock lane when idle (CSI-2 non-continuous clock) */ + bool clock_ncont; + struct ov5693_mode { struct v4l2_rect crop; struct v4l2_mbus_framefmt format; @@ -611,6 +622,19 @@ static int ov5693_enable_streaming(struct ov5693_devic= e *ov5693, bool enable) { int ret =3D 0; =20 + /* + * When the CSI-2 link is configured for a non-continuous clock, gate + * the MIPI clock lane while idle (bit 5) and keep the bus in LP11 + * (bit 2). The power-on default of MIPI_CTRL00 is 0x00 (free-running + * clock): the IPU3 CSI-2 receiver tolerates that, but the IPU6 one + * fails to lock onto the link and capture times out. Only touch the + * register when the endpoint requests a non-continuous clock, leaving + * the reset default in place otherwise. + */ + if (enable && ov5693->clock_ncont) + cci_write(ov5693->regmap, OV5693_MIPI_CTRL00_REG, + OV5693_MIPI_CTRL00_NCONT_CLOCK, &ret); + cci_write(ov5693->regmap, OV5693_SW_STREAM_REG, enable ? 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charset="utf-8" The ov5693 (INT33BE / OVTI5693) needs its MIPI clock lane gated while idle for the IPU6 CSI-2 receiver to lock onto the link; otherwise the sensor streams but capture times out and no frames arrive. The sensor driver gates the clock lane when the endpoint requests a non-continuous clock, so the bridge has to supply that property. The same sensor works with a free-running clock on the IPU3, and other sensors are unaffected, so add the "clock-noncontinuous" endpoint property only for the ov5693 and only when the bridge sits on an IPU6 (matched against ipu6_pci_tbl). Non-PCI bridge instances (e.g. the IVSC mei_csi path) are skipped. Signed-off-by: Fernando Rimoli --- drivers/media/pci/intel/ipu-bridge.c | 30 ++++++++++++++++++++++++++++ include/media/ipu-bridge.h | 2 +- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/media/pci/intel/ipu-bridge.c b/drivers/media/pci/intel= /ipu-bridge.c index b70d61099..98773a99a 100644 --- a/drivers/media/pci/intel/ipu-bridge.c +++ b/drivers/media/pci/intel/ipu-bridge.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -15,6 +16,7 @@ #include =20 #include +#include #include =20 #define ADEV_DEV(adev) ACPI_PTR(&((adev)->dev)) @@ -383,6 +385,25 @@ int ipu_bridge_parse_ssdb(struct acpi_device *adev, st= ruct ipu_sensor *sensor) } EXPORT_SYMBOL_NS_GPL(ipu_bridge_parse_ssdb, "INTEL_IPU_BRIDGE"); =20 +/* + * The ov5693 (INT33BE / OVTI5693, on Microsoft Surface devices) only locks + * onto the IPU6 CSI-2 receiver when its clock lane is gated while idle, w= hich + * the sensor driver does when the endpoint requests a non-continuous cloc= k. + * The same sensor works with a free-running clock on the IPU3, so only re= quest + * the non-continuous clock on the IPU6 variants, keyed off the bridge's P= CI ID. + */ +static bool ipu_bridge_needs_ncont_clock(struct ipu_bridge *bridge, + const struct ipu_sensor_config *cfg) +{ + if (strcmp(cfg->hid, "INT33BE") && strcmp(cfg->hid, "OVTI5693")) + return false; + + if (!dev_is_pci(bridge->dev)) + return false; + + return !!pci_match_id(ipu6_pci_tbl, to_pci_dev(bridge->dev)); +} + static void ipu_bridge_create_fwnode_properties( struct ipu_sensor *sensor, struct ipu_bridge *bridge, @@ -463,6 +484,15 @@ static void ipu_bridge_create_fwnode_properties( cfg->link_freqs, cfg->nr_link_freqs); =20 + /* + * This must stay after the link-frequencies above: the property array + * is NULL-terminated, so the entry only takes effect when a preceding + * slot is populated. All IPU6 ov5693 configs define a link frequency. + */ + if (ipu_bridge_needs_ncont_clock(bridge, cfg)) + sensor->ep_properties[4] =3D + PROPERTY_ENTRY_BOOL("clock-noncontinuous"); + sensor->ipu_properties[0] =3D PROPERTY_ENTRY_U32_ARRAY_LEN( sensor->prop_names.data_lanes, bridge->data_lanes, sensor->lanes); diff --git a/include/media/ipu-bridge.h b/include/media/ipu-bridge.h index 16fac7654..48eb1e270 100644 --- a/include/media/ipu-bridge.h +++ b/include/media/ipu-bridge.h @@ -141,7 +141,7 @@ struct ipu_sensor { const char *vcm_type; =20 struct ipu_property_names prop_names; - struct property_entry ep_properties[5]; + struct property_entry ep_properties[6]; struct property_entry dev_properties[5]; struct property_entry ipu_properties[3]; struct property_entry ivsc_properties[1]; --=20 2.43.0