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charset="utf-8" Extend the qcom,q6apm-lpass-dais device tree binding to explicitly describe Digital Audio Interface (DAI) child nodes. Add #address-cells and #size-cells to allow representation of multiple DAI instances as child nodes, and define a dai@ pattern to document per-DAI properties such as the interface ID and associated clocks. On platforms such as Monaco and Lemans, third-party codecs are hardware wired to the SoC and do not always have an in-tree codec driver to manage their clocks. For these designs, clock line enablement must be driven from the platform side, and this series provides the necessary support for that. On QAIF-based platforms such as Shikra and Hawi, responsibility for voting I2S MCLK and BCLK has moved from the DSP to the kernel. This series introduces the required device tree binding support to represent and vote for these clocks from the kernel. Co-developed-by: Srinivas Kandagatla Signed-off-by: Srinivas Kandagatla Signed-off-by: Mohammad Rafi Shaik --- .../bindings/sound/qcom,q6apm-lpass-dais.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.= yaml b/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml index 2fb95544db8b..cde52c6f6761 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml @@ -21,6 +21,46 @@ properties: '#sound-dai-cells': const: 1 =20 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +# Digital Audio Interfaces +patternProperties: + '^dai@[0-9a-f]+$': + type: object + description: + Q6DSP Digital Audio Interfaces. + + properties: + reg: + maxItems: 1 + description: + Digital Audio Interface ID + + clocks: + minItems: 1 + items: + - description: MI2S bit clock + - description: MI2S external bit clock + - description: MI2S master clock + + clock-names: + minItems: 1 + items: + - enum: [bclk, eclk, mclk] + - const: mclk + + dependencies: + clocks: [clock-names] + + required: + - reg + + additionalProperties: false + required: - compatible - '#sound-dai-cells' @@ -29,7 +69,20 @@ unevaluatedProperties: false =20 examples: - | + #include + dais { compatible =3D "qcom,q6apm-lpass-dais"; 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charset="utf-8" Add support for MI2S clock control within q6apm-lpass DAIs, including handling of MCLK, BCLK, and ECLK via the DAI .set_sysclk callback. Each MI2S port now retrieves its clock handles from the device tree, allowing per-port clock configuration and proper enable/disable during startup and shutdown. Co-developed-by: Srinivas Kandagatla Signed-off-by: Srinivas Kandagatla Tested-by: Neil Armstrong Signed-off-by: Mohammad Rafi Shaik --- sound/soc/qcom/qdsp6/q6apm-lpass-dais.c | 194 +++++++++++++++++++++++- sound/soc/qcom/qdsp6/q6prm.h | 4 + 2 files changed, 196 insertions(+), 2 deletions(-) diff --git a/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c b/sound/soc/qcom/qdsp6= /q6apm-lpass-dais.c index 006b283484d9..040b97f03897 100644 --- a/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c +++ b/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c @@ -2,10 +2,12 @@ // Copyright (c) 2021, Linaro Limited =20 #include +#include #include #include #include #include +#include #include #include #include @@ -15,15 +17,64 @@ #include "q6dsp-common.h" #include "audioreach.h" #include "q6apm.h" +#include "q6prm.h" =20 #define AUDIOREACH_BE_PCM_BASE 16 =20 +struct q6apm_dai_priv_data { + struct clk *mclk; + struct clk *bclk; + struct clk *eclk; + bool mclk_enabled, bclk_enabled, eclk_enabled; +}; + struct q6apm_lpass_dai_data { struct q6apm_graph *graph[APM_PORT_MAX]; bool is_port_started[APM_PORT_MAX]; struct audioreach_module_config module_config[APM_PORT_MAX]; + struct q6apm_dai_priv_data priv[APM_PORT_MAX]; }; =20 +static void q6apm_lpass_dai_disable_clocks(struct q6apm_lpass_dai_data *da= i_data, int id) +{ + if (dai_data->priv[id].mclk_enabled) { + clk_disable_unprepare(dai_data->priv[id].mclk); + dai_data->priv[id].mclk_enabled =3D false; + } + + if (dai_data->priv[id].bclk_enabled) { + clk_disable_unprepare(dai_data->priv[id].bclk); + dai_data->priv[id].bclk_enabled =3D false; + } + + if (dai_data->priv[id].eclk_enabled) { + clk_disable_unprepare(dai_data->priv[id].eclk); + dai_data->priv[id].eclk_enabled =3D false; + } +} + +static void q6apm_lpass_dai_put_clocks(struct q6apm_lpass_dai_data *dai_da= ta) +{ + int i; + + for (i =3D 0; i < APM_PORT_MAX; i++) { + q6apm_lpass_dai_disable_clocks(dai_data, i); + + if (dai_data->priv[i].mclk) { + clk_put(dai_data->priv[i].mclk); + dai_data->priv[i].mclk =3D NULL; + } + if (dai_data->priv[i].bclk) { + clk_put(dai_data->priv[i].bclk); + dai_data->priv[i].bclk =3D NULL; + } + if (dai_data->priv[i].eclk) { + clk_put(dai_data->priv[i].eclk); + dai_data->priv[i].eclk =3D NULL; + } + } +} + static int q6dma_set_channel_map(struct snd_soc_dai *dai, unsigned int tx_num, const unsigned int *tx_ch_mask, @@ -251,6 +302,66 @@ static int q6apm_lpass_dai_startup(struct snd_pcm_subs= tream *substream, struct s return 0; } =20 +static int q6i2s_dai_startup(struct snd_pcm_substream *substream, struct s= nd_soc_dai *dai) +{ + return q6apm_lpass_dai_startup(substream, dai); +} + +static void q6i2s_lpass_dai_shutdown(struct snd_pcm_substream *substream, = struct snd_soc_dai *dai) +{ + struct q6apm_lpass_dai_data *dai_data =3D dev_get_drvdata(dai->dev); + + q6apm_lpass_dai_shutdown(substream, dai); + q6apm_lpass_dai_disable_clocks(dai_data, dai->id); +} + +static int q6i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, unsigned = int freq, int dir) +{ + struct q6apm_lpass_dai_data *dai_data =3D dev_get_drvdata(dai->dev); + struct clk *sysclk =3D NULL; + bool *enabled =3D NULL; + int ret =3D 0; + + switch (clk_id) { + case LPAIF_MI2S_MCLK: + sysclk =3D dai_data->priv[dai->id].mclk; + enabled =3D &dai_data->priv[dai->id].mclk_enabled; + break; + case LPAIF_MI2S_BCLK: + sysclk =3D dai_data->priv[dai->id].bclk; + enabled =3D &dai_data->priv[dai->id].bclk_enabled; + break; + case LPAIF_MI2S_ECLK: + sysclk =3D dai_data->priv[dai->id].eclk; + enabled =3D &dai_data->priv[dai->id].eclk_enabled; + break; + default: + return -EINVAL; + } + + if (sysclk) { + ret =3D clk_set_rate(sysclk, freq); + if (ret) { + dev_err(dai->dev, "Error, Unable to set rate (%d) for sysclk %d\n", + freq, clk_id); + return ret; + } + + if (*enabled) + return 0; + + ret =3D clk_prepare_enable(sysclk); + if (ret) { + dev_err(dai->dev, "Error, Unable to prepare (%d) sysclk\n", clk_id); + return ret; + } + + *enabled =3D true; + } + + return ret; +} + static int q6i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) { struct q6apm_lpass_dai_data *dai_data =3D dev_get_drvdata(dai->dev); @@ -272,11 +383,12 @@ static const struct snd_soc_dai_ops q6dma_ops =3D { =20 static const struct snd_soc_dai_ops q6i2s_ops =3D { .prepare =3D q6apm_lpass_dai_prepare, - .startup =3D q6apm_lpass_dai_startup, - .shutdown =3D q6apm_lpass_dai_shutdown, + .startup =3D q6i2s_dai_startup, + .shutdown =3D q6i2s_lpass_dai_shutdown, .set_channel_map =3D q6dma_set_channel_map, .hw_params =3D q6dma_hw_params, .set_fmt =3D q6i2s_set_fmt, + .set_sysclk =3D q6i2s_set_sysclk, .trigger =3D q6apm_lpass_dai_trigger, }; =20 @@ -297,6 +409,76 @@ static const struct snd_soc_component_driver q6apm_lpa= ss_dai_component =3D { .remove_order =3D SND_SOC_COMP_ORDER_FIRST, }; =20 +static int of_q6apm_parse_dai_data(struct device *dev, + struct q6apm_lpass_dai_data *data) +{ + int ret; + + for_each_child_of_node_scoped(dev->of_node, node) { + struct q6apm_dai_priv_data *priv; + int id; + + ret =3D of_property_read_u32(node, "reg", &id); + if (ret || id < 0 || id >=3D APM_PORT_MAX) { + dev_err(dev, "valid dai id not found:%d\n", ret); + continue; + } + + switch (id) { + /* MI2S specific properties */ + case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: + case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: + case SENARY_MI2S_RX ... SENARY_MI2S_TX: + priv =3D &data->priv[id]; + priv->mclk =3D of_clk_get_by_name(node, "mclk"); + if (IS_ERR(priv->mclk)) { + int err =3D PTR_ERR(priv->mclk); + + priv->mclk =3D NULL; + if (err =3D=3D -EPROBE_DEFER) { + q6apm_lpass_dai_put_clocks(data); + return dev_err_probe(dev, err, + "unable to get mi2s mclk\n"); + } + } + + priv->bclk =3D of_clk_get_by_name(node, "bclk"); + if (IS_ERR(priv->bclk)) { + int err =3D PTR_ERR(priv->bclk); + + priv->bclk =3D NULL; + if (err =3D=3D -EPROBE_DEFER) { + q6apm_lpass_dai_put_clocks(data); + return dev_err_probe(dev, err, + "unable to get mi2s bclk\n"); + } + } + + priv->eclk =3D of_clk_get_by_name(node, "eclk"); + if (IS_ERR(priv->eclk)) { + int err =3D PTR_ERR(priv->eclk); + + priv->eclk =3D NULL; + if (err =3D=3D -EPROBE_DEFER) { + q6apm_lpass_dai_put_clocks(data); + return dev_err_probe(dev, err, + "unable to get mi2s eclk\n"); + } + } + break; + default: + break; + } + } + + return 0; +} + +static void q6apm_lpass_dai_clocks_action(void *data) +{ + q6apm_lpass_dai_put_clocks(data); +} + static int q6apm_lpass_dai_dev_probe(struct platform_device *pdev) { struct q6dsp_audio_port_dai_driver_config cfg; @@ -304,12 +486,20 @@ static int q6apm_lpass_dai_dev_probe(struct platform_= device *pdev) struct snd_soc_dai_driver *dais; struct device *dev =3D &pdev->dev; int num_dais; + int ret; =20 dai_data =3D devm_kzalloc(dev, sizeof(*dai_data), GFP_KERNEL); if (!dai_data) return -ENOMEM; =20 dev_set_drvdata(dev, dai_data); + ret =3D of_q6apm_parse_dai_data(dev, dai_data); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, q6apm_lpass_dai_clocks_action, dai_= data); + if (ret) + return ret; =20 memset(&cfg, 0, sizeof(cfg)); cfg.q6i2s_ops =3D &q6i2s_ops; diff --git a/sound/soc/qcom/qdsp6/q6prm.h b/sound/soc/qcom/qdsp6/q6prm.h index a988a32086fe..bbbe6d368a41 100644 --- a/sound/soc/qcom/qdsp6/q6prm.h +++ b/sound/soc/qcom/qdsp6/q6prm.h @@ -3,6 +3,10 @@ #ifndef __Q6PRM_H__ #define __Q6PRM_H__ =20 +#define LPAIF_MI2S_MCLK 1 +#define LPAIF_MI2S_BCLK 2 +#define LPAIF_MI2S_ECLK 3 + /* Clock ID for Primary I2S IBIT */ #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100 /* Clock ID for Primary I2S EBIT */ --=20 2.34.1 From nobody Sat Jul 25 02:11:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E88D407CE8 for ; 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charset="utf-8" The sc8280xp machine driver is currently written with a largely SoC-centric view and assumes a uniform audio topology across all boards. In practice, multiple products based on the same SoC use different board designs and external audio components, which require board-specific configuration to function correctly. Several Qualcomm platforms like talos integrate third-party audio codecs or use different external audio paths. These designs often require additional configuration such as explicit MI2S MCLK settings for audio to work. This change enhances the sc8280xp machine driver to support board-specific configuration such as allowing each board variant to provide its own DAPM widgets and routes, reflecting the actual audio components and connectors present and enabling MI2S MCLK programming for boards that use external codecs requiring a stable master clock. Tested-by: Neil Armstrong Signed-off-by: Mohammad Rafi Shaik --- sound/soc/qcom/sc8280xp.c | 251 +++++++++++++++++++++++++++++++++++--- 1 file changed, 231 insertions(+), 20 deletions(-) diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c index 98b15a527e37..2ecba74d736e 100644 --- a/sound/soc/qcom/sc8280xp.c +++ b/sound/soc/qcom/sc8280xp.c @@ -12,17 +12,78 @@ #include #include #include "qdsp6/q6afe.h" +#include "qdsp6/q6apm.h" +#include "qdsp6/q6prm.h" #include "common.h" #include "sdw.h" =20 +#define I2S_MCLKFS 256 + +#define I2S_MCLK_RATE(rate) \ + ((rate) * (I2S_MCLKFS)) +#define I2S_BIT_RATE(rate, channels, format) \ + ((rate) * (channels) * (format)) + +static struct snd_soc_dapm_widget sc8280xp_dapm_widgets[] =3D { + SND_SOC_DAPM_HP("Headphone Jack", NULL), + SND_SOC_DAPM_MIC("Mic Jack", NULL), + SND_SOC_DAPM_SPK("DP0 Jack", NULL), + SND_SOC_DAPM_SPK("DP1 Jack", NULL), + SND_SOC_DAPM_SPK("DP2 Jack", NULL), + SND_SOC_DAPM_SPK("DP3 Jack", NULL), + SND_SOC_DAPM_SPK("DP4 Jack", NULL), + SND_SOC_DAPM_SPK("DP5 Jack", NULL), + SND_SOC_DAPM_SPK("DP6 Jack", NULL), + SND_SOC_DAPM_SPK("DP7 Jack", NULL), +}; + +struct snd_soc_common { + const char *driver_name; + const struct snd_soc_dapm_widget *dapm_widgets; + int num_dapm_widgets; + const struct snd_soc_dapm_route *dapm_routes; + int num_dapm_routes; + const struct snd_kcontrol_new *controls; + int num_controls; + unsigned int codec_dai_fmt; + bool codec_sysclk_set; + bool mi2s_mclk_enable; + bool mi2s_bclk_enable; + bool wcd_jack; +}; + struct sc8280xp_snd_data { bool stream_prepared[AFE_PORT_MAX]; struct snd_soc_card *card; struct snd_soc_jack jack; struct snd_soc_jack dp_jack[8]; + const struct snd_soc_common *snd_soc_common_priv; bool jack_setup; }; =20 +static inline int sc8280xp_get_mclk_freq(struct snd_pcm_hw_params *params) +{ + int rate =3D params_rate(params); + + switch (rate) { + case 11025: + case 44100: + case 88200: + return I2S_MCLK_RATE(44100); + default: + break; + } + + return I2S_MCLK_RATE(rate); +} + +static inline int sc8280xp_get_bclk_freq(struct snd_pcm_hw_params *params) +{ + return I2S_BIT_RATE(params_rate(params), + params_channels(params), + snd_pcm_format_width(params_format(params))); +} + static int sc8280xp_snd_init(struct snd_soc_pcm_runtime *rtd) { struct sc8280xp_snd_data *data =3D snd_soc_card_get_drvdata(rtd->card); @@ -32,10 +93,6 @@ static int sc8280xp_snd_init(struct snd_soc_pcm_runtime = *rtd) int dp_pcm_id =3D 0; =20 switch (cpu_dai->id) { - case PRIMARY_MI2S_RX...QUATERNARY_MI2S_TX: - case QUINARY_MI2S_RX...QUINARY_MI2S_TX: - snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP); - break; case WSA_CODEC_DMA_RX_0: case WSA_CODEC_DMA_RX_1: /* @@ -64,7 +121,10 @@ static int sc8280xp_snd_init(struct snd_soc_pcm_runtime= *rtd) if (dp_jack) return qcom_snd_dp_jack_setup(rtd, dp_jack, dp_pcm_id); =20 - return qcom_snd_wcd_jack_setup(rtd, &data->jack, &data->jack_setup); + if (data->snd_soc_common_priv->wcd_jack) + return qcom_snd_wcd_jack_setup(rtd, &data->jack, &data->jack_setup); + + return 0; } =20 static int sc8280xp_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, @@ -96,6 +156,63 @@ static int sc8280xp_be_hw_params_fixup(struct snd_soc_p= cm_runtime *rtd, return 0; } =20 +static int sc8280xp_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd =3D snd_soc_substream_to_rtd(substream); + struct snd_soc_dai *codec_dai =3D snd_soc_rtd_to_codec(rtd, 0); + struct snd_soc_dai *cpu_dai =3D snd_soc_rtd_to_cpu(rtd, 0); + struct sc8280xp_snd_data *data =3D snd_soc_card_get_drvdata(rtd->card); + int mclk_freq =3D sc8280xp_get_mclk_freq(params); + int bclk_freq =3D sc8280xp_get_bclk_freq(params); + int ret; + + switch (cpu_dai->id) { + case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: + case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: + case SENARY_MI2S_RX ... SENARY_MI2S_TX: + ret =3D snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_BP_FP); + if (ret && ret !=3D -ENOTSUPP) + return ret; + + if (data->snd_soc_common_priv->codec_dai_fmt) { + ret =3D snd_soc_dai_set_fmt(codec_dai, + data->snd_soc_common_priv->codec_dai_fmt); + if (ret && ret !=3D -ENOTSUPP) + return ret; + } + + if (data->snd_soc_common_priv->mi2s_mclk_enable) { + ret =3D snd_soc_dai_set_sysclk(cpu_dai, + LPAIF_MI2S_MCLK, mclk_freq, + SND_SOC_CLOCK_OUT); + if (ret) + return ret; + } + + if (data->snd_soc_common_priv->mi2s_bclk_enable) { + ret =3D snd_soc_dai_set_sysclk(cpu_dai, + LPAIF_MI2S_BCLK, bclk_freq, + SND_SOC_CLOCK_OUT); + if (ret) + return ret; + } + + if (data->snd_soc_common_priv->codec_sysclk_set) { + ret =3D snd_soc_dai_set_sysclk(codec_dai, + 0, mclk_freq, + SND_SOC_CLOCK_IN); + if (ret) + return ret; + } + break; + default: + break; + } + + return 0; +} + static int sc8280xp_snd_prepare(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd =3D snd_soc_substream_to_rtd(substream); @@ -117,6 +234,7 @@ static int sc8280xp_snd_hw_free(struct snd_pcm_substrea= m *substream) static const struct snd_soc_ops sc8280xp_be_ops =3D { .startup =3D qcom_snd_sdw_startup, .shutdown =3D qcom_snd_sdw_shutdown, + .hw_params =3D sc8280xp_snd_hw_params, .hw_free =3D sc8280xp_snd_hw_free, .prepare =3D sc8280xp_snd_prepare, }; @@ -145,38 +263,131 @@ static int sc8280xp_platform_probe(struct platform_d= evice *pdev) card =3D devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); if (!card) return -ENOMEM; - card->owner =3D THIS_MODULE; + /* Allocate the private data */ data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; =20 + data->snd_soc_common_priv =3D of_device_get_match_data(dev); + if (!data->snd_soc_common_priv) + return -ENODEV; + + card->owner =3D THIS_MODULE; card->dev =3D dev; dev_set_drvdata(dev, card); snd_soc_card_set_drvdata(card, data); + card->dapm_widgets =3D data->snd_soc_common_priv->dapm_widgets; + card->num_dapm_widgets =3D data->snd_soc_common_priv->num_dapm_widgets; + card->dapm_routes =3D data->snd_soc_common_priv->dapm_routes; + card->num_dapm_routes =3D data->snd_soc_common_priv->num_dapm_routes; + card->controls =3D data->snd_soc_common_priv->controls; + card->num_controls =3D data->snd_soc_common_priv->num_controls; + ret =3D qcom_snd_parse_of(card); if (ret) return ret; =20 - card->driver_name =3D of_device_get_match_data(dev); + card->driver_name =3D data->snd_soc_common_priv->driver_name; sc8280xp_add_be_ops(card); return devm_snd_soc_register_card(dev, card); } =20 +static const struct snd_soc_common eliza_priv_data =3D { + .driver_name =3D "eliza", + .dapm_widgets =3D sc8280xp_dapm_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(sc8280xp_dapm_widgets), + .wcd_jack =3D true, +}; + +static const struct snd_soc_common kaanapali_priv_data =3D { + .driver_name =3D "kaanapali", + .dapm_widgets =3D sc8280xp_dapm_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(sc8280xp_dapm_widgets), + .wcd_jack =3D true, +}; + +static const struct snd_soc_common qcs9100_priv_data =3D { + .driver_name =3D "sa8775p", + .dapm_widgets =3D sc8280xp_dapm_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + +static const struct snd_soc_common qcs615_priv_data =3D { + .driver_name =3D "qcs615", + .dapm_widgets =3D sc8280xp_dapm_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + +static const struct snd_soc_common qcm6490_priv_data =3D { + .driver_name =3D "qcm6490", + .dapm_widgets =3D sc8280xp_dapm_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(sc8280xp_dapm_widgets), + .wcd_jack =3D true, +}; + +static const struct snd_soc_common qcs6490_priv_data =3D { + .driver_name =3D "qcs6490", + .dapm_widgets =3D sc8280xp_dapm_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(sc8280xp_dapm_widgets), + .wcd_jack =3D true, +}; + +static const struct snd_soc_common qcs8275_priv_data =3D { + .driver_name =3D "qcs8300", + .dapm_widgets =3D sc8280xp_dapm_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(sc8280xp_dapm_widgets), +}; + +static const struct snd_soc_common sc8280xp_priv_data =3D { + .driver_name =3D "sc8280xp", + .dapm_widgets =3D sc8280xp_dapm_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(sc8280xp_dapm_widgets), + .wcd_jack =3D true, +}; + +static const struct snd_soc_common sm8450_priv_data =3D { + .driver_name =3D "sm8450", + .dapm_widgets =3D sc8280xp_dapm_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(sc8280xp_dapm_widgets), + .wcd_jack =3D true, +}; + +static const struct snd_soc_common sm8550_priv_data =3D { + .driver_name =3D "sm8550", + .dapm_widgets =3D sc8280xp_dapm_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(sc8280xp_dapm_widgets), + .wcd_jack =3D true, +}; + +static const struct snd_soc_common sm8650_priv_data =3D { + .driver_name =3D "sm8650", + .dapm_widgets =3D sc8280xp_dapm_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(sc8280xp_dapm_widgets), + .wcd_jack =3D true, +}; + +static const struct snd_soc_common sm8750_priv_data =3D { + .driver_name =3D "sm8750", + .dapm_widgets =3D sc8280xp_dapm_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(sc8280xp_dapm_widgets), + .wcd_jack =3D true, +}; + static const struct of_device_id snd_sc8280xp_dt_match[] =3D { - {.compatible =3D "qcom,eliza-sndcard", "eliza"}, - {.compatible =3D "qcom,kaanapali-sndcard", "kaanapali"}, - {.compatible =3D "qcom,qcm6490-idp-sndcard", "qcm6490"}, - {.compatible =3D "qcom,qcs615-sndcard", "qcs615"}, - {.compatible =3D "qcom,qcs6490-rb3gen2-sndcard", "qcs6490"}, - {.compatible =3D "qcom,qcs8275-sndcard", "qcs8300"}, - {.compatible =3D "qcom,qcs9075-sndcard", "sa8775p"}, - {.compatible =3D "qcom,qcs9100-sndcard", "sa8775p"}, - {.compatible =3D "qcom,sc8280xp-sndcard", "sc8280xp"}, - {.compatible =3D "qcom,sm8450-sndcard", "sm8450"}, - {.compatible =3D "qcom,sm8550-sndcard", "sm8550"}, - {.compatible =3D "qcom,sm8650-sndcard", "sm8650"}, - {.compatible =3D "qcom,sm8750-sndcard", "sm8750"}, + { .compatible =3D "qcom,eliza-sndcard", .data =3D &eliza_priv_data }, + { .compatible =3D "qcom,kaanapali-sndcard", .data =3D &kaanapali_priv_dat= a }, + { .compatible =3D "qcom,qcm6490-idp-sndcard", .data =3D &qcm6490_priv_dat= a }, + { .compatible =3D "qcom,qcs615-sndcard", .data =3D &qcs615_priv_data }, + { .compatible =3D "qcom,qcs6490-rb3gen2-sndcard", .data =3D &qcs6490_priv= _data }, + { .compatible =3D "qcom,qcs8275-sndcard", .data =3D &qcs8275_priv_data }, + { .compatible =3D "qcom,qcs9075-sndcard", .data =3D &qcs9100_priv_data }, + { .compatible =3D "qcom,qcs9100-sndcard", .data =3D &qcs9100_priv_data }, + { .compatible =3D "qcom,sc8280xp-sndcard", .data =3D &sc8280xp_priv_data = }, + { .compatible =3D "qcom,sm8450-sndcard", .data =3D &sm8450_priv_data }, + { .compatible =3D "qcom,sm8550-sndcard", .data =3D &sm8550_priv_data }, + { .compatible =3D "qcom,sm8650-sndcard", .data =3D &sm8650_priv_data }, + { .compatible =3D "qcom,sm8750-sndcard", .data =3D &sm8750_priv_data }, {} }; =20 --=20 2.34.1