From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A718A435ABB; Mon, 20 Jul 2026 15:08:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560116; cv=none; b=hIbBDtoHdjtjidKnuwOgSqVoPtEH+m3ltWI4JUfRov2+f01WvlBAHdczUKNXpmZ86MklhUMixmo26S8mLcu86G8cLjz83PXqym/daD5JaHUiRcArbDWbm6SaSg3TwAU8+CTRYwbwIXkhtwVMZXlj7fn07Dhko/C4FZzgEU39wzM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560116; c=relaxed/simple; bh=ThaktiGAe/yfRYpI9orDOAKwzNP7ZavcpetdONWm9nI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hcQbcJ6pboYa5/WHlczjSrq1JlNdgTMVRwv2PA2PSYQsaTF0XAzNz9WE7Eks78Umgp+nmiJ0teFKdacUIjg02js5aR54KEobjhu/JfM2PHDkblRQ00HjZtD55xTMcaVmN8Xh7jxcS8zOpFD0C+Nuzdjo1ErUmgtfe0N/fhAWbdw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=KVDwbKop; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="KVDwbKop" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=kb 4jWdBr7fAMGhV7hOxhuVJo6c1gLcmiTbqibBA1sDU=; b=KVDwbKopKysaucMRs9 vwQ9KpV2FqhFGITqoRCFnxIIT3GIlaUaBJzVA8i3oQFykeCl1NZvYQ1ThBbUJZH6 LjTGBYx/tXd3O4YFTwKg3BKzcQxZM8p+JH/ucFPH0scL5NIuJtGrrCvbAaqIfmdw w6QcjRo88fO7gfeCHyFzYbVtI= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wDX+mO9OV5q8LEOKg--.8910S3; Mon, 20 Jul 2026 23:07:44 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 01/16] PCI: dwc: Add pcie_cap field and helper in designware header Date: Mon, 20 Jul 2026 23:06:04 +0800 Message-Id: <20260720150619.24733-2-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDX+mO9OV5q8LEOKg--.8910S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7KFWxCF4kArWUWw4fGr1fXrb_yoW8Ww45pa y3JF1Skr48AFWavF43AanxZr15tF93ArW7Ga93Kw1SqFyaka4UGa10yryYyF17KrWIkrya kw45t34rCFn8JFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zEv388UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxACwVGpeOcAFAAAA3o Content-Type: text/plain; charset="utf-8" Add a pcie_cap field to struct dw_pcie to store the offset of the PCI Express Capability structure. Provide a helper dw_pcie_get_pcie_cap() which performs the capability search on first call and caches the result. This is a preparatory step for replacing repetitive capability searches in both core and platform drivers. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index de4b245b1758..8113efd33a24 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -591,6 +591,8 @@ struct dw_pcie { * use_parent_dt_ranges to true to avoid this warning. */ bool use_parent_dt_ranges; + + u8 pcie_cap; /* PCIe capability offset */ }; =20 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) @@ -829,6 +831,21 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pci= e *pci) dw_pcie_writel_dbi(pci, reg, val); } =20 +/** + * dw_pcie_get_pcie_cap() - Return cached PCIe Capability offset + * @pci: DWC instance + * + * Finds and caches the offset of PCI_CAP_ID_EXP on first call. + * Returns 0 if the capability is not present. + */ +static inline u8 dw_pcie_get_pcie_cap(struct dw_pcie *pci) +{ + if (!pci->pcie_cap) + pci->pcie_cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + return pci->pcie_cap; +} + static inline int dw_pcie_start_link(struct dw_pcie *pci) { if (pci->ops && pci->ops->start_link) --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7565C436356; Mon, 20 Jul 2026 15:08:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560117; cv=none; b=M1Ot/p+50bxQzKdp7RXx+9spx8cICVkm34hz8z5/JzZA1CfIwGBRDCFN2wWqM41KgKqKMFPhwIeVXnSugRgF0QlMf0dtji0O9hHcz/6IBb/oZJG+G1YFgSMKBV0xx7Kkt9QvnKP644Y1I/xfi6pdMId688G0+JbwMH2LsieudbA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560117; c=relaxed/simple; bh=WYuhx25G9sjPOhTLSdw4bLr2ImKawi5tUo5DLE+nRxs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UOthfud6Abs6qqSxUNzFB4vuq+Chc82FlwH3h64v3lJ7JxOg4vHArqT5dYulwsue2oqUPejJcUXZ/x37hzW4FuUDrfH8PIIV+4gz/+MzeTsorhox9dldtmu5XNdl71eQuQpQ0oO9wrd/UEAO2Mi5bOaw1DxuWOszjTk6jY+pEUs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=glyoB2ln; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="glyoB2ln" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=/S B7jvifzYR7GkBWCB3qlrfMX4gh0Gr4R+CcLe5/I0k=; b=glyoB2lnLVd7f+Nq+d vlaSVI90dgg0bU5S3wjAW14RUXKb5ea59uEsW5HnTbRHRxrROTXY9B7Iaria71Fs GuEJQXXsGS1jzxxr2n6Hhf+w7ptJ1tR/Y+an0rm1j2HlGhoF2ZECc4i6mdm4FVSn o+Hd0tMxyv64sOsyyHunjBcAQ= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wDX+mO9OV5q8LEOKg--.8910S4; Mon, 20 Jul 2026 23:07:45 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 02/16] PCI: dwc: Use cached PCIe capability offset in core Date: Mon, 20 Jul 2026 23:06:05 +0800 Message-Id: <20260720150619.24733-3-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDX+mO9OV5q8LEOKg--.8910S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxtr1xCFWfZw4UCFW3tr4kXrb_yoW7WFy5pa y3XFyFyF18Ar45ZFsI9as5XF13tFnxArWUCa9agr1SvFy7AFW2qa10yry3trn7KFsFvryY 9w18trW3Cwn8JFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zidHUfUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCwwGwVGpeOcEAMgAA3Y Content-Type: text/plain; charset="utf-8" Modify the DWC core functions to use the cached pcie_cap offset instead of calling dw_pcie_find_capability() each time. In the DWC core, dw_pcie_find_capability() is called at several locations: - dw_pcie_ep_init_non_sticky_registers() - dw_pcie_wait_for_link() - dw_pcie_link_set_max_speed() - dw_pcie_link_get_max_link_width() - dw_pcie_link_set_max_link_width() The cached offset is initialized after hardware is ready: - In host mode: dw_pcie_host_init() calls pp->ops->host_init() (enables clocks/resets), then dw_pcie_get_pcie_cap() caches the offset. - In endpoint mode: the core no longer caches automatically. Instead, drivers must call dw_pcie_get_pcie_cap() after hardware is enabled (e.g., after PERST# deassert). dw_pcie_ep_init_non_sticky_registers() is called after that point, so it can safely use pci->pcie_cap. dw_pcie_ep_init_non_sticky_registers() now assumes pci->pcie_cap is valid. if not, it prints a warning and skips the operation. The other functions run after probe, so pci->pcie_cap is already valid and can be used directly. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- drivers/pci/controller/dwc/pcie-designware-host.c | 2 ++ drivers/pci/controller/dwc/pcie-designware.c | 15 ++++++--------- 3 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 7d2794945704..14228be8bbce 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -1246,7 +1246,7 @@ static void dw_pcie_ep_init_non_sticky_registers(stru= ct dw_pcie *pci) * to all other functions as well. */ if (funcs > 1) { - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D pci->pcie_cap; func0_lnkcap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); func0_lnkcap =3D FIELD_GET(PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS, func0_lnkcap); diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 06722259d2e3..fee800ac56d4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -593,6 +593,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) goto err_free_ecam; } =20 + dw_pcie_get_pcie_cap(pci); + if (pci_msi_enabled()) { pp->use_imsi_rx =3D !(pp->ops->msi_init || of_property_present(np, "msi-parent") || diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index ec4722ed9303..810729b91892 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -766,7 +766,7 @@ const char *dw_pcie_ltssm_status_string(enum dw_pcie_lt= ssm ltssm) */ int dw_pcie_wait_for_link(struct dw_pcie *pci) { - u32 offset, val, ltssm; + u32 val, ltssm; int retries; =20 /* Check if the link is up or not */ @@ -806,8 +806,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) =20 pci_host_common_link_train_delay(pci->max_link_speed); =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - val =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); + val =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); =20 dev_info(pci->dev, "PCIe Gen.%u x%u link up\n", FIELD_GET(PCI_EXP_LNKSTA_CLS, val), @@ -843,7 +842,7 @@ EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) { u32 cap, ctrl2, link_speed; - u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; =20 cap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); =20 @@ -890,7 +889,7 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *= pci) int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) { u8 cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - u32 lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + u32 lnkcap =3D dw_pcie_readl_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP); =20 return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); } @@ -898,7 +897,6 @@ int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_l= anes) { u32 lnkcap, lwsc, plc; - u8 cap; =20 if (!num_lanes) return; @@ -935,10 +933,9 @@ static void dw_pcie_link_set_max_link_width(struct dw_= pcie *pci, u32 num_lanes) dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); =20 - cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + lnkcap =3D dw_pcie_readl_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP); FIELD_MODIFY(PCI_EXP_LNKCAP_MLW, &lnkcap, num_lanes); - dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); + dw_pcie_writel_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP, lnkcap); } =20 void dw_pcie_iatu_detect(struct dw_pcie *pci) --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66816435EDA; Mon, 20 Jul 2026 15:08:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560120; cv=none; b=e6l7XVZcfr2du/BjjDnYeCSXuud6JRwg+JeI3NU/cPoCkNYTuub2/cIMNH3qHtFWiSUPBqrRq8zGLiNLSWj4avk2BrBqBlZtokBqmERsvrqdr4NkQXBp4ZxDTxoRQc5yxDtmPcFGe9U+pi7xU0WulhkqKPbjAjfLm89Iq7WVkGg= ARC-Message-Signature: i=1; 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(unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wDX+mO9OV5q8LEOKg--.8910S5; Mon, 20 Jul 2026 23:07:46 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 03/16] PCI: dwc: imx6: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:06 +0800 Message-Id: <20260720150619.24733-4-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDX+mO9OV5q8LEOKg--.8910S5 X-Coremail-Antispam: 1Uf129KBjvJXoW7CF18ZFW7uF45Zr4ktry7ZFb_yoW8uF43pa y3u3yFyr4rJF42qFsFy3Z8Zr13tas0kw47Jw47Kw1Sqry7JryDWFy0yryfta1akr4kKFy7 AF1xtFyfJ34FyF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zipBTrUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAKwVGpeOcIFMgAA3a Content-Type: text/plain; charset="utf-8" Thus, the cached offset is available when these functions are called, and DBI access occurs only after hardware is enabled. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pci-imx6, dw_pcie_find_capability() is called in the following call chain: static const struct dw_pcie_ops dw_pcie_ops =3D { .start_link =3D imx_pcie_start_link, }; imx_pcie_start_link() -> dw_pcie_find_capability() -> imx_pcie_ltssm_enable() -> dw_pcie_find_capability() Replace these calls with the cached pci->pcie_cap. The call chain after modification becomes: dw_pcie_host_init() -> pp->ops->init() [imx6_pcie_host_init] -> dw_pcie_get_pcie_cap() (caches offset) -> pci->ops->start_link =3D imx_pcie_start_link -> uses pci->pcie_cap -> imx_pcie_ltssm_enable() -> uses pci->pcie_cap --- drivers/pci/controller/dwc/pci-imx6.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 98e1db751132..74b28b4df484 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -966,10 +966,10 @@ static void imx_pcie_ltssm_enable(struct device *dev) { struct imx_pcie *imx_pcie =3D dev_get_drvdata(dev); const struct imx_pcie_drvdata *drvdata =3D imx_pcie->drvdata; - u8 offset =3D dw_pcie_find_capability(imx_pcie->pci, PCI_CAP_ID_EXP); + struct dw_pcie *pci =3D imx_pcie->pci; u32 tmp; =20 - tmp =3D dw_pcie_readl_dbi(imx_pcie->pci, offset + PCI_EXP_LNKCAP); + tmp =3D dw_pcie_readl_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP); phy_set_speed(imx_pcie->phy, FIELD_GET(PCI_EXP_LNKCAP_SLS, tmp)); if (drvdata->ltssm_mask) regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->lt= ssm_mask, @@ -995,7 +995,7 @@ static int imx_pcie_start_link(struct dw_pcie *pci) { struct imx_pcie *imx_pcie =3D to_imx_pcie(pci); struct device *dev =3D pci->dev; - u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; u32 tmp; int ret; =20 --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2848414A18; Mon, 20 Jul 2026 15:08:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560116; cv=none; b=LBky+yOy33mgSeVTmYhQpLO29M8FXEWgbt4IybaOhDD5weGeBzqhFN5fqqsb7eIiNVCm2yKS7aLwqr5EMMAtoGt0f7daq5oz6mMLihbD+aBTaIheOpIq7i61QcnNtCxtoDGfHOQ/j0PjnUDHjhhOlXCqUU4WZPfrqWL+MBNhDgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560116; c=relaxed/simple; bh=CwQvJhYMmSpEtBnu8YgoO14KM8+fei2hTUBjvIMzffE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=N+s5Ze9+K8Qw6fy80wzx2r0lX6xUQU3Jn7jNpELlMLmJh7TBdFgQEV/5lf11r5qky16gTv83DinPmiL5NMek0Hl8yKlRSyKeQHi2WLWjf2jrf0TQ9r3QDix8WlHVuiHf6QToDMluLOxXJKzkCnLvxqg8MU4BDqE4cJELTQ4YRr4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=U1xIB7cY; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="U1xIB7cY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=sC 5IK7rcAYFVlcW/qRjCYlhzV8RYd8qBA49KkuguIVM=; b=U1xIB7cYYmtHDba2Gg Aiy0ph56gAshFRwCfzdpxVDWPwdWnSX4lYYp2WwdOnuINDqBSSa5mMHpJgc97vM2 Gr5ydSMhFv7KNMtNYF3saeMz/EFrze2OhzMB6X8PDhdsaYJXwqaH63YV74W9Yd/t aXWMFCUldUyUPgObP/gCPc78s= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wDX+mO9OV5q8LEOKg--.8910S6; Mon, 20 Jul 2026 23:07:47 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 04/16] PCI: dwc: layerscape-ep: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:07 +0800 Message-Id: <20260720150619.24733-5-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDX+mO9OV5q8LEOKg--.8910S6 X-Coremail-Antispam: 1Uf129KBjvJXoWxZF15KF4kXF1ktr18Gry8Xwb_yoW5GF1kpF WUXF4YkF18Jr4SgFsrZan8Wr13GF9akFy7J397Kr1aqry2vryUGa90yry5tFn7GFWqkFyj 934rtFy7u345JrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pigAw7UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAOwVGpeOcMFQQAA3p Content-Type: text/plain; charset="utf-8" Replace these with dw_pcie_get_pcie_cap(). The hardware is already enabled by the driver before ls_pcie_ep_probe() and before the interrupt handler runs. dw_pcie_get_pcie_cap() will cache the offset on first call, and subsequent calls (including inside dw_pcie_ep_init) will use the cached value without re-searching. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pci-layerscape-ep, dw_pcie_find_capability() is called in: ls_pcie_ep_probe() -> offset =3D dw_pcie_find_capability() -> pcie->lnkcap =3D dw_pcie_readl_dbi(offset + PCI_EXP_LNKCAP) -> dw_pcie_ep_init() -> ls_pcie_ep_interrupt_init() -> devm_request_irq(..., ls_pcie_ep_event_handler) -> ls_pcie_ep_event_handler() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pci-layerscape-ep.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/c= ontroller/dwc/pci-layerscape-ep.c index 8936975ff104..b2d0b51df3c5 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -74,7 +74,6 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void= *dev_id) struct ls_pcie_ep *pcie =3D dev_id; struct dw_pcie *pci =3D pcie->pci; u32 val, cfg; - u8 offset; =20 val =3D ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_DR); ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); @@ -83,9 +82,6 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void= *dev_id) return IRQ_NONE; =20 if (val & PEX_PF0_PME_MES_DR_LUD) { - - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - /* * The values of the Maximum Link Width and Supported Link * Speed from the Link Capabilities Register will be lost @@ -93,7 +89,8 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void= *dev_id) * that configured by the Reset Configuration Word (RCW). */ dw_pcie_dbi_ro_wr_en(pci); - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); + dw_pcie_writel_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP, + pcie->lnkcap); dw_pcie_dbi_ro_wr_dis(pci); =20 cfg =3D ls_pcie_pf_lut_readl(pcie, PEX_PF0_CONFIG); @@ -266,7 +263,7 @@ static int __init ls_pcie_ep_probe(struct platform_devi= ce *pdev) =20 platform_set_drvdata(pdev, pcie); =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); pcie->lnkcap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); =20 ret =3D dw_pcie_ep_init(&pci->ep); --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57796435EE8; Mon, 20 Jul 2026 15:08:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560118; cv=none; b=Vsfw+CvTBH2QX6cDstPohuO09/CVVYxpu2LdQXUImcDWCu7tWlAtFmpK6CpO4jXCxIKooGBC9bxppUi2IEWLl66pJm2UuYnA1pJzbrqaW5+PPEZUvO7LWxH6M/I/H6tzs/jmtlpgOueBn+2TzIjc6CCso0pSA6upVDv8C7J1194= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560118; c=relaxed/simple; bh=+UCv5/M5ymon9oIhPPvm7y92eCqH3y218Q1o/o6jht0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OgD4/BEwIo2tO1u5Lzh7uTcSamWyk/tc3ToWLApBc4EcCmcLsXVf9i9JimN2m7CFD3D+aYPPEDMljM9wztratPt7BJUCUuORxdUqwb3lI069Wo+q1XgoRD3YFhPG2EgK4sgkNJv0KVqsn0oxPwWW/ioHKJChvH+OdH6noorH0fc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=aO3MFWV9; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="aO3MFWV9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=sq 5n5May5plZP321RlYIM0qj1KqVpHN9549zyN1aNPQ=; b=aO3MFWV9XIa4ABdZgE Hlnwa0G0y0jJsfMsU+rQWsAwNfdEQSRYyiF/0lG020ZdM1GUb2xHquff0SkSItpS n87eoGNP4gxWufaDI0dGAfmPZRd3iUPaWS2n7tJhD9P+/pRDRXpNGj7rHOOOhjXO Cpk0uPrOoe+twSKXp/RvlYGtk= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wDX+mO9OV5q8LEOKg--.8910S7; Mon, 20 Jul 2026 23:07:47 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 05/16] PCI: dwc: meson: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:08 +0800 Message-Id: <20260720150619.24733-6-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDX+mO9OV5q8LEOKg--.8910S7 X-Coremail-Antispam: 1Uf129KBjvJXoW7CFy3CFyDGrWDZw47Jw1xGrg_yoW8AFWkpF WYgr4jyr18Ar4YgwnrCan8ZFy3Jas8Ar47Ja93Kw1SvFy2kFsrJ34ayFWYka4xWFW293Z8 CFn8tryUZwn5trUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piyxR-UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxASxVWpeOcQFUAAA34 Content-Type: text/plain; charset="utf-8" dw_pcie_host_init() calls pp->ops->init (meson_pcie_host_init) before caching the offset. Therefore, inside .init we must call dw_pcie_get_pcie_cap() to obtain the offset (the helper will perform the DBI read and cache the result). This is safe because the hardware is already enabled by the driver's own initialization. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pci-meson, the call chain is: static const struct dw_pcie_host_ops meson_pcie_host_ops =3D { .init =3D meson_pcie_host_init, }; meson_pcie_host_init() -> meson_set_max_payload() -> dw_pcie_find_capability() -> meson_set_max_rd_req_size() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pci-meson.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controlle= r/dwc/pci-meson.c index 7a4da9fae1ea..c9d0388d262b 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -277,7 +277,7 @@ static void meson_set_max_payload(struct meson_pcie *mp= , int size) { struct dw_pcie *pci =3D &mp->pci; u32 val; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D dw_pcie_get_pcie_cap(pci); int max_payload_size =3D meson_size_to_payload(mp, size); =20 val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); @@ -293,7 +293,7 @@ static void meson_set_max_rd_req_size(struct meson_pcie= *mp, int size) { struct dw_pcie *pci =3D &mp->pci; u32 val; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D dw_pcie_get_pcie_cap(pci); int max_rd_req_size =3D meson_size_to_payload(mp, size); =20 val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED5D443634B; Mon, 20 Jul 2026 15:08:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560116; cv=none; b=Ig8WovL93yHhqw5ADJH1S5oVWzLvgIjsYDV6tgaMc6YAt0Z2uk+KeZnPZ8V7GGr+qFQ9NQak+XYvoSuVuCt3/ol4GRMQIl3LHdhLoShNSYLxJ8blJBXaWREWdEVlx9qpgKEVWVnCwuqq9pSuPmj9QrL9oKWZtJ1cE22J0aEiIpk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560116; c=relaxed/simple; bh=Y7dm1zb3V8Pn4q2QZHLiuOm/3UTjsQMJ8BNRtM6lalM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IwL/2mZtUS7HP3ya6gKAC2uSC9zWYFdqlyLju0Xapi9kLVLfxHci/WKHoMfUfqyDAeekwnyrHXmpTXj9dYWfuC0AnI85axnQjN7uruvm0iR4jw7t9VEQNXDt85OPpOR9qd1EfrGcNro4rGPME9AQtBHHPcMbaH4FnWVZU5v6qv8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=CYQ2209a; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="CYQ2209a" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=3T nk0wVtGn53M6dJL6AEJiPqhbC3YBLarkGOhYIYIBw=; b=CYQ2209abseG3G4v3z nirGxluq0GIYB/vwRbKW4Yo4Z7lkVSJA8AKPvPxv30EEtuDHkVfL/s12ywjRRntf 5CNqSiOasNI8LfMTXjp9xtGNN4Z/uT+7n8+63leY7twtvGSwH2XSH4Z8bjBo7oKO jRqjYbVuhrcdg0wgzX56UNwkk= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wDX+mO9OV5q8LEOKg--.8910S8; Mon, 20 Jul 2026 23:07:48 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com>, Sebastian Reichel Subject: [PATCH v3 06/16] PCI: dwc: rockchip: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:09 +0800 Message-Id: <20260720150619.24733-7-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDX+mO9OV5q8LEOKg--.8910S8 X-Coremail-Antispam: 1Uf129KBjvJXoW7ZFy3CF1kCFy3GFyxtr1DZFb_yoW8Gr4kpa yYyry0yryrGr4S93Z2vas8urySqFnxArW7Ja97G3WSvFy2k34Ut3yYkr98tFnrGF4jyFya kw1Ut348GrsxAFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piyxR-UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6wWxVWpeOcVuuAAA3U Content-Type: text/plain; charset="utf-8" dw_pcie_host_init() calls .init before caching the offset. So inside .init we call dw_pcie_get_pcie_cap() to trigger caching. The helper will perform the DBI read (hardware is already enabled) and cache the result. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Sebastian Reichel --- In pcie-dw-rockchip, the call chain is: static const struct dw_pcie_host_ops rockchip_pcie_host_ops =3D { .init =3D rockchip_pcie_host_init, }; rockchip_pcie_host_init() -> rockchip_pcie_enable_l0s() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 731d93663cca..be8b6187913d 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -369,7 +369,7 @@ static void rockchip_pcie_enable_l0s(struct dw_pcie *pc= i) u32 cap, lnkcap; =20 /* Enable L0S capability for all SoCs */ - cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + cap =3D dw_pcie_get_pcie_cap(pci); if (cap) { lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); lnkcap |=3D PCI_EXP_LNKCAP_ASPM_L0S; --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57899435EED; Mon, 20 Jul 2026 15:08:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560118; cv=none; b=XPa3e61He6XCJuF4c1oHqY1qlhsqTo91L0apZ9vsZ7ATWmZdMyd8xuaOVrMW74z+inTVyLgtXuye3Bm6PUn0fG/hlbIjaHQTfPag1NH+6M2LsKT4ORbyf2+hg35lQqX2eNZGyntd3/0vlY//lc4QU86q1CgNDC/7f56GE1p7PTk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560118; c=relaxed/simple; bh=aTSU8cGptt1iIE491RxaEDXSLRqZ0TwtMEh+pilwLoU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iFhw137RZmmiAuKCsNOtw702x+vnzk62jSyRl7WWwDE3NTp8GP+Uso+mlvNCh1ad446WyworxvQBgJ7t4y21pkyIAcAZztfnhquvvUS86cbpEKmk7n14vZnP/rXByQZTw1vFbnSfrp+jSGXkT3L5xPBL+c1Nh3ZdnICAYmlOuwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=IFTUZrp4; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="IFTUZrp4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=S4 lPlR1q4qSCvgYn9gZFu5HucqogfFBKik1eEg5ZKUU=; b=IFTUZrp4E9PZKqQGHU jILUxrpWJD9kNSDQNDCct1EO5IHqaTfV1PLv3Buw3HPhXxbG8l0vFXtWfO0phug+ Fq9aLtAp97ZUlgohkgbK5M0BgY539ri6XL2Z1cplFxkoxGS8YhCY/7jb0A/yJPOj Z1OpM9bzQG2mLsXIWZWsrEUvA= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wDX+mO9OV5q8LEOKg--.8910S9; Mon, 20 Jul 2026 23:07:49 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 07/16] PCI: dwc: eswin: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:10 +0800 Message-Id: <20260720150619.24733-8-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDX+mO9OV5q8LEOKg--.8910S9 X-Coremail-Antispam: 1Uf129KBjvdXoWrKF4UZFW8XF4kWw18tr1DZFb_yoWkuFXE9a 4DKr9rAr47GF90k3Zavw4fAF9Fya4xXr1293WFyF9xZFyIgr1jgrnFqF98AFWxCFn5XFyr Jr4qvFyxAryUJjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sRNF4EPUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6wWxVWpeOcVuzQAA3h Content-Type: text/plain; charset="utf-8" This function is called after dw_pcie_host_init() has already cached the offset (dw_pcie_link_up() is called after .init and after caching). Therefore, we can directly use pci->pcie_cap. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-eswin, the call chain is: static const struct dw_pcie_ops dw_pcie_ops =3D { .link_up =3D eswin_pcie_link_up, }; eswin_pcie_link_up() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-eswin.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-eswin.c b/drivers/pci/controll= er/dwc/pcie-eswin.c index ce8d64f8a395..6a37fd5a8384 100644 --- a/drivers/pci/controller/dwc/pcie-eswin.c +++ b/drivers/pci/controller/dwc/pcie-eswin.c @@ -84,8 +84,7 @@ static int eswin_pcie_start_link(struct dw_pcie *pci) =20 static bool eswin_pcie_link_up(struct dw_pcie *pci) { - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - u16 val =3D dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); + u16 val =3D dw_pcie_readw_dbi(pci, pci->pcie_cap + PCI_EXP_LNKSTA); =20 return val & PCI_EXP_LNKSTA_DLLLA; } --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 950C743635E; Mon, 20 Jul 2026 15:08:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560117; cv=none; b=OOQcuL5FwCavaq4VAabpEJRNudQAGR6OrKCOMs69r2bcg0Ciz0jxKVKb8GEKNMbWjKYdTz7ZyerVQRPgrz5sQrlT17OWJtw7eZK2xHTuKvSH8EEtcJzcPEZFvAbSacoRdlmb6Soksj5sVIha64Tfad6Th6zVfq3XVKHeWTV93Sg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560117; c=relaxed/simple; bh=KFNywJY77A37y9C7nyuYTxEOSJ8mD3bMQuXrniAKLF0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pLW313R7ws83bxPsOmcECA1Op3M29H3H/Pr7qF+MgFsyeQl9exa+d9R6Own7c+dpPDPhI9bl+oZXn6mm5G3EI7qvYq0qa8a4Jm2i9J2rCBCkmpg1mJsXn25J6kvP4WXK3v7gOc7a6K10tMzDkzuUYgFnMna5jwoww0T8flGm13E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=T05Ujlka; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="T05Ujlka" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Ff B7GrmVp8WAki9+UnmVSGGvKtwSZ9GLa+Vb7MYQ6is=; b=T05UjlkaldoQa5YO1i pYWOXA+5sHjoD1Znr8vTiWAk3LqecPXJQt2ysiuoKU09Ur5AmUhmWEXNBJxkoq2y oKSNHkoYPQvONVjblDNCVPpvZJO0k52szKh6MijJ7Ps8HK9TcOOGPx0R8mcmAhCU XRJCZO3IGNeWr/eQtCx1y2HFM= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wD3b1rIOV5qyHOjKQ--.35310S2; Mon, 20 Jul 2026 23:07:54 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 08/16] PCI: dwc: fu740: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:11 +0800 Message-Id: <20260720150619.24733-9-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3b1rIOV5qyHOjKQ--.35310S2 X-Coremail-Antispam: 1Uf129KBjvdXoW7Xw1UXr4rWw1rCr47Xr13urg_yoWDArbE9a 4UGFs7ArWUKryFy3W2k3yfJF97Za47WF1UKa1rtFW3ZF97Xw18Wr9FqFyDJF48W34DXF1x JF4qvF40ka9rAjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sRt7KIPUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6wuyVmpeOctvPAAA3R Content-Type: text/plain; charset="utf-8" This callback is invoked after dw_pcie_host_init() has cached the offset, so we can use pci->pcie_cap directly. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-fu740, the call chain is: static const struct dw_pcie_ops dw_pcie_ops =3D { .start_link =3D fu740_pcie_start_link, }; fu740_pcie_start_link() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-fu740.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controll= er/dwc/pcie-fu740.c index d0a34f680397..72c0a6316fff 100644 --- a/drivers/pci/controller/dwc/pcie-fu740.c +++ b/drivers/pci/controller/dwc/pcie-fu740.c @@ -178,7 +178,7 @@ static int fu740_pcie_start_link(struct dw_pcie *pci) { struct device *dev =3D pci->dev; struct fu740_pcie *afp =3D dev_get_drvdata(dev); - u8 cap_exp =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 cap_exp =3D pci->pcie_cap; int ret; u32 orig, tmp; =20 --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4282439336; Mon, 20 Jul 2026 15:08:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560124; cv=none; b=S6JVJqhqsTv6lQ6CeZA3TsrwIEbM8sD7nOxCy65nFVnxOgJLSQySf9mzfJZHTLoVWfhLFtWiGUc290qN2Un3Yap9e4kuyEbm1D/edtg5fkjZAowumnI+jWc3MRxUVxyXmfmwPm54U9fxQQTIrClbWWqHPHtcydBijolm/K+kNWk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560124; c=relaxed/simple; bh=Aif5jRlv7FbAEr+ujojpAGSKgOIGUwI6prHdmq3qkhQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GWTwRL2TKiMSGPjngcpWHwBB7UEl2Qzv1CE7UvypnT8C6B6AYphKPgIazR3VZW70R8sfjkERcOC0dfuaf4XIfBS9DhphGlWNEUXO019QfQ8NS6PYACyVDyrWeom8y9Liy3E1RwcLobfZWHoH2TGJx2986Jm8hhDi66HxH3BvZ34= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=P7co5Xrj; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="P7co5Xrj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=e2 nYu9u3Jutd+nElU90XXHobR87pV+uv8qFn8mq8pVQ=; b=P7co5XrjYMyTZkVAHt /cKwUjkvIhjJZ13ufrkXHk5vM5fgZrivLl6avaptV5bMUovq4jhXCIXZtygS/sZR +JL7x8K/M6DAAQjnRDkZdy7NaHhN1mmKSkHIMUfKsECCiFfOhpsrgmMKlhUTM4b5 w7hQcCHbDNxtAcEn3lZ7fPc2E= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wD3b1rIOV5qyHOjKQ--.35310S3; Mon, 20 Jul 2026 23:07:56 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 09/16] PCI: dwc: intel-gw: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:12 +0800 Message-Id: <20260720150619.24733-10-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3b1rIOV5qyHOjKQ--.35310S3 X-Coremail-Antispam: 1Uf129KBjvJXoW7GF1xWrW8JrykKFy3Cr1fCrg_yoW8JF17pa y5Xr1jyFn5XF429F17A3Z8XF1Yy3ZxA3s3Ga97Gr1SvF9rCryDK3yqkryFkF9rGFW0vw1a kw1Utw17Grn8JrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pig_-QUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7AyzV2peOcx2MwAA3A Content-Type: text/plain; charset="utf-8" dw_pcie_host_init() calls .init before caching the offset, so inside .init we must call dw_pcie_get_pcie_cap() to obtain the offset (hardware is already enabled). The helper will cache the result for later use. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-intel-gw, the call chain is: static const struct dw_pcie_host_ops intel_pcie_dw_ops =3D { .init =3D intel_pcie_rc_init, }; intel_pcie_rc_init() -> intel_pcie_host_setup() -> intel_pcie_link_setup() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-intel-gw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index 348e579e683f..a891c3f8eb01 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -119,7 +119,7 @@ static void intel_pcie_ltssm_disable(struct intel_pcie = *pcie) static void intel_pcie_link_setup(struct intel_pcie *pcie) { u32 val; - u8 offset =3D dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); + u8 offset =3D dw_pcie_get_pcie_cap(&pcie->pci); =20 val =3D pcie_rc_cfg_rd(pcie, offset + PCI_EXP_LNKCTL); =20 --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FCCA42A7AA; Mon, 20 Jul 2026 15:08:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560117; cv=none; b=LEJsyWap736T1MZrnXSnjLT6snf1wh5ae1rSbkendI9fJ3c1aoll1x2EWjKhfuGK10/4Z0dakvB4W/m6eWYicMCFF+7FiIVQES1J+ap4FeatlXTigJVbHSuSIxhaEpG2vQqAeHv8gA4vjTthUyU84BLFO9K/4DrHPiZJ3Ao/s/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560117; c=relaxed/simple; bh=zSySQHbhIR5jy2BFEbRzYy23VNeqQZTs/FWYx57PtM8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NWB4ZyDA/QxEjoBkAeiw5z9XPhM0QvZYr5dXPy7pXomhoIQsO+AkQsXY+2Wlx0JajPG56Xo8tkODDBt6PKmJfSYaHa8nf5ulrAtjvwA6otU5ti2z9eu/HBlrXYxQnlQ175LRaz4+Q/osutjW3t/FAPqFf0Xlih07g4REWaDPfJE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=WHD25rbD; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="WHD25rbD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=P5 dtUmSCJE7DzqsEwcI8FKsNsEzR7pCOmSoVvece9QE=; b=WHD25rbD+O3j/PT/bT hZqCaT6y3aNagSE1KNUgmZzKqZzOjklu7qJiEGkfnex+zdNyzT4/sZb7/ExrlHfy I4u2eHHcW3SLMybgrWivdvpxISrVGWvUVfkR7jTgf03CFB4Dr4OPWN8z/k2quiWE mw5891+p7BDY6f5GDoCuVDVew= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wD3b1rIOV5qyHOjKQ--.35310S4; Mon, 20 Jul 2026 23:07:57 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 10/16] PCI: dwc: qcom-ep: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:13 +0800 Message-Id: <20260720150619.24733-11-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3b1rIOV5qyHOjKQ--.35310S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxAw4kWFW3Cw4fAFy7JFy3CFg_yoW5GFy8pa s0qrsIyr18Jr48XrsFka98XFnxWrn8Ary7Aa97Kw1fZa42v347Ja1jyryftFn7GFW7KryU Cr4rt3yxu3WYyFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pEzB-NUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCww2zV2peOc0BRQAA3u Content-Type: text/plain; charset="utf-8" dw_pcie_ep_init() no longer caches the offset automatically. For qcom-ep, hardware (clocks, PHY) is enabled only after PERST# deassert. Therefore, we must call dw_pcie_get_pcie_cap() in qcom_pcie_perst_deassert() after the resources are enabled, before any DBI access. This ensures the cached offset is valid for subsequent uses in interrupt handlers and ICC updates. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-qcom-ep, dw_pcie_find_capability() appears in: qcom_pcie_ep_probe() -> dw_pcie_ep_init() -> qcom_pcie_ep_enable_irq_resources() -> qcom_pcie_ep_global_irq_thread() -> qcom_pcie_ep_icc_update() -> dw_pcie_find_capability() -> qcom_pcie_ep_perst_irq_thread() -> qcom_pcie_perst_deassert() -> offset =3D dw_pcie_find_capability() (called twice) --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 56184e6ca6e6..16b0891f9571 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -307,15 +307,13 @@ static void qcom_pcie_dw_write_dbi2(struct dw_pcie *p= ci, void __iomem *base, static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) { struct dw_pcie *pci =3D &pcie_ep->pci; - u32 offset, status; - int speed, width; - int ret; + int speed, width, ret; + u32 status; =20 if (!pcie_ep->icc_mem) return; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - status =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + status =3D readw(pci->dbi_base + pci->pcie_cap + PCI_EXP_LNKSTA); =20 speed =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, status); width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, status); @@ -491,14 +489,15 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *p= ci) =20 dw_pcie_dbi_ro_wr_en(pci); =20 + dw_pcie_get_pcie_cap(pci); + /* Set the L0s Exit Latency to 2us-4us =3D 0x6 */ - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D pci->pcie_cap; val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); FIELD_MODIFY(PCI_EXP_LNKCAP_L0SEL, &val, 0x6); dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); =20 /* Set the L1 Exit Latency to be 32us-64 us =3D 0x6 */ - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); val =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); FIELD_MODIFY(PCI_EXP_LNKCAP_L1EL, &val, 0x6); dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14F9F3AB496; Mon, 20 Jul 2026 15:08:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560120; cv=none; b=TTCnLFnKfNLqnz9l9xvTgqT4tsEFc9pVYPEaUGxEXm3C/VnuTL1UoNz1BZ4vRaP5g56yne8giIgeR1W51KFRHMeoJ+QYjxVvTLkAoxCrDXYdLygPkVjnXKzutZ4l163AUy0rAAQHR5Lu6xwVjy08k1ZAZcANughZjIyGMWHOLmM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560120; c=relaxed/simple; bh=xvn+wBM6m6H4j2V5VrCDG7F+OqWRxP3XqIkHxq0xqNk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oNNKC/fUII/3pkTBhgRsiMh5xx3DPJkRI18UbFp1tB+AvEnARkJngF+dG2dLuYFeBMn5dM/cIx9FzNat34uX9pi08l+fiPhzJ5yqQxuSLLQQdSQylQJCjAxnswAPDZPKejNJ74byxWXZLELZQP/yhDd0/76wSIjczFIZqHQ753E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=kZgUgkgH; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="kZgUgkgH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Bh DWjSEv175HZK5Lkhl53A0JTo49xTss24i6v5jm7E4=; b=kZgUgkgHJL7Sf1yplc EnVrsUr+kYw+MnNaSlluBx5Yi7X5Bp4RB+P69pUgltAro9iVZSKW7dLWF5mbf370 LWNjY+SZWr9P+hZaEDuv9kpdl1fIU+SyfCYTwc0y5Jc3Sq+HbrVZs3IOtC3wGaC4 yWHKyq4Tktzljvj7NEpmiisuA= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wD3b1rIOV5qyHOjKQ--.35310S5; Mon, 20 Jul 2026 23:07:58 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 11/16] PCI: dwc: qcom: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:14 +0800 Message-Id: <20260720150619.24733-12-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3b1rIOV5qyHOjKQ--.35310S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxCF4xJFWUKFWfWw13Jr45GFg_yoWrCw4Dpa s0vrn0yF45Jr48WFnFyFZ3Xr1agrnxArW7Aa97Kr1SqF9xtryUGa1jyrySyFn3GFZrtFy7 Gry8tryUX3WrtrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0ziHa09UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC7A6zV2peOc52YQAA3S Content-Type: text/plain; charset="utf-8" dw_pcie_host_init() caches the offset after .init, so .post_init callbacks and later functions (.link_up, icc_opp_update) can use pci->pcie_cap directly. For .init itself, we must call dw_pcie_get_pcie_cap() inside qcom_pcie_host_init() to obtain the offset (hardware is already enabled). Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-qcom, dw_pcie_find_capability() appears in multiple call chains: static const struct dw_pcie_host_ops qcom_pcie_dw_ops =3D { .init =3D qcom_pcie_host_init, }; qcom_pcie_host_init() -> qcom_pcie_clear_aspm_l0s() -> dw_pcie_find_capability() static const struct qcom_pcie_ops ops_* =3D { .post_init =3D qcom_pcie_post_init_*, }; qcom_pcie_post_init_*() -> qcom_pcie_set_slot_nccs() (for many versions) -> dw_pcie_find_capability() -> For 2_3_3 and 2_9_0: also calls dw_pcie_find_capability() directly static const struct dw_pcie_ops dw_pcie_ops =3D { .link_up =3D qcom_pcie_link_up, }; qcom_pcie_link_up() -> dw_pcie_find_capability() qcom_pcie_probe() -> dw_pcie_host_init() -> qcom_pcie_icc_opp_update() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-qcom.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index d8eb52857f69..bd383d7cb02b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -341,13 +341,13 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci) { struct qcom_pcie *pcie =3D to_qcom_pcie(pci); - u16 offset; + u8 offset; u32 val; =20 if (!pcie->cfg->no_l0s) return; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); =20 dw_pcie_dbi_ro_wr_en(pci); =20 @@ -360,7 +360,6 @@ static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pc= i) =20 static void qcom_pcie_set_slot_nccs(struct dw_pcie *pci) { - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; =20 dw_pcie_dbi_ro_wr_en(pci); @@ -370,9 +369,9 @@ static void qcom_pcie_set_slot_nccs(struct dw_pcie *pci) * notifications for the Hot-Plug commands. So set the NCCS field to * avoid waiting for the completions. */ - val =3D readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); + val =3D readl(pci->dbi_base + pci->pcie_cap + PCI_EXP_SLTCAP); val |=3D PCI_EXP_SLTCAP_NCCS; - writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); + writel(val, pci->dbi_base + pci->pcie_cap + PCI_EXP_SLTCAP); =20 dw_pcie_dbi_ro_wr_dis(pci); } @@ -935,7 +934,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) { struct dw_pcie *pci =3D pcie->pci; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; u32 val; =20 /* Force PHY out of lowest power state */ @@ -1257,7 +1256,7 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pci= e) static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) { struct dw_pcie *pci =3D pcie->pci; - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 offset =3D pci->pcie_cap; u32 val; int i; =20 @@ -1303,8 +1302,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie= *pcie) =20 static bool qcom_pcie_link_up(struct dw_pcie *pci) { - u16 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - u16 val =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + u16 val =3D readw(pci->dbi_base + pci->pcie_cap + PCI_EXP_LNKSTA); =20 return val & PCI_EXP_LNKSTA_DLLLA; } @@ -1664,15 +1662,14 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pci= e) =20 static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) { - u32 offset, status, width, speed; + u32 status, width, speed; struct dw_pcie *pci =3D pcie->pci; struct dev_pm_opp_key key =3D {}; unsigned long freq_kbps; struct dev_pm_opp *opp; int ret, freq_mbps; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - status =3D readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); + status =3D readw(pci->dbi_base + pci->pcie_cap + PCI_EXP_LNKSTA); =20 /* Only update constraints if link is up. */ if (!(status & PCI_EXP_LNKSTA_DLLLA)) --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3235843553E; Mon, 20 Jul 2026 15:08:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560119; cv=none; b=s+A3LmKNUtxH6kqMlLibLcfA0Asc8sZr6ZO37Vtuv+e7QJawVbRMyPnBVRJur6oCVVrJYblnSsKn6hg7wS1DWUkgv4JTXSoUEy8DxakAhbfjvpCC4zPOoQjOLMlhJoI4s2dER9qxY4Hcx8+/5E61wgp8pthtLrxzqfJWT2Gdjxc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560119; c=relaxed/simple; bh=GZRRdIebw/R7rBRANI0WHKYmQLKIYwinmBYXNPBBtRU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mqvez09vic6Ejke0EhAvSIz8/wNQ+isfOTs8xTVNaUjRP4qaQuoVXlTj/USL2fFxi5aVn/buOcg2Fhf6UeqCW7uv8HqbcgmbmhSUIU5T35J1j7lFEQeg1/8476mClIbDXaDThArBokpFztSfnEAWBvl4f+gXnrBQZQUqarxlPiw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Rsa4jCy4; arc=none smtp.client-ip=117.135.210.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Rsa4jCy4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=mA 809+5dKgIh5hEU/u2sEYn54hA7ngIexLFJ1RFII/4=; b=Rsa4jCy4DZD7SMWYo7 jBSCqh9Uym3kU3QnHscX2w+T5j8CfHl4x70kbASd0ua39cOpmpSZfFOEqU+hASMB M+lRnw9Rx7nT0npcoOUrBMQgY64hXsZ64tQML0k0CFYlpkNBIyZMKl7H1U0izOe6 EZuBeYsiFHxPVCQ09c8uU66gY= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wD3b1rIOV5qyHOjKQ--.35310S6; Mon, 20 Jul 2026 23:07:59 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 12/16] PCI: dwc: sophgo: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:15 +0800 Message-Id: <20260720150619.24733-13-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3b1rIOV5qyHOjKQ--.35310S6 X-Coremail-Antispam: 1Uf129KBjvJXoW7CF48WFW5tr1rXryrCry3Arb_yoW8Jw1kpa y5Zr4FkF4rJF4Yqa1Iy3WkZr1Yq3sxAryxJa93Gw4av34akFyDJw45tFyYgFnrGFWjyry3 KFn8t3W3WF98AwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pi9a9hUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6w+zV2peOc9vigAA3n Content-Type: text/plain; charset="utf-8" dw_pcie_host_init() calls .init before caching, so we must call dw_pcie_get_pcie_cap() inside .init. The hardware is already enabled by the driver's own initialization before this point. The helper will cache the offset and avoid redundant searches. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-sophgo, the call chain is: static const struct dw_pcie_host_ops sophgo_pcie_host_ops =3D { .init =3D sophgo_pcie_host_init, }; sophgo_pcie_host_init() -> sophgo_pcie_disable_l0s_l1() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-sophgo.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-sophgo.c b/drivers/pci/control= ler/dwc/pcie-sophgo.c index 044088898819..39703d2b7b5f 100644 --- a/drivers/pci/controller/dwc/pcie-sophgo.c +++ b/drivers/pci/controller/dwc/pcie-sophgo.c @@ -164,9 +164,10 @@ static void sophgo_pcie_msi_enable(struct dw_pcie_rp *= pp) static void sophgo_pcie_disable_l0s_l1(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - u32 offset, val; + u8 offset; + u32 val; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); =20 dw_pcie_dbi_ro_wr_en(pci); =20 --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A40CD3C5DBB; Mon, 20 Jul 2026 15:08:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560119; cv=none; b=T7VhXIWHEJdi6XhonTRGa24i4C5ZixKMgekc+YIbneug1Mi6g1vSU3DTNSpvyUkqh1C2neLZHrkYEfgHXdzdb18mVIQEejEp5kDVeusrsy8IP28XjcJwJ+7U26FOHjD9b0VMn3EfeCdcgGdZNj+LPhTdsyVyQGIDlGJ3Jw1YkoY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560119; c=relaxed/simple; bh=7kuZgxbRxcfBpcO4AlzJeBjtFJr6PEda/pW7p8B9V/U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YQKKe+YQSBu5jEq55M+AvUtCMgzetbeydkkouiJprr+ENdLtdMxo2V+ZN5J8mC1lNDBxHeqgIt7eEpix0tMMjNsEHV2pToXKaxXbmZqJDYwazXWZwwoqLWnpYedcGl/imfRYZNgRvAAV+ox7QKtLgRu7NR2vI9vGWh+cneWlT9o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=GF+PwHNR; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="GF+PwHNR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=rb JVHVOturhJVseaFdgCutzkTWzNq56ytxEmv63ILZM=; b=GF+PwHNR5pTt4PDsWs T0s0PiiqjMWesPjJyyiowX5dFZfrnnirwrFYBQhSP0lrzpNSqY6cgjdv2QOJuIqq tIl5UUx1O9sm7a+L/BKoT/KuyihjJDqUqhlhhH1t+I8P1+BJiEsvrNc6nopIbVDj DvRKjT+EbgW3o8RLRY00CQ7rE= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wD3b1rIOV5qyHOjKQ--.35310S7; Mon, 20 Jul 2026 23:08:00 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 13/16] PCI: dwc: spacemit-k1: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:16 +0800 Message-Id: <20260720150619.24733-14-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3b1rIOV5qyHOjKQ--.35310S7 X-Coremail-Antispam: 1Uf129KBjvdXoWrKr1fWF1UGr15JF4rXr1kZrb_yoWkCrgE9F y3Jan7JrW5Cr90k3Zayw1aqr9Yy3y7X3W09a1ftF98Z3Z2qw1YgryDZFWkAa1UGrs7Xryf Gw1qvF1rC3yUKjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sRNVbytUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxBC0WGpeOdAGWwAA34 Content-Type: text/plain; charset="utf-8" Because .init runs before core caching, we call dw_pcie_get_pcie_cap() inside k1_pcie_disable_aspm_l1() to get the capability base, then add PCI_EXP_LNKCAP. Hardware is already enabled at this point. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-spacemit-k1, the call chain is: static const struct dw_pcie_host_ops k1_pcie_host_ops =3D { .init =3D k1_pcie_init, }; k1_pcie_init() -> k1_pcie_disable_aspm_l1() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-spacemit-k1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/co= ntroller/dwc/pcie-spacemit-k1.c index 04241df8fd59..3e741324f44a 100644 --- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c @@ -116,7 +116,7 @@ static void k1_pcie_disable_aspm_l1(struct k1_pcie *k1) u8 offset; u32 val; =20 - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + offset =3D dw_pcie_get_pcie_cap(pci); offset +=3D PCI_EXP_LNKCAP; =20 dw_pcie_dbi_ro_wr_en(pci); --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15116436BD4; Mon, 20 Jul 2026 15:08:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560121; cv=none; b=sKIs8KE8JkdcEBXR7Fy1rFJ9T08p6oOE8CosEGjp32wpKzilwghAQV2MIcjzYDVktHRpP+AhT1dZntb1lCWB4xqdPzBvBdksbijhLAY4gP7IdEfREwozKL/H+uij3E3QurwwyvQLfus4wWUm11nXulQGAZUiFO5NHS68xPcxE/U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560121; c=relaxed/simple; bh=lUMJBA5oUnnTXQALxg7z88nPxjG8v70kIBk50sr5d1k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Czzkzh9gHI6OyrDJ8L0weLtUyfPWvYIk6OeAHWRt8Cy7nzDJ5LBYDkBJhEMGBwTidlXi6k5swUIVEC8GoUAacf7g0ooh6ytJmM00O1ZVvVsePEgT0J8LUz3tFHGsGPVf5OoKKyzYkrHkMOVDQQWdBXyAJS5xJdNksEVv2+aVkeg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=p5auUxhn; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="p5auUxhn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=/i OTdtu/aTwGdJUNHIqJwX0fu5L6Cd4Ns7bFgW3B/CE=; b=p5auUxhnEfBNES3fQG /5lF37QXLQgFIFFyWudRnnYGV60U57RN3sj6TCtJPX4ApgYAU3FmWt7m0eVmv/rn 3q88jJs/6ELE9CYOkItHihO1HRuJRwJ5PIQR5RxfJhBgzyRQ2b04o3yH85Jyzema diLdDoIf3bPZ3EEr6o8wmxNr0= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wD3b1rIOV5qyHOjKQ--.35310S8; Mon, 20 Jul 2026 23:08:00 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 14/16] PCI: dwc: spear13xx: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:17 +0800 Message-Id: <20260720150619.24733-15-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3b1rIOV5qyHOjKQ--.35310S8 X-Coremail-Antispam: 1Uf129KBjvJXoW7GF1DKr1kCFyruF4ftrW8Zwb_yoW8JF1rpa 9xXry2yF1rJr4aqr42v3Z8Xr15t3s8urWqq39akw1SvF17CryUtrW5t34YyF13WFWqyry3 Kr1Uta4xWF98Jw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pi9a9hUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxBG0WGpeOdEGcgAA3R Content-Type: text/plain; charset="utf-8" Inside .init we must call dw_pcie_get_pcie_cap() to obtain the offset, because the core has not yet cached it. The hardware is already enabled by the driver's own initialization before this point. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-spear13xx, the call chain is: static const struct dw_pcie_host_ops spear13xx_pcie_host_ops =3D { .init =3D spear13xx_pcie_host_init, }; spear13xx_pcie_host_init() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-spear13xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/cont= roller/dwc/pcie-spear13xx.c index 01794a9d3ad2..6e4c11b497d4 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -122,7 +122,7 @@ static int spear13xx_pcie_host_init(struct dw_pcie_rp *= pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct spear13xx_pcie *spear13xx_pcie =3D to_spear13xx_pcie(pci); - u32 exp_cap_off =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u8 exp_cap_off =3D dw_pcie_get_pcie_cap(pci); u32 val; =20 spear13xx_pcie->app_base =3D pci->dbi_base + 0x2000; --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 814A03B960F; Mon, 20 Jul 2026 15:08:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560120; cv=none; b=ctumqXcRUol9osdZDsVdCFVQ4hUJH6TrUb7B105DNuvnd2ZA10WCnOHXUGt7vkmP0Paa+ivdH0mIH44b47Itx2YT5vizLbLhe8bMkG7g/GZ5GzcSXdeBCZ2y6szoe8303kcpV0uAhOdI4BeSKC4KfqDr2lJhBP1up0F1e0k52lI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560120; c=relaxed/simple; bh=bMErmdnUMpkcm6PndS0VqL63j5qilTdWF/Efbl+gFsA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oXSnMa56z2QsPN0rwCu0G1WxykG5o1E+lXt4lqAx0kj6ov+PymElrpBYI4Pe7L1AU51ZKCLjDgkGJYezwAVFw1yTvjgTUMBT1VATXpFzio6cx5Buo+hhXRvzHNFsCsjo2CiOrhJtGtZ1Cx6NSiY/KPpFZUcrMEq+m3gYQ5TRCbk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=X+REq//w; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="X+REq//w" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Om uI2Spp3n9kV5Al6PVnZ7ZuVvU00LmjtW0tSnMTkU8=; b=X+REq//wOe+JPBVZRf iKQ/Wg1l8eNIl04rCuJGnuOUVa50cGEdGMeJCu2Yh+d9tcScIZQEApLrC9W3a70f gFUMjuZVKj/ff/b7qjLQIxhMNH/WvppMBSfysyFsyVfa/P89hnK1ajV01wTpR5+r 8+94fpUyPI8nU9fmA6j71Lkxw= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-1 (Coremail) with SMTP id _____wD3b1rIOV5qyHOjKQ--.35310S9; Mon, 20 Jul 2026 23:08:01 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 15/16] PCI: dwc: tegra194: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:18 +0800 Message-Id: <20260720150619.24733-16-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3b1rIOV5qyHOjKQ--.35310S9 X-Coremail-Antispam: 1Uf129KBjvJXoW7trWfJrW7KFWkXFWkKFy3urg_yoW8KF18pa yfXrWFkr1UJr4SqFsrAan8ZF1F93sIyrW7GanagwsIvr17C347WwsYk3y5tF17CFZFyryU Cr18tFy7Gr15J37anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pi9a9hUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCwxG0WGpeOdEBugAA3Z Content-Type: text/plain; charset="utf-8" In host mode: tegra_pcie_dw_host_init() runs inside .start_link, which is called after dw_pcie_host_init() has cached the offset. However, the driver's own initialization already enables hardware, so calling dw_pcie_get_pcie_cap() is safe and will return the cached value. In endpoint mode: pex_ep_event_pex_rst_deassert() runs after hardware is enabled (PERST# deassert). Because the core no longer caches automatically, we call dw_pcie_get_pcie_cap() here to cache the offset for subsequent accesses. The helper performs the DBI read only when hardware is ready. Thus, the private pcie_cap_base is always valid and can still be used for register accesses. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-tegra194, dw_pcie_find_capability() appears in: static const struct dw_pcie_ops tegra_dw_pcie_ops =3D { .start_link =3D tegra_pcie_dw_start_link, }; tegra_pcie_dw_start_link() -> tegra_pcie_dw_host_init() -> dw_pcie_find_capability() tegra_pcie_dw_probe() case DW_PCIE_EP_TYPE: tegra_pcie_config_ep() -> pex_ep_event_pex_rst_deassert() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 795cef5a915d..bf482bc66a92 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -905,8 +905,7 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *p= p) pp->bridge->ops =3D &tegra_pci_ops; =20 if (!pcie->pcie_cap_base) - pcie->pcie_cap_base =3D dw_pcie_find_capability(&pcie->pci, - PCI_CAP_ID_EXP); + pcie->pcie_cap_base =3D dw_pcie_get_pcie_cap(pci); =20 val =3D dw_pcie_readl_dbi(pci, PCI_IO_BASE); val &=3D ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); @@ -1889,8 +1888,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegr= a_pcie_dw *pcie) dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); } =20 - pcie->pcie_cap_base =3D dw_pcie_find_capability(&pcie->pci, - PCI_CAP_ID_EXP); + pcie->pcie_cap_base =3D dw_pcie_get_pcie_cap(pci); =20 /* Clear Slot Clock Configuration bit if SRNS configuration */ if (pcie->enable_srns) { --=20 2.34.1 From nobody Sat Jul 25 02:13:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C85DA439337; Mon, 20 Jul 2026 15:08:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560125; cv=none; b=dQyD7nVcXGBSbIr5JS0WojcBMc6pEFD7eVKRl3ihXN4ofo9YmLOsBPxT7x4+DG7d1qcMNElLTIFotV0YxTZABRbjST7Wy2T4RsHQfFwxi008BmwyuCMxPfrxmqkX9nRZ+nBruKHNfjXk4Jkb2stW4VbdH5qsRwpR1hD68OlN35U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784560125; c=relaxed/simple; bh=66IBhF1pQmHCc5Bn86cYjQ39VKbzO0j4snPG+BTKAT0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=g9Z0cSKX99xu2m6LzfsA5sx0V5XvKkNNRZfy0wOCPUZejTjOJse/iGGe2XNQXfVVtC52m9AP3swJIbem2/lsshKmZn/SCYkyR/vG+moTsUl3PvX1ZeuE4CXBJPYDvA9lmTBjRMokVCViY9TWB84Bon4EgW3/D1qL0MXoE2N8KKo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=PL56MJC6; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="PL56MJC6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=VX L2XKRY5F3qPW2VboJTa9SPw1RX8rEnzJV3c1g8W44=; b=PL56MJC6Mw2Dm3beJw EGXf2JsTShEbMBOlljS+EgYO6qacNN2UjIkc8WYsI3Z3k7cA6sDekfjYsxzQ//WC ct1DT3oLvPkTGbHh3jinH59RtwXi3SySdmeiigJq4uG8QntqeP+JmCy4vww5lACu u6uUmyYQXJwiJIDj086urjZ4o= Received: from zhb.. (unknown []) by gzga-smtp-mtada-g1-3 (Coremail) with SMTP id _____wDX5ybVOV5q0OGYJQ--.29751S2; Mon, 20 Jul 2026 23:08:06 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com Cc: imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-amlogic@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 16/16] PCI: dwc: ultrarisc: Use cached PCIe capability offset Date: Mon, 20 Jul 2026 23:06:19 +0800 Message-Id: <20260720150619.24733-17-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720150619.24733-1-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wDX5ybVOV5q0OGYJQ--.29751S2 X-Coremail-Antispam: 1Uf129KBjvJXoW7ZFy7CF43CF1xGry8JFy7KFg_yoW8Grykpa y3WryjyF1Dtr4YvFs2v3WDXF13tFnxAr9xJanrGrnIvF1akrWUJ390k34rtFn7GFWUKryY kr1YyFy5Ga4rtwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pi0tCwUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbCxBa1WWpeOdYHFAAA32 Content-Type: text/plain; charset="utf-8" Inside .init we call dw_pcie_get_pcie_cap() to obtain the offset, because the core has not yet cached it. Hardware is already enabled by the driver before this point. Signed-off-by: Hans Zhang <18255117159@163.com> --- In pcie-ultrarisc, the call chain is: static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops =3D { .init =3D ultrarisc_pcie_host_init, }; ultrarisc_pcie_host_init() -> dw_pcie_find_capability() --- drivers/pci/controller/dwc/pcie-ultrarisc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/cont= roller/dwc/pcie-ultrarisc.c index 6ee661ceff67..3f6e3ab0aa69 100644 --- a/drivers/pci/controller/dwc/pcie-ultrarisc.c +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c @@ -49,7 +49,7 @@ static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64); dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val); =20 - cap_exp =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + cap_exp =3D dw_pcie_get_pcie_cap(pci); val =3D dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2); FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT); dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val); --=20 2.34.1