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charset="utf-8" From: Yemike Abhilash Chandra The DS90UB960 chip has two CSI-2 transmit ports (TX0 and TX1), but the current driver implementation only utilizes TX0. To enable TX1 as the active output port, the I2C Bidirectional Control Channel (BCC) mapping in the RX_PORT_CTL register must be configured to use I2C Slave Port 1. This patch adds a new function, ub960_parse_active_ports(), which is called during driver initialization to scan the device tree and identify which RX and TX ports are enabled. The function creates bitmasks representing the active ports and uses these masks to correctly configure the RX_PORT_CTL register, ensuring proper port routing for whichever TX port is in use. DS90UB960 data sheet: https://www.ti.com/lit/ds/symlink/ds90ub960-q1.pdf Signed-off-by: Yemike Abhilash Chandra Co-developed-by: Rishikesh Donadkar Signed-off-by: Rishikesh Donadkar --- drivers/media/i2c/ds90ub960.c | 46 ++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/ds90ub960.c b/drivers/media/i2c/ds90ub960.c index 15a9797b47ac..653dc7a4eee5 100644 --- a/drivers/media/i2c/ds90ub960.c +++ b/drivers/media/i2c/ds90ub960.c @@ -26,6 +26,7 @@ * - i2c-atr could be made embeddable instead of allocatable. */ =20 +#include #include #include #include @@ -76,6 +77,8 @@ =20 #define UB960_NUM_BC_GPIOS 4 =20 +#define UB960_CSI_TX0 BIT(4) + /* * Register map * @@ -114,6 +117,7 @@ #define UB960_SR_SCL_HIGH_TIME 0x0a #define UB960_SR_SCL_LOW_TIME 0x0b #define UB960_SR_RX_PORT_CTL 0x0c +#define UB960_SR_RX_PORT_CTL_BCC_MAP GENMASK(7, 4) #define UB960_SR_IO_CTL 0x0d #define UB960_SR_GPIO_PIN_STS 0x0e #define UB960_SR_GPIO_INPUT_CTL 0x0f @@ -589,6 +593,9 @@ struct ub960_data { u32 tx_data_rate; /* Nominal data rate (Gb/s) */ s64 tx_link_freq[1]; =20 + u8 rx_mask; + u8 tx_mask; + struct i2c_atr *atr; =20 struct { @@ -2538,7 +2545,18 @@ static int ub960_init_rx_ports_ub960(struct ub960_da= ta *priv) struct device *dev =3D &priv->client->dev; unsigned int port_lock_mask; unsigned int port_mask; - int ret; + u8 enabled_rxports_mask; + u8 enabled_rxports; + int ret =3D 0; + + /* Configure I2C interface for RX ports */ + enabled_rxports_mask =3D FIELD_PREP(UB960_SR_RX_PORT_CTL_BCC_MAP, priv->r= x_mask); + enabled_rxports =3D (priv->tx_mask & UB960_CSI_TX0) ? 0x00 : enabled_rxp= orts_mask; + + ret =3D ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, enabled_rxports_mas= k, + enabled_rxports, &ret); + if (ret) + return ret; =20 for_each_active_rxport(priv, it) { ret =3D ub960_init_rx_port_ub960(priv, it.rxport); @@ -4789,6 +4807,30 @@ static int ub960_parse_dt_txports(struct ub960_data = *priv) return 0; } =20 +static void ub960_parse_active_ports(struct ub960_data *priv) +{ + struct device *dev =3D &priv->client->dev; + int nport; + + priv->rx_mask =3D 0; + priv->tx_mask =3D 0; + + for (nport =3D 0; nport < priv->hw_data->num_rxports + priv->hw_data->num= _txports; nport++) { + struct fwnode_handle *ep_fwnode; + + ep_fwnode =3D fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), nport, 0,= 0); + if (!ep_fwnode) + continue; + + if (nport < priv->hw_data->num_rxports) + priv->rx_mask |=3D BIT(nport); + else + priv->tx_mask |=3D BIT(nport); + + fwnode_handle_put(ep_fwnode); + } +} + static int ub960_parse_dt(struct ub960_data *priv) { int ret; @@ -5162,6 +5204,8 @@ static int ub960_probe(struct i2c_client *client) if (ret) goto err_mutex_destroy; =20 + ub960_parse_active_ports(priv); + ret =3D ub960_parse_dt(priv); if (ret) goto err_disable_core_hw; --=20 2.34.1 From nobody Sat Jul 25 02:43:54 2026 Received: from mx0b-0002e601.pphosted.com (mx0b-0002e601.pphosted.com [148.163.154.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A69C83EF648; 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charset="utf-8" From: Jai Luthra Before this, the deserializer would ignore the virtual channel (VC) ID set in the incoming CSI packets, and set the ID to the RX port number in the outgoing packets. This was done to support multiple single-channel cameras, all sending packets with the same default VC ID =3D 0. Now we check which (and how many) channels are under use on any incoming FPDLink port, and map it to available channels on the outgoing CSI port. Add a dedicated virtual channel mapping for ub9702 deserializers which require different VC configuration compared to ub960. Update the configuration logic to select the appropriate map based on the deserializer type. Signed-off-by: Jai Luthra Co-developed-by: Rishikesh Donadkar Signed-off-by: Rishikesh Donadkar --- drivers/media/i2c/ds90ub960.c | 194 +++++++++++++++++++--------------- 1 file changed, 109 insertions(+), 85 deletions(-) diff --git a/drivers/media/i2c/ds90ub960.c b/drivers/media/i2c/ds90ub960.c index 653dc7a4eee5..9ce6d9e6e3e8 100644 --- a/drivers/media/i2c/ds90ub960.c +++ b/drivers/media/i2c/ds90ub960.c @@ -72,6 +72,7 @@ #define UB960_MAX_RX_NPORTS 4 #define UB960_MAX_TX_NPORTS 2 #define UB960_MAX_NPORTS (UB960_MAX_RX_NPORTS + UB960_MAX_TX_NPORTS) +#define UB960_MAX_VC 4 =20 #define UB960_MAX_PORT_ALIASES 8 =20 @@ -3471,40 +3472,100 @@ static int ub960_rxport_handle_events(struct ub960= _data *priv, u8 nport) */ =20 /* - * The current implementation only supports a simple VC mapping, where all= VCs - * from a one RX port will be mapped to the same VC. Also, the hardware - * dictates that all streams from an RX port must go to a single TX port. + * Map incoming streams with different virtual channels from 1-4 sensors to + * unique VCs on CSI TX0. Sensors using multiple VCs will work, but due to + * limited total channels (4) this will reduce the total number of sensors= that + * can work simultaneously. * - * This function decides the target VC numbers for each RX port with a sim= ple - * algorithm, so that for each TX port, we get VC numbers starting from 0, - * and counting up. + * The current implementation is limited to using a single CSI TX port + * at a time (either TX0 or TX1 and not both simultaneously), + * as that is the most common HW configuration found on boards with DS90UB= 960. + * For using both CSI TX0 & TX1 the below method will need significant cha= nges. * - * E.g. if all four RX ports are in use, of which the first two go to the - * first TX port and the secont two go to the second TX port, we would get - * the following VCs for the four RX ports: 0, 1, 0, 1. + * VC mapping differs between ub960 and ub9702 deserializers: + * For ub960: + * - Each VC uses 2 bits in the mapping register + * - Supports up to 4 virtual channels (VC0-VC3) + * For ub9702: + * - Each VC uses 4 bits in the mapping register + * - Currently uses only 2 virtual channels (VC0, VC1) * - * TODO: implement a more sophisticated VC mapping. As the driver cannot k= now - * what VCs the sinks expect (say, an FPGA with hardcoded VC routing), this - * probably needs to be somehow configurable. Device tree? + * The mapping registers determine which output VC a given input VC + * will be mapped to when forwarding data from the deserializer. */ -static void ub960_get_vc_maps(struct ub960_data *priv, - struct v4l2_subdev_state *state, u8 *vc) + +static void ub960_get_vc_maps(struct ub960_data *priv, u8 *vc_map) { - u8 cur_vc[UB960_MAX_TX_NPORTS] =3D {}; - struct v4l2_subdev_route *route; - u8 handled_mask =3D 0; + struct device *dev =3D &priv->client->dev; + u8 nport, available_vc =3D 0; =20 - for_each_active_route(&state->routing, route) { - unsigned int rx, tx; + for (nport =3D 0; nport < priv->hw_data->num_rxports; ++nport) { + struct v4l2_mbus_frame_desc source_fd; + bool used_vc[UB960_MAX_VC] =3D {false}; + u8 vc, cur_vc =3D available_vc; + int j, ret; + u8 map; =20 - rx =3D ub960_pad_to_port(priv, route->sink_pad); - if (BIT(rx) & handled_mask) + if (!priv->rxports[nport]) continue; =20 - tx =3D ub960_pad_to_port(priv, route->source_pad); + ret =3D v4l2_subdev_call(priv->rxports[nport]->source.sd, pad, + get_frame_desc, + priv->rxports[nport]->source.pad, + &source_fd); + /* Mark channels used in source in used_vc[] */ + if (!ret) { + for (j =3D 0; j < source_fd.num_entries; ++j) { + u8 source_vc =3D source_fd.entry[j].bus.csi2.vc; + + if (source_vc < UB960_MAX_VC) + used_vc[source_vc] =3D true; + } + } else if (ret =3D=3D -ENOIOCTLCMD) { + /* assume VC=3D0 is used if sensor driver doesn't provide info */ + used_vc[0] =3D true; + } else { + continue; + } + + /* Start with all channels mapped to first free output */ =20 - vc[rx] =3D cur_vc[tx]++; - handled_mask |=3D BIT(rx); + if (priv->hw_data->chip_type =3D=3D UB960) { + map =3D (cur_vc << 6) | (cur_vc << 4) | (cur_vc << 2) | + (cur_vc << 0); + } else { + map =3D (cur_vc << 4) | (cur_vc << 0); + } + + /* Map actually used to channels to distinct free outputs */ + for (vc =3D 0; vc < UB960_MAX_VC; ++vc) { + if (used_vc[vc]) { + if (priv->hw_data->chip_type =3D=3D UB960) { + /* For ub960: 2 bits per VC */ + map &=3D ~(0x03 << (2 * vc)); + map |=3D (cur_vc << (2 * vc)); + } else { + /* For ub9702: 4 bits per VC */ + map &=3D ~(0x0f << (4 * vc)); + map |=3D (cur_vc << (4 * vc)); + } + ++cur_vc; + } + } + + /* Don't enable port if we ran out of available channels */ + if (cur_vc > UB960_MAX_VC) { + dev_err(dev, + "No VCs available for RX port %d\n", + nport); + continue; + } + + /* Enable port and update map */ + vc_map[nport] =3D map; + available_vc =3D cur_vc; + dev_dbg(dev, "%s: VC map for port %d is 0x%02x", + __func__, nport, map); } } =20 @@ -3552,45 +3613,6 @@ static int ub960_disable_rx_port(struct ub960_data *= priv, unsigned int nport) UB960_SR_FWD_CTL1_PORT_DIS(nport), NULL); } =20 -/* - * The driver only supports using a single VC for each source. This functi= on - * checks that each source only provides streams using a single VC. - */ -static int ub960_validate_stream_vcs(struct ub960_data *priv) -{ - for_each_active_rxport(priv, it) { - struct v4l2_mbus_frame_desc desc; - int ret; - u8 vc; - - ret =3D v4l2_subdev_call(it.rxport->source.sd, pad, - get_frame_desc, it.rxport->source.pad, - &desc); - if (ret) - return ret; - - if (desc.type !=3D V4L2_MBUS_FRAME_DESC_TYPE_CSI2) - continue; - - if (desc.num_entries =3D=3D 0) - continue; - - vc =3D desc.entry[0].bus.csi2.vc; - - for (unsigned int i =3D 1; i < desc.num_entries; i++) { - if (vc =3D=3D desc.entry[i].bus.csi2.vc) - continue; - - dev_err(&priv->client->dev, - "rx%u: source with multiple virtual-channels is not supported\n", - it.nport); - return -ENODEV; - } - } - - return 0; -} - static int ub960_configure_ports_for_streaming(struct ub960_data *priv, struct v4l2_subdev_state *state) { @@ -3606,11 +3628,7 @@ static int ub960_configure_ports_for_streaming(struc= t ub960_data *priv, struct v4l2_subdev_route *route; int ret; =20 - ret =3D ub960_validate_stream_vcs(priv); - if (ret) - return ret; - - ub960_get_vc_maps(priv, state, vc_map); + ub960_get_vc_maps(priv, vc_map); =20 for_each_active_route(&state->routing, route) { struct ub960_rxport *rxport; @@ -3676,16 +3694,14 @@ static int ub960_configure_ports_for_streaming(stru= ct ub960_data *priv, for_each_active_rxport(priv, it) { unsigned long nport =3D it.nport; =20 - u8 vc =3D vc_map[nport]; - if (rx_data[nport].num_streams =3D=3D 0) continue; =20 switch (it.rxport->rx_mode) { case RXPORT_MODE_RAW10: ub960_rxport_write(priv, nport, UB960_RR_RAW10_ID, - rx_data[nport].pixel_dt | (vc << UB960_RR_RAW10_ID_VC_SHIFT), - &ret); + rx_data[nport].pixel_dt | (nport << UB960_RR_RAW10_ID_VC_SHIFT), + &ret); =20 ub960_rxport_write(priv, nport, UB960_RR_RAW_EMBED_DTYPE, @@ -3701,15 +3717,10 @@ static int ub960_configure_ports_for_streaming(stru= ct ub960_data *priv, =20 case RXPORT_MODE_CSI2_SYNC: case RXPORT_MODE_CSI2_NONSYNC: - if (priv->hw_data->chip_type =3D=3D UB960 || - priv->hw_data->chip_type =3D=3D UB954) { - /* Map all VCs from this port to the same VC */ - ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP, - (vc << UB960_RR_CSI_VC_MAP_SHIFT(3)) | - (vc << UB960_RR_CSI_VC_MAP_SHIFT(2)) | - (vc << UB960_RR_CSI_VC_MAP_SHIFT(1)) | - (vc << UB960_RR_CSI_VC_MAP_SHIFT(0)), - &ret); + if (priv->hw_data->chip_type =3D=3D UB960) { + ub960_rxport_write(priv, nport, + UB960_RR_CSI_VC_MAP, + vc_map[nport], &ret); } else { unsigned int i; =20 @@ -3717,8 +3728,7 @@ static int ub960_configure_ports_for_streaming(struct= ub960_data *priv, for (i =3D 0; i < 8; i++) ub960_rxport_write(priv, nport, UB9702_RR_VC_ID_MAP(i), - (nport << 4) | nport, - &ret); + vc_map[nport], &ret); } =20 break; @@ -3965,6 +3975,11 @@ static int ub960_set_routing(struct v4l2_subdev *sd, return _ub960_set_routing(sd, state, routing); } =20 +static inline u8 ub960_get_output_vc(u8 map, u8 input_vc) +{ + return (map >> (2 * input_vc)) & 0x03; +} + static int ub960_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, struct v4l2_mbus_frame_desc *fd) { @@ -3982,7 +3997,7 @@ static int ub960_get_frame_desc(struct v4l2_subdev *s= d, unsigned int pad, =20 state =3D v4l2_subdev_lock_and_get_active_state(&priv->sd); =20 - ub960_get_vc_maps(priv, state, vc_map); + ub960_get_vc_maps(priv, vc_map); =20 for_each_active_route(&state->routing, route) { struct v4l2_mbus_frame_desc_entry *source_entry =3D NULL; @@ -4025,7 +4040,16 @@ static int ub960_get_frame_desc(struct v4l2_subdev *= sd, unsigned int pad, fd->entry[fd->num_entries].length =3D source_entry->length; fd->entry[fd->num_entries].pixelcode =3D source_entry->pixelcode; =20 - fd->entry[fd->num_entries].bus.csi2.vc =3D vc_map[nport]; + if (priv->hw_data->chip_type =3D=3D UB960) + fd->entry[fd->num_entries].bus.csi2.vc =3D + (vc_map[nport] >> (2 * source_entry->bus.csi2.vc)) & 0x03; + else + fd->entry[fd->num_entries].bus.csi2.vc =3D + (vc_map[nport] >> (4 * source_entry->bus.csi2.vc)) & 0x0f; + + dev_dbg(dev, "Mapping sink %d/%d to output VC %d", + route->sink_pad, route->sink_stream, + fd->entry[fd->num_entries].bus.csi2.vc); =20 if (source_fd.type =3D=3D V4L2_MBUS_FRAME_DESC_TYPE_CSI2) { fd->entry[fd->num_entries].bus.csi2.dt =3D --=20 2.34.1