From nobody Sat Jul 25 03:21:06 2026 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E22B0281532; Mon, 20 Jul 2026 02:05:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.152 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784513128; cv=none; b=V5j3DIRermsAlsUMighMMwLuGo8s00N7zpzgsZVzWlwFBFT96op8QtOj3wvnVV6kQ2P8xO7+WTKhwA2cZMCxnnflCHbHrRhsPX30tLke3vdz4Zau7a/nmTUHNqA8UwqqZuZQF49k/AqbpIVJUhC5ZbuVWJx3s/4Y9jbrlczVNnA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784513128; c=relaxed/simple; bh=+H+IvnrluCyVX7JUSFzBakIcBmkkyE4myb1rGiHnoC8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZeWWvvxm1J/AZSLc0dFo5uKL5s1g900HzEEvHyQcjTQMc3t+Mv6DAwuqIazXMsmiF31MsVn+LvZRR1zvNyCakR0b1ZQkEuZkZ9Gvl7gvZABrUkhwA34b1aJ7M5eIPmHFFpoNATjf8TdruJXz1YvlqoBF9Vz4T9IXwOEUuQYwEB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=DeQfwH8z; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=R+UrFqV0; arc=none smtp.client-ip=80.241.56.152 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="DeQfwH8z"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="R+UrFqV0" Received: from smtp202.mailbox.org (smtp202.mailbox.org [10.196.197.202]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA512) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 4h3P3y52JJzKmxW; Mon, 20 Jul 2026 04:05:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1784513118; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oOGj7NgHOfYtmIXSGKq1OSkcTev6QSK8vz7ynL+0tWQ=; b=DeQfwH8zG1dqkvk1n1gELQWtU/Tu7xkC+FRL5daZK11fC/aHrF+LqP7n47q1CAtyN2gUuU bcyoplR0OJ3mStHbVU0toQ7Bt8q392Z6imTjxPV8S3fRJcoe6q10xsv0hJVVMx9LhpVAAI sZnwzwN494k4ip0E/XFhH6b4Wpn9Ph9LEdrXh7I0kaipOHoeooKrWi729DN5EjbroTQNbF 1ckzt6V+qpVlzMXmfRmi8U5ZG0uzhRke0wQjlzMWD2EM7L8hB0nHzgTUOYWRzbNJtLN9Gr wqSo3zoVK1kNfOnSEFeMoDR7AIzH5MQscj/CU0aJH2IWsrxF83vIe14iZdzRUA== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1784513117; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oOGj7NgHOfYtmIXSGKq1OSkcTev6QSK8vz7ynL+0tWQ=; b=R+UrFqV03tJucq6lWHjAeQ8JogvrCdLG1dMnoQJFOSJA8YKInEuG0WzzpBNF7u2sfU9OJw 0v4h5jzQipTdhzVuJtdBHUPYfYpJcOOTDdYSUenkvrosfyFuFAL/ed72K7pvUWS15t0nDU SqHVy7gfA9deP0J4wABCq9+mdTGlcWrc5tAbOA6yutzLKChSNrwQ9lSLHeObeG9reRHOGp mjtu7xMLJEd6P0yToZgMO3UBHijs+cdIrQ/wO953p9MvwV1eL9eWL9wR2RG3VWoCcFLZ5s PgpJgjDNgGsTfjbHdASlNIHeLeF2BoV/cLO/VTsHxR/KYijmBu2TtJFscpEAWQ== To: linux-pci@vger.kernel.org Cc: Marek Vasut , Krzysztof Kozlowski , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 1/5] dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car X5H PCIe4 compatible Date: Mon, 20 Jul 2026 04:02:29 +0200 Message-ID: <20260720020505.315335-2-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260720020505.315335-1-marek.vasut+renesas@mailbox.org> References: <20260720020505.315335-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: a7a6ca05f31cccb2dff X-MBO-RS-META: 5rttwbg4zpzpey6564ntqds5f6g3dp1o Document bindings for R-Car X5H (R8A78000) PCIe4 host module. The binding document is deliberately using "renesas,rcar-gen5-pcie4" DT compatible string to discern R-Car X5H PCIe4 controller supported by this binding, from R-Car X5H PCIe6 controller which will use a separate binding. The R-Car X5H PCIe4 controller does no longer include PHY register range, the PHY is now a separate IP and referenced via the 'phy' DT property. The 'reg' and 'reg-names' DT properties therefore differ between R-Car Gen4 PCIe and R-Car X5H PCIe4, and the difference is handled in the allOf section. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: Add RB from Krzysztof --- .../bindings/pci/rcar-gen4-pci-host.yaml | 74 +++++++++++++------ 1 file changed, 52 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml = b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml index 64f456c6a75a1..9767a52f3904e 100644 --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml @@ -10,30 +10,20 @@ title: Renesas R-Car Gen4 PCIe Host maintainers: - Yoshihiro Shimoda =20 -allOf: - - $ref: snps,dw-pcie.yaml# - properties: compatible: - items: - - enum: - - renesas,r8a779f0-pcie # R-Car S4-8 - - renesas,r8a779g0-pcie # R-Car V4H - - renesas,r8a779h0-pcie # R-Car V4M - - const: renesas,rcar-gen4-pcie # R-Car Gen4 - - reg: - maxItems: 7 - - reg-names: - items: - - const: dbi - - const: dbi2 - - const: atu - - const: dma - - const: app - - const: phy - - const: config + oneOf: + - items: + - enum: + - renesas,r8a779f0-pcie # R-Car S4-8 + - renesas,r8a779g0-pcie # R-Car V4H + - renesas,r8a779h0-pcie # R-Car V4M + - const: renesas,rcar-gen4-pcie # R-Car Gen4 + + - items: + - enum: + - renesas,r8a78000-pcie4 # R-Car X5H PCIe4 + - const: renesas,rcar-gen5-pcie4 # R-Car Gen5 PCIe4 =20 interrupts: maxItems: 4 @@ -84,6 +74,46 @@ required: - resets - reset-names =20 +allOf: + - $ref: snps,dw-pcie.yaml# + - if: + properties: + compatible: + contains: + const: renesas,rcar-gen4-pcie + then: + properties: + reg: + maxItems: 7 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: dma + - const: app + - const: phy + - const: config + - if: + properties: + compatible: + contains: + const: renesas,rcar-gen5-pcie4 + then: + properties: + reg: + maxItems: 6 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: dma + - const: app + - const: config + unevaluatedProperties: false =20 examples: --=20 2.53.0 From nobody Sat Jul 25 03:21:06 2026 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 765A2282F26; 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d=mailbox.org; s=mail20150812; t=1784513120; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lrLRIaFCiSjGKemS1+PTENGyKItMA/JqxcvMIUVTg2s=; b=lCIGUmGp1O15zUrwZjypYliMhdeTnTk3KSmPfEyYwaZGUJr3uVLjYKcO61vt1GslJo+plk ozeXajpQs9DepclamEjrW5+BUmdiPkHGYfiB72VNWqJtm0MK4mzamfzlHPgwNvU4yA31hc wgxJTKiodZL+XxPffvDGMGDFhY0JmUuu0/yicD4AqMCtV5JiYxGigjZ0Zr5v72DqYzUkvb 0I7NOx6qoECXOxE9Oh5eOlzPE1+rubkQfIAyPtzYNTNJR3G9aKqI9+0Y9tq3gy22AmbEHK fAALuqpO3l1u0qSmqWixZKrmByMnMoiatzbDwT48e2FosN3s8KdGMVxif/f1Kw== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 2/5] PCI: dwc: rcar-gen4: Rework rcar_gen4_pcie_drvdata .additional_common_init into .init Date: Mon, 20 Jul 2026 04:02:30 +0200 Message-ID: <20260720020505.315335-3-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260720020505.315335-1-marek.vasut+renesas@mailbox.org> References: <20260720020505.315335-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: 7443db17e511f9236b9 X-MBO-RS-META: 6eq3xis5bfhq79dkmbxex788uwqsg43m X-Rspamd-Queue-Id: 4h3P420JDkzKs8b Rework the current complicated initialization callchain that invokes host_init->common_init->additional_common_init() for host and ep_init->common_init->additional_common_init() for endpoint into simpler host_init->init() and ep_init->init() . The init callback is now always implmented for all R-Car Gen4 SoCs, therefore there is no need to check whether the callback is not NULL. For R-Car S4 the .init callback is rcar_gen4_pcie_common_init(), for R-Car V4H and V4M the .init callback is implemented using a new function rcar_gen4_v4h_v4m_pcie_init() which calls the common rcar_gen4_pcie_common_init() followed by R-Car V4H and V4M specific hardware initialization. The hardware initialization sequence remains unchanged. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: Rename additional_common_init to init, reworked from previous patch PCI: dwc: rcar-gen4: Return error code from .additional_common_init --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 56 ++++++++++++--------- 1 file changed, 32 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 5f7211b91ee5b..5724f64eadfad 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -87,7 +87,7 @@ MODULE_FIRMWARE(RCAR_GEN4_PCIE_FIRMWARE_NAME); =20 struct rcar_gen4_pcie; struct rcar_gen4_pcie_drvdata { - void (*additional_common_init)(struct rcar_gen4_pcie *rcar); + int (*init)(struct rcar_gen4_pcie *rcar); int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable); enum dw_pcie_device_mode mode; }; @@ -241,9 +241,6 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_= pcie *rcar) reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc); fsleep(1000); =20 - if (rcar->drvdata->additional_common_init) - rcar->drvdata->additional_common_init(rcar); - return 0; =20 err_unprepare: @@ -252,6 +249,31 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4= _pcie *rcar) return ret; } =20 +static int rcar_gen4_v4h_v4m_pcie_init(struct rcar_gen4_pcie *rcar) +{ + struct dw_pcie *dw =3D &rcar->dw; + u32 val; + int ret; + + /* R-Car Gen4 common initialization. */ + ret =3D rcar_gen4_pcie_common_init(rcar); + if (ret) + return ret; + + /* R-Car V4H and V4M specific additional initialization. */ + val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); + val &=3D ~PORT_LANE_SKEW_INSERT_MASK; + if (dw->num_lanes < 4) + val |=3D BIT(6); + dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); + + val =3D readl(rcar->base + PCIEPWRMNGCTRL); + val |=3D APP_CLK_REQ_N | APP_CLK_PM_EN; + writel(val, rcar->base + PCIEPWRMNGCTRL); + + return 0; +} + static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar) { struct dw_pcie *dw =3D &rcar->dw; @@ -420,7 +442,7 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *= pp) =20 gpiod_set_value_cansleep(dw->pe_rst, 1); =20 - ret =3D rcar_gen4_pcie_common_init(rcar); + ret =3D rcar->drvdata->init(rcar); if (ret) return ret; =20 @@ -487,7 +509,7 @@ static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_e= p *ep) struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); int ret; =20 - ret =3D rcar_gen4_pcie_common_init(rcar); + ret =3D rcar->drvdata->init(rcar); if (ret) return; =20 @@ -681,22 +703,6 @@ static int r8a779f0_pcie_ltssm_control(struct rcar_gen= 4_pcie *rcar, bool enable) return 0; } =20 -static void rcar_gen4_pcie_additional_common_init(struct rcar_gen4_pcie *r= car) -{ - struct dw_pcie *dw =3D &rcar->dw; - u32 val; - - val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); - val &=3D ~PORT_LANE_SKEW_INSERT_MASK; - if (dw->num_lanes < 4) - val |=3D BIT(6); - dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); - - val =3D readl(rcar->base + PCIEPWRMNGCTRL); - val |=3D APP_CLK_REQ_N | APP_CLK_PM_EN; - writel(val, rcar->base + PCIEPWRMNGCTRL); -} - static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar, u32 offset, u32 mask, u32 val) { @@ -848,23 +854,25 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_g= en4_pcie *rcar, bool enable } =20 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie =3D { + .init =3D rcar_gen4_pcie_common_init, .ltssm_control =3D r8a779f0_pcie_ltssm_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie_ep =3D { + .init =3D rcar_gen4_pcie_common_init, .ltssm_control =3D r8a779f0_pcie_ltssm_control, .mode =3D DW_PCIE_EP_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie =3D { - .additional_common_init =3D rcar_gen4_pcie_additional_common_init, + .init =3D rcar_gen4_v4h_v4m_pcie_init, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie_ep =3D { - .additional_common_init =3D rcar_gen4_pcie_additional_common_init, + .init =3D rcar_gen4_v4h_v4m_pcie_init, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, .mode =3D DW_PCIE_EP_TYPE, }; --=20 2.53.0 From nobody Sat Jul 25 03:21:06 2026 Received: from mout-p-103.mailbox.org (mout-p-103.mailbox.org [80.241.56.161]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 384A0282F1F; Mon, 20 Jul 2026 02:05:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.161 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784513129; cv=none; b=boTbv71vONGkqva9T0w3/Ax3InS/WfVyKisE9ysBpvpXcnN6t3npRq7RPeCvz8MhcMnFGD1djFSJa1v7tTzgGhiOh5sUjF/A9tfKo93rKqepXmMQB92tZVUj7mjV7FfQkysn0Aw7VCzLuXJRyXOTDj0BlKTWhWBbaBc1raAhz14= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="eCVCNSIL" Received: from smtp202.mailbox.org (smtp202.mailbox.org [10.196.197.202]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA512) (No client certificate requested) by mout-p-103.mailbox.org (Postfix) with ESMTPS id 4h3P4511ZPzKn8l; Mon, 20 Jul 2026 04:05:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1784513125; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=upke4j96P67TQl/si4nbcl5wUON9IBWPSX/vdoa7JVk=; b=kSrWqq9Tlv7UztALGdsf83oF6Z2NzUbGsrPCmYDoRfOopcWp6VXKqNkYayzm2A97nBORPs lmG5sDtqUJsNIZVvpsr25XqpQIuCghPQyNX0ApuqdqDR2uvPWK+FqW9l8nz6tElOJxtSIS 1gVzAJMlyv4XTgy2pOTW8gwzM8oKec8uKnSnXzUJj9TVGSx4ioAl8ZxwfL/DKBA7O9fTH7 oDtCodTeObrjcO2LgTMtB/uQu2lxySxi3WbrB/ars5CaTat3adDOFf30JNbb2qDzvjII1c FxPZKThOxrpipHMfBojdxuTWorwqbWivZDdmKRqh5LYyOryFxCBWkj3wsbmYEg== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1784513123; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=upke4j96P67TQl/si4nbcl5wUON9IBWPSX/vdoa7JVk=; b=eCVCNSILxFKfs6RWprQ+Uq9oMXRdUdUaatKi3yQ/eX0TIKW8/9LMpebqNUD7TmB9sNLiFx CpZ08H0zlIaXx4aE9iHhRI0qWahoncwaGMcAt++RfcixPUDYiFPYHBkNz2VxJj8G30uCiT yu0rK/spHaR6axkjD5DxUkOJt11rhK1on3vNAcQXou7B/Ytrzjg/6aKAPko+Eq20mzcfTG T3OdF8JUT2h0iznTWQYt1DCLlIB1v3Odgw0iG1Z+gBvLbDBeT6tswyHZTpVp9RXw4VjMgL Rk/ukXo2PfinbW/FhUfr+KZ/b7RqgzNNGFSHTz6KPoO6ySCSDA/QaU10v4aQ2w== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 3/5] PCI: dwc: rcar-gen4: Split .start_link into ltssm_control and speed_control Date: Mon, 20 Jul 2026 04:02:31 +0200 Message-ID: <20260720020505.315335-4-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260720020505.315335-1-marek.vasut+renesas@mailbox.org> References: <20260720020505.315335-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: 41c980f3f7a55eeb220 X-MBO-RS-META: 37fzax1n5r4j71ob7hw3xwcsuyzs1k9b Introduce new .speed_control callback and implement it on R-Car Gen4. The callback implements the second half of what is currently present in rcar_gen4_pcie_start_link(), and rcar_gen4_pcie_start_link() does call the .speed_control callback. This is a preparatory patch for R-Car Gen5 support, where the .speed_control implementation is different. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: No change --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 39 ++++++++++++++------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 5724f64eadfad..73b01e74b42cb 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -89,6 +89,7 @@ struct rcar_gen4_pcie; struct rcar_gen4_pcie_drvdata { int (*init)(struct rcar_gen4_pcie *rcar); int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable); + int (*speed_control)(struct rcar_gen4_pcie *rcar); enum dw_pcie_device_mode mode; }; =20 @@ -140,20 +141,10 @@ static int rcar_gen4_pcie_speed_change(struct dw_pcie= *dw) return -ETIMEDOUT; } =20 -/* - * Enable LTSSM of this controller and manually initiate the speed change. - * Always return 0. - */ -static int rcar_gen4_pcie_start_link(struct dw_pcie *dw) +static int rcar_gen4_pcie_speed_control(struct rcar_gen4_pcie *rcar) { - struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); - int i, changes, ret; - - if (rcar->drvdata->ltssm_control) { - ret =3D rcar->drvdata->ltssm_control(rcar, true); - if (ret) - return ret; - } + struct dw_pcie *dw =3D &rcar->dw; + int i, changes; =20 /* * Require direct speed change with retrying here if the max_link_speed @@ -177,6 +168,24 @@ static int rcar_gen4_pcie_start_link(struct dw_pcie *d= w) return 0; } =20 +/* + * Enable LTSSM of this controller and manually initiate the speed change. + * Always return 0. + */ +static int rcar_gen4_pcie_start_link(struct dw_pcie *dw) +{ + struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); + int ret; + + if (rcar->drvdata->ltssm_control) { + ret =3D rcar->drvdata->ltssm_control(rcar, true); + if (ret) + return ret; + } + + return rcar->drvdata->speed_control(rcar); +} + static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw) { struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); @@ -856,24 +865,28 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_g= en4_pcie *rcar, bool enable static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie =3D { .init =3D rcar_gen4_pcie_common_init, .ltssm_control =3D r8a779f0_pcie_ltssm_control, + .speed_control =3D rcar_gen4_pcie_speed_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie_ep =3D { .init =3D rcar_gen4_pcie_common_init, .ltssm_control =3D r8a779f0_pcie_ltssm_control, + .speed_control =3D rcar_gen4_pcie_speed_control, .mode =3D DW_PCIE_EP_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie =3D { .init =3D rcar_gen4_v4h_v4m_pcie_init, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, + .speed_control =3D rcar_gen4_pcie_speed_control, .mode =3D DW_PCIE_RC_TYPE, }; =20 static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie_ep =3D { .init =3D rcar_gen4_v4h_v4m_pcie_init, .ltssm_control =3D rcar_gen4_pcie_ltssm_control, + .speed_control =3D rcar_gen4_pcie_speed_control, .mode =3D DW_PCIE_EP_TYPE, }; =20 --=20 2.53.0 From nobody Sat Jul 25 03:21:06 2026 Received: from mout-p-101.mailbox.org (mout-p-101.mailbox.org [80.241.56.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BAC7277CA5; Mon, 20 Jul 2026 02:05:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.151 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784513136; cv=none; b=uP7vOtGfIKHzRAsgPfmWHGWWcMA2GP1D9HbrVcjlIoNbcB3d6N3FZA3RNdsk2KS1CFD+c7CmE3z8KUZ1l0zXrFZfhGJbjvXUhD5FwVEkQk/YyuqBkUBIMvY4ut8TiacetDNKlExJpKl7KllhbnJhhCjfyopIJYkIir79Es0W5KI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="X931V/0X" Received: from smtp202.mailbox.org (smtp202.mailbox.org [10.196.197.202]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA512) (No client certificate requested) by mout-p-101.mailbox.org (Postfix) with ESMTPS id 4h3P482hbdz8skS; Mon, 20 Jul 2026 04:05:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1784513128; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=njm3xdISsTV/ECNAw54Ext3jP7saCAxJKQEqqzCdqig=; b=tGM26k23FIqKhc5NLL2aMeWWWMcvwKIvpUaBygXtUsocQFri7UUD5Lim1/qO17nFrwx7by 6BXpwVH7www/905aMCAcDHbKQ+yli2p/q41C5BPohY9S1uVFYUx4tX3luOwjORywNmDirF WSPhLxWd1+kIUJbEQmuIXjUu2xrgRbykKGRHCXNSfgFcEQ5gx3f53Y+GDsrMW3w6cx7qI5 hlrTiTuaoDockqwYsS+zvs8SYFr6PX8SQEnFj9vdsUWMblVgdQSehQRsUlcCpn2w4rO6Dj p9yk2L7RbzqvU0JdMLECGmIQUS5hFLlxjVAldCzcravHq+2QYqVJt5d6QYXSVg== From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1784513126; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=njm3xdISsTV/ECNAw54Ext3jP7saCAxJKQEqqzCdqig=; b=X931V/0Xlm7lMbvGqhjy8+lTu8orP4SVQl3JpWzeZt9VhvFKDheJ6DjS/9gCvOKHVbW6c0 VhbeT+rByrxlSSGJO+mYY+rdhD40n4e2T2wdUdxL0fbCp5NLBKjZ0+avZ3cARqY6A9ePhQ GfeeegUjkEQRD9migZGAWFSH5iOtAeETz6WNvo9ui/28MftvE9bInjXaqaNTRkaAcATl69 JKIpW9pwE03KKW6zmPNrzj+Db3rkll0gwNaUhcXreq0CuTBVeLWS25JmeSB6Z70xH6XQbf dTi6UrwVib2LsEx5EgXsK40zPNX0VVe3nuCCC1b/QAyyTbKMcZxXZufYuDBZ5g== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 4/5] PCI: dwc: rcar-gen4: Handle PERST via reset subsystem Date: Mon, 20 Jul 2026 04:02:32 +0200 Message-ID: <20260720020505.315335-5-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260720020505.315335-1-marek.vasut+renesas@mailbox.org> References: <20260720020505.315335-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: 7b06da2ebe055c30912 X-MBO-RS-META: 6d5m96uxoqj7efk5iiyp41dqd3ehhcs9 Handle PERST via both GPIO and reset subsystem. On R-Car Gen4, the PERST signal is operated as a GPIO, on R-Car Gen5 it might only be accessible via SCMI reset via reset subsystem. Support both options. This is a preparatory patch for R-Car Gen5 support. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: - Use dev_err_probe() for perst in rcar_gen4_pcie_get_resources() - Use of_get_next_available_child() to obtain root port OF node - Switch to of_reset_control_get_optional_exclusive() to deal with R-Car Gen4, where the PERST is handled as GPIO instead of reset - Rename rcar_gen4_pcie_host_perst() to rcar_gen4_pcie_host_perst_asser= t() and use bool type for assert and deassert selection - Add missing reset_control_put() into rcar_gen4_pcie_probe() fail path --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 39 ++++++++++++++++++--- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 73b01e74b42cb..2ee8b344ec541 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -98,6 +98,7 @@ struct rcar_gen4_pcie { void __iomem *base; void __iomem *phy_base; struct platform_device *pdev; + struct reset_control *perst; const struct rcar_gen4_pcie_drvdata *drvdata; }; #define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw) @@ -316,12 +317,23 @@ static void rcar_gen4_pcie_unprepare(struct rcar_gen4= _pcie *rcar) =20 static int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar) { + struct device *dev =3D rcar->dw.dev; + struct device_node *root_port; + rcar->phy_base =3D devm_platform_ioremap_resource_byname(rcar->pdev, "phy= "); if (IS_ERR(rcar->phy_base)) return PTR_ERR(rcar->phy_base); =20 + root_port =3D of_get_next_available_child(dev->of_node, NULL); + rcar->perst =3D of_reset_control_get_optional_exclusive(root_port, "perst= "); + of_node_put(root_port); + if (IS_ERR(rcar->perst)) + return dev_err_probe(dev, PTR_ERR(rcar->perst), "Failed to get PERST#\n"= ); + /* Renesas-specific registers */ rcar->base =3D devm_platform_ioremap_resource_byname(rcar->pdev, "app"); + if (IS_ERR(rcar->base)) + reset_control_put(rcar->perst); =20 return PTR_ERR_OR_ZERO(rcar->base); } @@ -442,6 +454,22 @@ static int rcar_gen4_pcie_host_msi_init(struct dw_pcie= _rp *pp) return ret; } =20 +static void rcar_gen4_pcie_host_perst_assert(struct dw_pcie_rp *pp, bool a= ssert) +{ + struct dw_pcie *dw =3D to_dw_pcie_from_pp(pp); + struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); + + gpiod_set_value_cansleep(dw->pe_rst, assert); + + if (!rcar->perst) + return; + + if (assert) + reset_control_assert(rcar->perst); + else + reset_control_deassert(rcar->perst); +} + /* Host mode */ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp) { @@ -449,7 +477,7 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *= pp) struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); int ret; =20 - gpiod_set_value_cansleep(dw->pe_rst, 1); + rcar_gen4_pcie_host_perst_assert(pp, true); =20 ret =3D rcar->drvdata->init(rcar); if (ret) @@ -470,7 +498,7 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *= pp) =20 msleep(PCIE_T_PVPERL_MS); /* pe_rst requires 100msec delay */ =20 - gpiod_set_value_cansleep(dw->pe_rst, 0); + rcar_gen4_pcie_host_perst_assert(pp, false); =20 return 0; =20 @@ -484,7 +512,7 @@ static void rcar_gen4_pcie_host_deinit(struct dw_pcie_r= p *pp) struct dw_pcie *dw =3D to_dw_pcie_from_pp(pp); struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); =20 - gpiod_set_value_cansleep(dw->pe_rst, 1); + rcar_gen4_pcie_host_perst_assert(pp, true); rcar_gen4_pcie_common_deinit(rcar); } =20 @@ -654,7 +682,7 @@ static int rcar_gen4_pcie_probe(struct platform_device = *pdev) =20 err =3D rcar_gen4_pcie_prepare(rcar); if (err) - return err; + goto err_prepare; =20 err =3D rcar_gen4_add_dw_pcie(rcar); if (err) @@ -662,6 +690,8 @@ static int rcar_gen4_pcie_probe(struct platform_device = *pdev) =20 return 0; =20 +err_prepare: + reset_control_put(rcar->perst); err_unprepare: rcar_gen4_pcie_unprepare(rcar); =20 @@ -688,6 +718,7 @@ static void rcar_gen4_pcie_remove(struct platform_devic= e *pdev) =20 rcar_gen4_remove_dw_pcie(rcar); rcar_gen4_pcie_unprepare(rcar); + reset_control_put(rcar->perst); } =20 static int r8a779f0_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool e= nable) --=20 2.53.0 From nobody Sat Jul 25 03:21:06 2026 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B7A423EA94; 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d=mailbox.org; s=mail20150812; t=1784513129; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=M0FmG2kmaql9hnKmKKlfzRx38uaj2SHRPGIAXj+elyM=; b=e9zL0CZCi1zXEQHINt9tmR2PonVkss0Qvh26QCvJAo+rgsB1/sjBHkLoRZRRzQW112QzHU tYKGOEsaTLgeW2a4Wvp0/dcHPjpFUaNAx87lI67ueswesPZ6LVfAbBalU7L4KLzUys08AC hzmQFKoF77FGmNVPzhKNDj1OGjN7VX4iX3NlILiMnalfJxPGTwJdWEAAC1xwGSv4JFsx6q qCTUCr6epMZZdfC02HRighyrlGoUaqK7S9N90K6BHExXQJqIbhKzq/Td+u2kC0LOGMfwOv hh5Cdj5c/h9Fs4noiGBrF2Ug2rbKW9k97BuHqOLYNS0qZbdF0zmgtoKQLLkcHg== To: linux-pci@vger.kernel.org Cc: Marek Vasut , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Rob Herring , Yoshihiro Shimoda , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 5/5] PCI: dwc: rcar-gen4: Add support for R-Car X5H PCIe4 Date: Mon, 20 Jul 2026 04:02:33 +0200 Message-ID: <20260720020505.315335-6-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260720020505.315335-1-marek.vasut+renesas@mailbox.org> References: <20260720020505.315335-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: 18909668765b58c831e X-MBO-RS-META: obnr95ab6mi3xyr6mf1s83nxwr6z1c5h X-Rspamd-Queue-Id: 4h3P4C32x5zKn31 Add support for R8A78000 (R-Car X5H) PCIe4. This driver previously supported R-Car Gen4 S4/V4H/V4M. PCIe features of R-Car X5H PCIe4 are almost all the same. The controller initialization sequence is slightly different and is factored out into controller specific callbacks, in a manner similar to previous R-Car Gen4 handling. The controller does have a PHY attached to it, but the PHY is operated by a separate PHY driver, the PHY driver instance binding is handled in rcar_gen4_pcie_get_resources() and controlled in the aforementioned controller specific callbacks. The controller driver is deliberately using "renesas,rcar-gen5-pcie4" DT compatible string to discern R-Car X5H PCIe4 controller supported by this driver, from R-Car X5H PCIe6 controller which will most likely use a separate driver. The R-Car X5H PCIe4 controller embeds HDMA instead of EDMA embedded in the R-Car Gen4 PCIe controller, "dw-edma" driver supports both DMA variants. Endpoint mode is currently not implemented for R-Car Gen5 PCIe4. Signed-off-by: Marek Vasut --- Cc: "Krzysztof Wilczy=C5=84ski" Cc: Bjorn Helgaas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: No change --- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 115 +++++++++++++++++++- 1 file changed, 113 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 2ee8b344ec541..f403e11c884a4 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,7 @@ =20 /* MSI Capability */ #define MSICAP0 0x0050 +#define MSICAP0_MMESCAP_MASK GENMASK(19, 17) #define MSICAP0_MSIE BIT(16) =20 /* PCIe Interrupt Status 0 */ @@ -74,6 +76,11 @@ #define PCIEPWRMNGCTRL 0x0070 #define APP_CLK_REQ_N BIT(11) #define APP_CLK_PM_EN BIT(10) +#define APP_READY_ENTR_L23 BIT(6) +#define APP_REQ_ENTR_L1 BIT(5) + +/* PCI Express capability */ +#define EXPCAP(x) (0x0070 + (x)) =20 #define RCAR_NUM_SPEED_CHANGE_RETRIES 10 #define RCAR_MAX_LINK_SPEED 4 @@ -97,6 +104,7 @@ struct rcar_gen4_pcie { struct dw_pcie dw; void __iomem *base; void __iomem *phy_base; + struct phy *phy; struct platform_device *pdev; struct reset_control *perst; const struct rcar_gen4_pcie_drvdata *drvdata; @@ -169,6 +177,35 @@ static int rcar_gen4_pcie_speed_control(struct rcar_ge= n4_pcie *rcar) return 0; } =20 +static int rcar_gen5_pcie_speed_control(struct rcar_gen4_pcie *rcar) +{ + struct dw_pcie *dw =3D &rcar->dw; + u32 lnkcap =3D dw_pcie_readl_dbi(dw, EXPCAP(PCI_EXP_LNKCAP)); + u32 lnksta =3D dw_pcie_readw_dbi(dw, EXPCAP(PCI_EXP_LNKSTA)); + u32 val, retries; + + if ((lnksta & PCI_EXP_LNKSTA_CLS) =3D=3D (lnkcap & PCI_EXP_LNKCAP_SLS)) + return 0; + + /* Retrain link */ + val =3D dw_pcie_readl_dbi(dw, EXPCAP(PCI_EXP_LNKCTL)); + val |=3D PCI_EXP_LNKCTL_RL; + dw_pcie_writel_dbi(dw, EXPCAP(PCI_EXP_LNKCTL), val); + + /* Wait for link retrain */ + for (retries =3D 0; retries <=3D 10; retries++) { + lnksta =3D dw_pcie_readw_dbi(dw, EXPCAP(PCI_EXP_LNKSTA)); + + /* Check retrain flag */ + if (!(lnksta & PCI_EXP_LNKSTA_LT)) + break; + + usleep_range(1000, 1100); + } + + return 0; +} + /* * Enable LTSSM of this controller and manually initiate the speed change. * Always return 0. @@ -284,6 +321,44 @@ static int rcar_gen4_v4h_v4m_pcie_init(struct rcar_gen= 4_pcie *rcar) return 0; } =20 +static int rcar_gen5_pcie_init(struct rcar_gen4_pcie *rcar) +{ + struct dw_pcie *dw =3D &rcar->dw; + int ret; + u32 val; + + /* R-Car Gen4 and Gen5 common initialization. */ + ret =3D rcar_gen4_pcie_common_init(rcar); + if (ret) + return ret; + + /* R-Car Gen5 specific additional initialization. */ + ret =3D phy_init(rcar->phy); + if (ret) + return ret; + + dw_pcie_dbi_ro_wr_en(dw); + + val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); + val &=3D ~PORT_LANE_SKEW_INSERT_MASK; + if (dw->num_lanes < 8) + val |=3D BIT(6); + dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); + + val =3D dw_pcie_readl_dbi(dw, MSICAP0); + FIELD_MODIFY(MSICAP0_MMESCAP_MASK, &val, 4); + dw_pcie_writel_dbi(dw, MSICAP0, val); + + dw_pcie_dbi_ro_wr_dis(dw); + + val =3D readl(rcar->base + PCIEPWRMNGCTRL); + val |=3D APP_CLK_REQ_N | APP_CLK_PM_EN | + APP_READY_ENTR_L23 | APP_REQ_ENTR_L1; + writel(val, rcar->base + PCIEPWRMNGCTRL); + + return 0; +} + static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar) { struct dw_pcie *dw =3D &rcar->dw; @@ -321,8 +396,11 @@ static int rcar_gen4_pcie_get_resources(struct rcar_ge= n4_pcie *rcar) struct device_node *root_port; =20 rcar->phy_base =3D devm_platform_ioremap_resource_byname(rcar->pdev, "phy= "); - if (IS_ERR(rcar->phy_base)) - return PTR_ERR(rcar->phy_base); + if (IS_ERR(rcar->phy_base)) { + rcar->phy =3D devm_phy_get(dev, NULL); + if (IS_ERR(rcar->phy)) + return PTR_ERR(rcar->phy); + } =20 root_port =3D of_get_next_available_child(dev->of_node, NULL); rcar->perst =3D of_reset_control_get_optional_exclusive(root_port, "perst= "); @@ -743,6 +821,28 @@ static int r8a779f0_pcie_ltssm_control(struct rcar_gen= 4_pcie *rcar, bool enable) return 0; } =20 +static int rcar_gen5_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool = enable) +{ + u32 val; + + val =3D readl(rcar->base + PCIERSTCTRL1); + if (enable) { + val |=3D APP_LTSSM_ENABLE; + val &=3D ~APP_HOLD_PHY_RST; + } else { + val &=3D ~APP_LTSSM_ENABLE; + val |=3D APP_HOLD_PHY_RST; + } + writel(val, rcar->base + PCIERSTCTRL1); + + if (enable) + phy_power_on(rcar->phy); + else + phy_power_off(rcar->phy); + + return 0; +} + static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar, u32 offset, u32 mask, u32 val) { @@ -921,6 +1021,13 @@ static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen= 4_pcie_ep =3D { .mode =3D DW_PCIE_EP_TYPE, }; =20 +static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen5_pcie =3D { + .init =3D rcar_gen5_pcie_init, + .ltssm_control =3D rcar_gen5_pcie_ltssm_control, + .speed_control =3D rcar_gen5_pcie_speed_control, + .mode =3D DW_PCIE_RC_TYPE, +}; + static const struct of_device_id rcar_gen4_pcie_of_match[] =3D { { .compatible =3D "renesas,r8a779f0-pcie", @@ -938,6 +1045,10 @@ static const struct of_device_id rcar_gen4_pcie_of_ma= tch[] =3D { .compatible =3D "renesas,rcar-gen4-pcie-ep", .data =3D &drvdata_rcar_gen4_pcie_ep, }, + { + .compatible =3D "renesas,rcar-gen5-pcie4", + .data =3D &drvdata_rcar_gen5_pcie, + }, {}, }; MODULE_DEVICE_TABLE(of, rcar_gen4_pcie_of_match); --=20 2.53.0