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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13ce2ddfb35sm37963183c88.14.2026.07.20.21.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 21:51:19 -0700 (PDT) From: Hangxiang Ma Date: Mon, 20 Jul 2026 21:50:34 -0700 Subject: [PATCH v15 1/8] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Kaanapali CSI2 PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260720-kaanapali-camss-v15-1-c0b1c1167c5d@oss.qualcomm.com> References: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> In-Reply-To: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: KwChyaOFmVm9969CTCZh0zxKX0pwLZFY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfX0HQnYMgoq2L7 7PT51xWVze7CDCVeEmgXjmAhVgKt4vfG2JqENr5x1y3MkG+Dj6obhs/QMWQNwcI+Bjetl/0aEk4 w6m9wWHnl4fnZR+uA9bhOUk7iGfL+BRsC7MDc33M1MFIolF8+KpqwljgA4Eg5XPySGtScQTeJKJ taOmYbkLUNhLHvcttumO1/du7dCO9dTzrYwzc/KG36JCjMF3F/YZYezRL67HxhAy9b1/tbPngme zJ0t6wxT04ri6h9tiXqIs9Ii6hzeCUbx8Uy8FviMDn+zmgCJXrkPs5iE8/XHzfawoRpK9aREwhf IA+eQQcNyOjj+QkRTs3pEn2ouBtxqYqXTVZPCqkICstwQpSRIzplev4wN2EAD7BBt3GBUQqf18C OQ7Hlth/yZS6lzhFxcZn807teGmltGVZp8D4yCw5kNCSPwDd3VuCK7Lr/G3jDHRBWuxURtRcqAz +zRmQW9xNTZjuihj+ww== X-Authority-Analysis: v=2.4 cv=I9JVgtgg c=1 sm=1 tr=0 ts=6a5efaca cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=8sc_bQFcTW-iTt5i-CEA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: KwChyaOFmVm9969CTCZh0zxKX0pwLZFY X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfX7iudqi9sleRG VICnMV+pVDphzfnPOZBnV/oAdxeX8+SD6c1L3yv3OHF0I2krp6jDNkhK3HTLENSOfhztAoGHkhs r/sg97a0CdW3NcRptzVS9Oc1npkdv3A= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210046 The Kaanapali CSI2 PHY is compatible with the existing x1e80100 CSI2 C-PHY/DPHY binding. Add the "qcom,kaanapali-csi2-phy" compatible. Signed-off-by: Hangxiang Ma Reviewed-by: Bryan O'Donoghue --- Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.y= aml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml index 880fe602945c..7943049834f9 100644 --- a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml @@ -16,7 +16,9 @@ description: =20 properties: compatible: - const: qcom,x1e80100-csi2-phy + enum: + - qcom,kaanapali-csi2-phy + - qcom,x1e80100-csi2-phy =20 reg: maxItems: 1 --=20 2.34.1 From nobody Sat Jul 25 01:40:44 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 577A83B47F5 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13ce2ddfb35sm37963183c88.14.2026.07.20.21.51.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 21:51:21 -0700 (PDT) From: Hangxiang Ma Date: Mon, 20 Jul 2026 21:50:35 -0700 Subject: [PATCH v15 2/8] media: dt-bindings: Add CAMSS device for Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260720-kaanapali-camss-v15-2-c0b1c1167c5d@oss.qualcomm.com> References: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> In-Reply-To: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfX+/MABzSeCJzL 5pp7juArCF69w7vV0UL/L9FYLbM+3fOt2y6KzD0yux/PDrcM6Wot1B4eM2ehXGoa3CdP5NHcW62 hWgSnwW5xO0ZGkd+tXmeC4aV5nckxcDlNbTaI6RBkIiM10kRdo9pdwcFVsiog7wjxwDjMHWnOlN /m/Nw49ArofDRcNU9/rDfRChkKqBi8g0mQWSjKlAeJVW18qNpqo25dBS5rolcIsbLgwQw3Vuh2U /8BT/k7V3FovnYwOzhCLKkQOHQdtQCQsT5oLCopF8uniBgfuEar0WRDsP0owVmNM8W45WdiN6Jj F7SesQ1viw1+x7Oyd5KUp41v3lHidac5RRD8caUVe4WIbl7lx0D8kkPcwUYaCWLd6p+kfABIS+j xC85EuLAQrXbL+rqsRKffocK0fDySgOLZe+LXoAdxOWtDMqW/4eN7Lsmodi7v/9ygz+xTeKV7r+ CiHp64lQk9iAYnDC0pw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfXykJ/znt9zOIm kmr/5Ur11nTyX0xO8NqjCpvwGD/buAEh7UYjg37CQqdrjCXrgysmIiIFeU+rIFkEa8CVJ6/7N+a ukBR5qQIA/WIZfsrEfYC8GkZNFMdD0s= X-Authority-Analysis: v=2.4 cv=WNpPmHsR c=1 sm=1 tr=0 ts=6a5efacc cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=gEfo2CItAAAA:8 a=KKAkSRfTAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=7Lj6VqmjGphfb2gh5wsA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 a=sptkURWiP4Gy88Gu7hUp:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: w75dquttN_VR8FuxIEgluiwtmZM7KkQW X-Proofpoint-ORIG-GUID: w75dquttN_VR8FuxIEgluiwtmZM7KkQW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 suspectscore=0 spamscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210046 Add bindings for Camera Subsystem (CAMSS) on the Qualcomm Kaanapali platform. The Kaanapali platform provides: - 6 x CSIPHY (CSI Physical Layer) - 3 x TPG (Test Pattern Generator) - 3 x CSID (CSI Decoder) - 2 x CSID Lite - 3 x VFE (Video Front End), 5 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE Lite Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Signed-off-by: Hangxiang Ma --- .../bindings/media/qcom,kaanapali-camss.yaml | 426 +++++++++++++++++= ++++ 1 file changed, 426 insertions(+) diff --git a/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.y= aml b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml new file mode 100644 index 000000000000..57f57a16d477 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,kaanapali-camss.yaml @@ -0,0 +1,426 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,kaanapali-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali Camera Subsystem (CAMSS) + +maintainers: + - Hangxiang Ma + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,kaanapali-camss + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + reg: + maxItems: 13 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csitpg0 + - const: csitpg1 + - const: csitpg2 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 23 + + clock-names: + items: + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: cpas_ahb + - const: cpas_fast_ahb + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe2 + - const: cpas_vfe_lite + - const: csid + - const: csid_csiphy_rx + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: qdss_debug_xo + + interrupts: + maxItems: 10 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + phys: + maxItems: 6 + description: CSIPHY 0-5 PHYs used by the CSID controllers. + + phy-names: + items: + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + - const: sf_icp_mnoc + + iommus: + maxItems: 1 + + power-domains: + items: + - description: + IFE0 GDSC - Global Distributed Switch Controller for IFE0. + - description: + IFE1 GDSC - Global Distributed Switch Controller for IFE1. + - description: + IFE2 GDSC - Global Distributed Switch Controller for IFE2. + - description: + Titan GDSC - Global Distributed Switch Controller for the entire= camss. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports, one per CSID. Each port receives the CSI data + decoded by the matching CSIPHY. + + patternProperties: + "^port@[0-5]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY 0-5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + +patternProperties: + "^phy@[0-9a-f]+$": + $ref: /schemas/phy/qcom,x1e80100-csi2-phy.yaml# + unevaluatedProperties: false + description: + CSIPHY blocks decoding the incoming MIPI CSI2 sensor streams. + + "^opp-table(-.*)?$": + type: object + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - phys + - phy-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + isp@9253000 { + compatible =3D "qcom,kaanapali-camss"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + reg =3D <0x0 0x09253000 0x0 0x5e80>, + <0x0 0x09263000 0x0 0x5e80>, + <0x0 0x09273000 0x0 0x5e80>, + <0x0 0x092d3000 0x0 0x3880>, + <0x0 0x092e7000 0x0 0x3880>, + <0x0 0x093fd000 0x0 0x400>, + <0x0 0x093fe000 0x0 0x400>, + <0x0 0x093ff000 0x0 0x400>, + <0x0 0x09151000 0x0 0x20000>, + <0x0 0x09171000 0x0 0x20000>, + <0x0 0x09191000 0x0 0x20000>, + <0x0 0x092dc000 0x0 0x1300>, + <0x0 0x092f0000 0x0 0x1300>; + reg-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks =3D <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-names =3D "camnoc_nrt_axi", + "camnoc_rt_axi", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "cpas_vfe_lite", + "csid", + "csid_csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo"; + + interrupts =3D , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACT= IVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACT= IVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF QCOM_ICC_T= AG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus =3D <&apps_smmu 0x1c00 0x00>; + + power-domains =3D <&camcc CAM_CC_TFE_0_GDSC>, + <&camcc CAM_CC_TFE_1_GDSC>, + <&camcc CAM_CC_TFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names =3D "ife0", + "ife1", + "ife2", + "top"; + + phys =3D <&csiphy0 PHY_TYPE_DPHY>, + <&csiphy1 PHY_TYPE_DPHY>, + <&csiphy2 PHY_TYPE_DPHY>, + <&csiphy3 PHY_TYPE_DPHY>, + <&csiphy4 PHY_TYPE_DPHY>, + <&csiphy5 PHY_TYPE_DPHY>; + phy-names =3D "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + camss_csiphy0_inep0: endpoint@0 { + reg =3D <0>; + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&csiphy0_out>; + }; + }; + }; + + csiphy0: phy@9523000 { + compatible =3D "qcom,kaanapali-csi2-phy"; + reg =3D <0x0 0x09523000 0x0 0x2000>; + + clocks =3D <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13ce2ddfb35sm37963183c88.14.2026.07.20.21.51.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 21:51:23 -0700 (PDT) From: Hangxiang Ma Date: Mon, 20 Jul 2026 21:50:36 -0700 Subject: [PATCH v15 3/8] media: qcom: camss: Add Kaanapali compatible camss driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260720-kaanapali-camss-v15-3-c0b1c1167c5d@oss.qualcomm.com> References: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> In-Reply-To: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: DWicMU9-QTuaJd_GOcjZeal4SpktcW-l X-Authority-Analysis: v=2.4 cv=TIZ1jVla c=1 sm=1 tr=0 ts=6a5eface cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=Eph36bqoL6-XvbZcx_wA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfX8W767Uhbj+fx Q+JvH3MEOCSaz63mcojb3WC79VtOhMapftOwUyM5v11LqXguekechWkW+JkUQ6wWzanfdNO5FQ2 bv36q6dIlNl0O3DVMCP7c7Zb3tyqIz4= X-Proofpoint-GUID: DWicMU9-QTuaJd_GOcjZeal4SpktcW-l X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfX91r05MJLtHiz L3nBTuM+nCI6+q9kSizvoJUtDHpvZoFgs+1TAViwAuTN4+1alIyBHDOxNE1aXZ4UGVmuBj7tPuY 5m/m9naMFqVfesZT3FRpii+9nOQgRMfq7xRrDxFZjMECyHYfT4aojyYHqDbaj9V0iv1S1t8N3PP oNQNCKjD7e9qWa/nO2UowouDiwywgg5dXbXipMAG1ubIxv/X7E2HVjwFgcoD5x4AMj6+7xLJjwj vnioyjE8LCvcFVgdwgcVQCNbRYMr+duDvnp8HIX6bE8UX6mWjwnV1L6lmrpsas/+dPIbe8EeKKw cj1jM8SA9v4moZwL/qMoO7v1jVFrRULHHAFxI2r+VKZQkgbk5eazaLkThaJYdcN5Wg71vqC0gKS FitrSjSvk1fP4M4fAF/SGgoT31gd5HYw5Kwavbh8I8WlkXY17ar1smHszs7FWL8ENDEODVZfXjW QqWbqfdtX1l1AO8thuQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 spamscore=0 clxscore=1015 malwarescore=0 bulkscore=0 suspectscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210046 Add support for Kaanapali in the camss driver. Add high level resource information along with the bus bandwidth votes. Module level detailed resource information will be enumerated in the following patches of the series. Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index f360b2c99bf8..d41ac42919f2 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -35,6 +35,20 @@ =20 static const struct parent_dev_ops vfe_parent_dev_ops; =20 +static const struct resources_icc icc_res_kaanapali[] =3D { + { + .name =3D "ahb", + .icc_bw_tbl.avg =3D 150000, + .icc_bw_tbl.peak =3D 300000, + }, + /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */ + { + .name =3D "hf_mnoc", + .icc_bw_tbl.avg =3D 471860, + .icc_bw_tbl.peak =3D 925857, + }, +}; + static const struct camss_subdev_resources csiphy_res_8x16[] =3D { /* CSIPHY0 */ { @@ -5532,6 +5546,13 @@ static void camss_remove(struct platform_device *pde= v) camss_genpd_cleanup(camss); } =20 +static const struct camss_resources kaanapali_resources =3D { + .version =3D CAMSS_KAANAPALI, + .pd_name =3D "top", + .icc_res =3D icc_res_kaanapali, + .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), +}; + static const struct camss_resources msm8916_resources =3D { .version =3D CAMSS_8x16, .legacy_phy =3D true, @@ -5781,6 +5802,7 @@ static const struct camss_resources x1e80100_resource= s =3D { }; =20 static const struct of_device_id camss_dt_match[] =3D { + { .compatible =3D "qcom,kaanapali-camss", .data =3D &kaanapali_resources = }, { .compatible =3D "qcom,msm8916-camss", .data =3D &msm8916_resources }, { .compatible =3D "qcom,msm8939-camss", .data =3D &msm8939_resources }, { .compatible =3D "qcom,msm8953-camss", .data =3D &msm8953_resources }, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/plat= form/qcom/camss/camss.h index 698694d3064e..cea213dc36eb 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -96,6 +96,7 @@ enum camss_version { CAMSS_8550, CAMSS_8650, CAMSS_8775P, + CAMSS_KAANAPALI, CAMSS_X1E80100, }; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13ce2ddfb35sm37963183c88.14.2026.07.20.21.51.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 21:51:25 -0700 (PDT) From: Hangxiang Ma Date: Mon, 20 Jul 2026 21:50:37 -0700 Subject: [PATCH v15 4/8] phy: qcom-mipi-csi2: Parametrise the common status register offset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260720-kaanapali-camss-v15-4-c0b1c1167c5d@oss.qualcomm.com> References: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> In-Reply-To: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfX8oL6+ddpkI5r /K7FIGE8cSifv09QwOgylAUVj56DHoIPMq1pX5SwMEfyggH5C7hSURchpdxkxnYjwimHERlgJLD LvEW/17BTjq7CuvDDx2NCiEYe/KhC6U= X-Proofpoint-GUID: k2KKx39boQEuRNtgXB9taeU4JhrdwSBG X-Authority-Analysis: v=2.4 cv=OMYXGyaB c=1 sm=1 tr=0 ts=6a5efad0 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=P6Xs4Y00w1yHQXPR5eoA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: k2KKx39boQEuRNtgXB9taeU4JhrdwSBG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfX60gXM2BXth2D UTR5uLnHBes5SvDKaMb1er/zYN3yCVf0GGLxI5IJtiPvJtgVo5yZoJhxf5zEQX6jJoiUxjNkcF3 V05SZcbUHDKbJ4r9w3L/lyRIO8knptmWqYnnlU6DyDQ2t8ahx59rFWLArNOrRcsXUOlFpEfPfGu 1Jq9Jo+NnS4QC2Jc/7sFygOIE5reREXy2rh0IW5/Fq29TWP1pXgeGvGV9+f5ynBRSsDX2+1o/Kw NY7fhviFBm2mUR2N7+v7oy3NK2G66wHNGpSCi+at9AHuidiG1btSChoA8Ygo4AED6wfJW5ygIzS 5nmcvNM2pqPjjWDsLqpj9p6z9AwJSl9lq5gM+PsDogiQ0pJYvODoG6u6PwrHm/WDwtpxwmsBZ2X 65+XTrNshhPxltaSo474QB8uhfincajzm903q87FClbzZ7JaZoGApXzSI2MfLMrdYOaiK33lzG0 ddYJF2agWk0Av1Mibvg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 clxscore=1015 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210046 The CSI2 PHY common status registers are not at a fixed offset from the common register block across SoCs: x1e80100 uses 0xb0 while other 3PH v2.4.0 parts differ. Replace the hard-coded 0xb0 in CSIPHY_3PH_CMN_CSI_COMMON_STATUSn() with a per-SoC common_status_offset field in struct mipi_csi2phy_device_regs, initialising x1e80100 to 0xb0 so behaviour is unchanged. This is a no-functional-change preparation for describing other SoC offsets. Signed-off-by: Hangxiang Ma --- drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 16 +++++++++++----- drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 1 + 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/p= hy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c index 966d79c98f9b..8cd331cfb4b3 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -19,7 +19,8 @@ #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL10_IRQ_CLEAR_CMD BIT(0) -#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x= 4 * (n)) +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, common_status_offset, n)= \ + ((offset) + (common_status_offset) + 0x4 * (n)) =20 #define CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(n) ((0x200 * (n)) + 0x24) =20 @@ -176,19 +177,23 @@ static void phy_qcom_mipi_csi2_hw_version_read(struct= mipi_csi2phy_device *csi2p CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 6)); =20 tmp =3D readl_relaxed(csi2phy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 12)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, + regs->common_status_offset, 12)); csi2phy->hw_version =3D tmp; =20 tmp =3D readl_relaxed(csi2phy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 13)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, + regs->common_status_offset, 13)); csi2phy->hw_version |=3D (tmp << 8) & 0xFF00; =20 tmp =3D readl_relaxed(csi2phy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 14)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, + regs->common_status_offset, 14)); csi2phy->hw_version |=3D (tmp << 16) & 0xFF0000; =20 tmp =3D readl_relaxed(csi2phy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 15)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, + regs->common_status_offset, 15)); csi2phy->hw_version |=3D (tmp << 24) & 0xFF000000; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13ce2ddfb35sm37963183c88.14.2026.07.20.21.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 21:51:27 -0700 (PDT) From: Hangxiang Ma Date: Mon, 20 Jul 2026 21:50:38 -0700 Subject: [PATCH v15 5/8] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260720-kaanapali-camss-v15-5-c0b1c1167c5d@oss.qualcomm.com> References: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> In-Reply-To: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfXzyKWeU9mVMXk oUT/uqrRgd9FZQms9ZcwZWFbVPBsslddDsjjF+HDGa5co0zgzd6GyDCA3xZm9E6QWLWlz1wAE8l GzXk6krdt0dHXje7b224utkK/2FMuXm6uqd9fNQoolUE37cKElPB2Sc2DTnoTSXvphiUKxGsT60 W16EgmNBw0oqSMLsYawtVG8wO/hv8j+r1TjRpQijQOzkNW9hOkUFuSM5LSA67ki+gN5273lISg5 I1euGVLrCbrqo40Lp2p/XIs2Yn54642xfUJkLkpClJ+wYE7c6tPIk+DcBrqzrHVUa8rl8hnLhFs 4VNO4VJQz0VE1WyMY1UdIY1427ScdTh8dcV9iCKcDfs3Yx9GuNf8a8F8c+Ybz7HyCf4lCxyrv+r cLEAMOcQhDnlaTgFr0WiEzIoYR3efO7r5NmMxZ9vAEq8b8K2L0JggWgHCpXCR0Ddk4o/byyA/ja h3wVVaRk6wlz96AXBgQ== X-Proofpoint-ORIG-GUID: LmPs5ttNkr_oFLb1tgxAS2ouhvMjB6xO X-Proofpoint-GUID: LmPs5ttNkr_oFLb1tgxAS2ouhvMjB6xO X-Authority-Analysis: v=2.4 cv=M5F97Sws c=1 sm=1 tr=0 ts=6a5efad1 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=YI0lirVkik_cQ8OgtUwA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfXxy/tJUl5Lp4p nXbljsiD+5901XyCCCNKxzq9oneTXis7ly0KA6DiKwvJXLadXq5SfkYptEJKuKhQkiNTYl85TuF yMce+c+BJ/CN8NkXwMhHxWMEVZKwebs= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 spamscore=0 bulkscore=0 impostorscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210046 Add support for the v2.4.0 two-phase CSIPHY found on Kaanapali, where the PHY is driven by the standalone phy-qcom-mipi-csi2 DPHY driver rather than by CAMSS. Add the mipi_csi2_dphy_3nm_kaanapali configuration, which reuses the x1e80100 lane sequence, clocks, supplies and power domains but selects the v2.4.0 common status offset, and register the "qcom,kaanapali-csi2-phy" compatible. Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/camss.c | 53 ++++++++++++++++++= ++++ drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 16 +++++++ drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 1 + drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 1 + 4 files changed, 71 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index d41ac42919f2..c19190f2a439 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -35,6 +35,57 @@ =20 static const struct parent_dev_ops vfe_parent_dev_ops; =20 +static const struct camss_subdev_resources csiphy_res_kaanapali[] =3D { + /* CSIPHY0 */ + { + .csiphy =3D { + .id =3D 0, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY1 */ + { + .csiphy =3D { + .id =3D 1, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY2 */ + { + .csiphy =3D { + .id =3D 2, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY3 */ + { + .csiphy =3D { + .id =3D 3, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY4 */ + { + .csiphy =3D { + .id =3D 4, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, + /* CSIPHY5 */ + { + .csiphy =3D { + .id =3D 5, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + }, + }, +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "ahb", @@ -5549,8 +5600,10 @@ static void camss_remove(struct platform_device *pde= v) static const struct camss_resources kaanapali_resources =3D { .version =3D CAMSS_KAANAPALI, .pd_name =3D "top", + .csiphy_res =3D csiphy_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), + .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/p= hy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c index 8cd331cfb4b3..658a39463104 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -389,3 +389,19 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x= 1e =3D { .genpds =3D x1e_genpds, .num_genpds =3D ARRAY_SIZE(x1e_genpds), }; + +const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_3nm_kaanapali =3D { + .ops =3D &phy_qcom_mipi_csi2_ops_3ph_1_0, + .reg_info =3D { + .init_seq =3D lane_regs_x1e80100, + .lane_array_size =3D ARRAY_SIZE(lane_regs_x1e80100), + .common_regs_offset =3D 0x1000, + .common_status_offset =3D 0x138, + }, + .supply_names =3D (const char **)x1e_supplies, + .num_supplies =3D ARRAY_SIZE(x1e_supplies), + .clk_names =3D (const char **)x1e_clks, + .num_clk =3D ARRAY_SIZE(x1e_clks), + .genpds =3D x1e_genpds, + .num_genpds =3D ARRAY_SIZE(x1e_genpds), +}; diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/q= ualcomm/phy-qcom-mipi-csi2-core.c index aae049f0ec16..aaa81bbb4862 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c @@ -430,6 +430,7 @@ static int phy_qcom_mipi_csi2_probe(struct platform_dev= ice *pdev) =20 static const struct of_device_id phy_qcom_mipi_csi2_of_match_table[] =3D { { .compatible =3D "qcom,x1e80100-csi2-phy", .data =3D &mipi_csi2_dphy_4nm= _x1e }, + { .compatible =3D "qcom,kaanapali-csi2-phy", .data =3D &mipi_csi2_dphy_3n= m_kaanapali }, { } }; MODULE_DEVICE_TABLE(of, phy_qcom_mipi_csi2_of_match_table); diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualco= mm/phy-qcom-mipi-csi2.h index d6366f809e51..2355a1db9b94 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h @@ -94,5 +94,6 @@ struct mipi_csi2phy_device { }; =20 extern const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13ce2ddfb35sm37963183c88.14.2026.07.20.21.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 21:51:29 -0700 (PDT) From: Hangxiang Ma Date: Mon, 20 Jul 2026 21:50:39 -0700 Subject: [PATCH v15 6/8] media: qcom: camss: csid: Add support for CSID gen4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260720-kaanapali-camss-v15-6-c0b1c1167c5d@oss.qualcomm.com> References: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> In-Reply-To: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma , Atiya Kailany X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfX4IZ9Gd3DNf8f gXntkYIY2q3d/MvRLpeig9oZu68rK8UR0h/LDvHgFPgAuW1WactiDQnxtbRB3LLmXK0VKvthxjZ 7gUUTIsjI2C2HMnudheMvCGErSS18Mo= X-Proofpoint-GUID: D1BxWCau_YkManph3NHvYwH41cNtyOA2 X-Authority-Analysis: v=2.4 cv=FJErAeos c=1 sm=1 tr=0 ts=6a5efad4 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=hAI97D9Htgy7VLTQvtAA:9 a=4Q4zU7iZy6iiv8wZ:21 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfX709oBS/tFMQV 1siLcMU4XrUQlRRdepo8PdzGuyxt3lFgxpA9MnuErAQhtct/pA70+pXp6yZEmL546rgUoSGr+nI tl+cxOZeZ2fbkLelM7Vxf1G6GHXBpKwittcvZ2Bt0NcO4BiA3nJ35C046KH/WqzQBCVSRsAyk7j cBg9ZvYLzYaKY5MiegM3Znzheh+VDrnYM96gCv4xWasruGGIemWScSLGPoiyGBFFW4t7V6Uxo54 p12mRglKtZe9sCJ0ic1m2zU5psCFIqe3MKGiXQHUWxdOV+hg0BnrQzWo2maGjLxjB9uXS93MHkc tIIbU111UZZwp0YRp9JZogl7s4WglJq84/aVg8p2SOq8o1nvybJhzjYNTdwefasAiXVR/vijksT F8TKbyN2dgysNy8rMRB938dPRqEhyBZoTfdIFdgUx4yBP8sxaG9e8NWi2/xrS1ismqyjH8Dd2Aq 8tASiN9qSQtbIFAOgAg== X-Proofpoint-ORIG-GUID: D1BxWCau_YkManph3NHvYwH41cNtyOA2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 spamscore=0 suspectscore=0 bulkscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210046 Add more detailed resource information for CSID devices along with the driver for CSID gen4 that is responsible for CSID register configuration, module reset and IRQ handling for BUF_DONE events. In this CSID version, RUP and AUP update values are split into two registers along with a SET register. Accordingly, enhance the CSID interface to accommodate both the legacy combined reg_update and the split RUP and AUP updates. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/Makefile | 1 + .../media/platform/qcom/camss/camss-csid-gen4.c | 380 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-csid.h | 9 +- drivers/media/platform/qcom/camss/camss.c | 75 ++++ 4 files changed, 464 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index 27898b3cc7d3..cebfd947f28e 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -10,6 +10,7 @@ qcom-camss-objs +=3D \ camss-csid-680.o \ camss-csid-gen2.o \ camss-csid-gen3.o \ + camss-csid-gen4.o \ camss-csiphy.o \ camss-csiphy-2ph-1-0.o \ camss-csiphy-3ph-1-0.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen4.c b/drivers/= media/platform/qcom/camss/camss-csid-gen4.c new file mode 100644 index 000000000000..4ff2f41f70f7 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-csid-gen4.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-csid-gen4.c + * + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include + +#include "camss.h" +#include "camss-csid.h" +#include "camss-csid-gen3.h" + +/* Reset and Command Registers */ +#define CSID_RST_CFG 0x108 +#define RST_MODE BIT(0) +#define RST_LOCATION BIT(4) + +/* Reset and Command Registers */ +#define CSID_RST_CMD 0x10C +#define SELECT_HW_RST BIT(0) +#define SELECT_IRQ_RST BIT(2) +#define CSID_IRQ_CMD 0x110 +#define IRQ_CMD_CLEAR BIT(0) + +/* Register Update Commands, RUP/AUP */ +#define CSID_RUP_CMD 0x114 +#define CSID_AUP_CMD 0x118 +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi)) +#define CSID_RUP_AUP_CMD 0x11C +#define RUP_SET BIT(0) +#define MUP BIT(4) + +/* Top level interrupt registers */ +#define CSID_TOP_IRQ_STATUS 0x180 +#define CSID_TOP_IRQ_MASK 0x184 +#define CSID_TOP_IRQ_CLEAR 0x188 +#define INFO_RST_DONE BIT(0) +#define CSI2_RX_IRQ_STATUS BIT(2) +#define BUF_DONE_IRQ_STATUS BIT(3) + +/* Buffer done interrupt registers */ +#define CSID_BUF_DONE_IRQ_STATUS 0x1A0 +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET 16 +#define CSID_BUF_DONE_IRQ_MASK 0x1A4 +#define CSID_BUF_DONE_IRQ_CLEAR 0x1A8 +#define CSID_BUF_DONE_IRQ_SET 0x1AC + +/* CSI2 RX interrupt registers */ +#define CSID_CSI2_RX_IRQ_STATUS 0x1B0 +#define CSID_CSI2_RX_IRQ_MASK 0x1B4 +#define CSID_CSI2_RX_IRQ_CLEAR 0x1B8 +#define CSID_CSI2_RX_IRQ_SET 0x1BC + +/* CSI2 RX Configuration */ +#define CSID_CSI2_RX_CFG0 0x880 +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 +#define CSID_CSI2_RX_CFG1 0x884 +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) +#define CSI2_RX_CFG1_VC_MODE BIT(2) + +#define MSM_CSID_MAX_SRC_STREAMS_GEN4 (csid_is_lite(csid) ? 4 : 5) + +/* RDI Configuration */ +#define CSID_RDI_CFG0(rdi) (csid_is_lite(csid) ?\ + (0x3080 + 0x200 * (rdi)) :\ + (0x5480 + 0x200 * (rdi))) +#define RDI_CFG0_RETIME_BS BIT(5) +#define RDI_CFG0_TIMESTAMP_EN BIT(6) +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) +#define RDI_CFG0_DECODE_FORMAT 12 +#define RDI_CFG0_DT 16 +#define RDI_CFG0_VC 22 +#define RDI_CFG0_EN BIT(31) + +/* RDI Control and Configuration */ +#define CSID_RDI_CTRL(rdi) (csid_is_lite(csid) ?\ + (0x3088 + 0x200 * (rdi)) :\ + (0x5488 + 0x200 * (rdi))) +#define RDI_CTRL_START_CMD BIT(0) + +#define CSID_RDI_CFG1(rdi) (csid_is_lite(csid) ?\ + (0x3094 + 0x200 * (rdi)) :\ + (0x5494 + 0x200 * (rdi))) +#define RDI_CFG1_DROP_H_EN BIT(5) +#define RDI_CFG1_DROP_V_EN BIT(6) +#define RDI_CFG1_CROP_H_EN BIT(7) +#define RDI_CFG1_CROP_V_EN BIT(8) +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) + +/* RDI Pixel Store Configuration */ +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0x5498 + 0x200 * (rdi)) +#define RDI_PIX_STORE_CFG0_EN BIT(0) +#define RDI_PIX_STORE_CFG0_MIN_HBI 1 + +/* RDI IRQ Status in wrapper */ +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0x224 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_MASK(rdi) (0x228 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0x22C + (0x10 * (rdi))) +#define INFO_RUP_DONE BIT(23) + +static void __csid_aup_rup_trigger(struct csid_device *csid) +{ + /* trigger SET in combined register */ + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); +} + +static void __csid_aup_rup_clear(struct csid_device *csid, int port_id) +{ + /* Hardware clears the registers upon consuming the settings */ + csid->aup_update &=3D ~CSID_RUP_AUP_RDI(port_id); + csid->rup_update &=3D ~CSID_RUP_AUP_RDI(port_id); +} + +static void __csid_aup_update(struct csid_device *csid, int port_id) +{ + csid->aup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->aup_update, csid->base + CSID_AUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_reg_update(struct csid_device *csid, int port_id) +{ + csid->rup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->rup_update, csid->base + CSID_RUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_configure_rx(struct csid_device *csid, + struct csid_phy_config *phy) +{ + int val; + + val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + writel(val, csid->base + CSID_CSI2_RX_CFG0); + + val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; + writel(val, csid->base + CSID_CSI2_RX_CFG1); +} + +static void __csid_configure_rx_vc(struct csid_device *csid, int vc) +{ + int val; + + if (vc > 3) { + val =3D readl(csid->base + CSID_CSI2_RX_CFG1); + val |=3D CSI2_RX_CFG1_VC_MODE; + writel(val, csid->base + CSID_CSI2_RX_CFG1); + } +} + +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) +{ + int val =3D 0; + + if (enable) + val =3D RDI_CTRL_START_CMD; + + writel(val, csid->base + CSID_RDI_CTRL(rdi)); +} + +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rd= i) +{ + u32 val; + + /* + * Configure pixel store to allow absorption of hblanking or idle time. + * This helps with horizontal crop and prevents line buffer conflicts. + * Reset state is 0x8 which has MIN_HBI=3D4, we keep the default MIN_HBI + * and just enable the pixel store functionality. + */ + val =3D (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN; + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi)); +} + +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enabl= e, u8 port, u8 vc) +{ + u8 lane_cnt =3D csid->phy.lane_cnt; + u32 val; + + /* Source pads matching RDI channels on hardware. + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. + */ + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIRST= _SRC + port]; + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res->f= ormats->formats, + csid->res->formats->nformats, + input_format->code); + + if (!lane_cnt) + lane_cnt =3D 4; + + val =3D RDI_CFG0_TIMESTAMP_EN; + val |=3D RDI_CFG0_TIMESTAMP_STB_SEL; + val |=3D RDI_CFG0_RETIME_BS; + + /* note: for non-RDI path, this should be format->decode_format */ + val |=3D DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + val |=3D vc << RDI_CFG0_VC; + val |=3D format->data_type << RDI_CFG0_DT; + writel(val, csid->base + CSID_RDI_CFG0(port)); + + val =3D RDI_CFG1_PACKING_FORMAT_MIPI; + writel(val, csid->base + CSID_RDI_CFG1(port)); + + /* Configure pixel store using dedicated register in gen4 */ + if (!csid_is_lite(csid)) + __csid_configure_rdi_pix_store(csid, port); + + val =3D 0; + writel(val, csid->base + CSID_RDI_CTRL(port)); + + val =3D readl(csid->base + CSID_RDI_CFG0(port)); + + if (enable) + val |=3D RDI_CFG0_EN; + + writel(val, csid->base + CSID_RDI_CFG0(port)); +} + +static void csid_configure_stream(struct csid_device *csid, u8 enable) +{ + u8 i, k; + + __csid_configure_rx(csid, &csid->phy); + + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + __csid_configure_rdi_stream(csid, enable, i, 0); + __csid_configure_rx_vc(csid, 0); + + for (k =3D 0; k < CAMSS_INIT_BUF_COUNT; k++) + __csid_aup_update(csid, i); + + __csid_reg_update(csid, i); + + __csid_ctrl_rdi(csid, enable, i); + } + } +} + +static int csid_configure_testgen_pattern(struct csid_device *csid, s32 va= l) +{ + return 0; +} + +static void csid_subdev_reg_update(struct csid_device *csid, int port_id, + bool clear) +{ + if (clear) + __csid_aup_rup_clear(csid, port_id); + else + __csid_aup_update(csid, port_id); +} + +/** + * csid_isr - CSID module interrupt service routine + * @irq: Interrupt line + * @dev: CSID device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t csid_isr(int irq, void *dev) +{ + struct csid_device *csid =3D dev; + u32 val, buf_done_val; + u8 reset_done; + int i; + + val =3D readl(csid->base + CSID_TOP_IRQ_STATUS); + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + + reset_done =3D val & INFO_RST_DONE; + + buf_done_val =3D readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + val =3D readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + + if (val & INFO_RUP_DONE) + csid_subdev_reg_update(csid, i, true); + + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) + camss_buf_done(csid->camss, csid->id, i); + } + } + + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + if (reset_done) + complete(&csid->reset_complete); + + return IRQ_HANDLED; +} + +/** + * csid_reset - Trigger reset on CSID module and wait to complete + * @csid: CSID device + * + * Return 0 on success or a negative error code otherwise + */ +static int csid_reset(struct csid_device *csid) +{ + unsigned long time; + u32 val; + int i; + + reinit_completion(&csid->reset_complete); + + val =3D INFO_RST_DONE | BUF_DONE_IRQ_STATUS; + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + writel(val, csid->base + CSID_TOP_IRQ_MASK); + + val =3D 0; + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_GEN4; i++) { + if (csid->phy.en_vc & BIT(i)) { + /* + * Only need to clear buf done IRQ status here, + * RUP done IRQ status will be cleared once isr + * strobe generated by CSID_RST_CMD + */ + val |=3D BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i); + } + } + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK); + + /* Clear all IRQ status with CLEAR bits set */ + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + val =3D RST_LOCATION | RST_MODE; + writel(val, csid->base + CSID_RST_CFG); + + val =3D SELECT_HW_RST | SELECT_IRQ_RST; + writel(val, csid->base + CSID_RST_CMD); + + time =3D wait_for_completion_timeout(&csid->reset_complete, + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); + + if (!time) { + dev_err(csid->camss->dev, "CSID reset timeout\n"); + return -EIO; + } + + return 0; +} + +static void csid_subdev_init(struct csid_device *csid) +{ + csid->testgen.nmodes =3D CSID_PAYLOAD_MODE_DISABLED; +} + +const struct csid_hw_ops csid_ops_gen4 =3D { + .configure_stream =3D csid_configure_stream, + .configure_testgen_pattern =3D csid_configure_testgen_pattern, + .hw_version =3D csid_hw_version, + .isr =3D csid_isr, + .reset =3D csid_reset, + .src_pad_code =3D csid_src_pad_code, + .subdev_init =3D csid_subdev_init, + .reg_update =3D csid_subdev_reg_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media= /platform/qcom/camss/camss-csid.h index 5296b10f6bac..4f31ad303c4e 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -154,7 +154,13 @@ struct csid_device { void __iomem *base; u32 irq; char irq_name[30]; - u32 reg_update; + union { + u32 reg_update; + struct { + u32 rup_update; + u32 aup_update; + }; + }; struct camss_clock *clock; int nclocks; struct regulator_bulk_data *supplies; @@ -218,6 +224,7 @@ extern const struct csid_hw_ops csid_ops_340; extern const struct csid_hw_ops csid_ops_680; extern const struct csid_hw_ops csid_ops_gen2; extern const struct csid_hw_ops csid_ops_gen3; +extern const struct csid_hw_ops csid_ops_gen4; =20 /* * csid_is_lite - Check if CSID is CSID lite. diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index c19190f2a439..57d743a6e726 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -86,6 +86,79 @@ static const struct camss_subdev_resources csiphy_res_ka= anapali[] =3D { }, }; =20 +static const struct camss_subdev_resources csid_res_kaanapali[] =3D { + /* CSID0 */ + { + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE0 */ + { + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite0" }, + .interrupt =3D { "csid_lite0" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE1 */ + { + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite1" }, + .interrupt =3D { "csid_lite1" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_gen4, + .formats =3D &csid_formats_gen2 + } + } +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "ahb", @@ -5601,9 +5674,11 @@ static const struct camss_resources kaanapali_resour= ces =3D { .version =3D CAMSS_KAANAPALI, .pd_name =3D "top", .csiphy_res =3D csiphy_res_kaanapali, + .csid_res =3D csid_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), + .csid_num =3D ARRAY_SIZE(csid_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { --=20 2.34.1 From nobody Sat Jul 25 01:40:44 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCE6B387347 for ; Tue, 21 Jul 2026 04:51:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13ce2ddfb35sm37963183c88.14.2026.07.20.21.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 21:51:31 -0700 (PDT) From: Hangxiang Ma Date: Mon, 20 Jul 2026 21:50:40 -0700 Subject: [PATCH v15 7/8] media: qcom: camss: vfe: Add support for VFE gen4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260720-kaanapali-camss-v15-7-c0b1c1167c5d@oss.qualcomm.com> References: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> In-Reply-To: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma , Atiya Kailany X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: svFBJt2uon8Jh749Aem_rHKfJbfUg6IH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfX9EPzEryuDFFp DEkAEWQVh1YRqkGUvxUC2twvh7jArvMCmxfy/v5wRUJigRKWM8dLGuV4u1RVavwnKB5oErAT/37 rXQfyLdIyU4OB9WWHI9PQHzrFs7l4tEEcZWNG7753SGg+NzAf6pKP0h2T+IfiFXEazHASchvYG2 0hpDu5pinc8hh/ceezaG6aTq+Yul+xqYpic0cYM6Ss0ET6nneTgSmplAN9wol+pEmLic/9jNqj+ ASgRwPGeKJLsULBpfRfaGn2GmsaDku0rGoArK6VuN5GugEBhNiwUqr/55+k0s9N3vlfccGaL3q5 KNn4w7SX4qiy8j0W6CQEh/yXKbYdwTpBak10MaALTvNvz1+5AM68GkJmzGmrSLjjZ/sStpBfwqg WJWaGdQbLN28y8+oesUFP6B8qXKn8PB2t3MA5P+INfBrPpnxqHQvERaQZXkxGktW3IboSZvMu6D 1R4j7y3kqsN83E4gcuA== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfXx3kbk7kOCABH +NAgFQ2xx9rs06LNKlRudlQzObuIOuHOArMSXuNWfCo4iCZaQi+MBxVS1FyfYlAxUIjWebTMnkx uWCKFx3kxjH05ik1cG8bGuI19rW+eCM= X-Authority-Analysis: v=2.4 cv=daawG3Xe c=1 sm=1 tr=0 ts=6a5efad8 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=1ZGTSUkntXfq-hYXLBIA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: svFBJt2uon8Jh749Aem_rHKfJbfUg6IH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 clxscore=1015 adultscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210046 Add Video Front End (VFE) version gen4 as found on the Kaanapali SoC. The FULL front end modules in Kaanapali camera subsystem are called TFEs (Thin Front End), however, retaining the name VFE at places to maintain consistency and avoid unnecessary code changes. This change limits the VFE output lines to 3 for now as constrained by the CAMSS driver framework. Kaanapali architecture requires for the REG_UPDATE and AUP_UPDATE to be issued after all of the CSID configuration has been done. Additionally, the number of AUP_UPDATEs should match the number of buffers enqueued to the write master while it's being enabled. Although the real time data from TFE goes through the RT_CAMNOC, we are required to enable both the camnoc_rt_axi and camnoc_nrt_axi clocks for the PDX_NOC, that follows both the RT and NRT NOCs in this architecture, to ensure that both of the latter are idle after reset. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-vfe-gen4.c | 197 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-vfe.c | 9 +- drivers/media/platform/qcom/camss/camss-vfe.h | 2 + drivers/media/platform/qcom/camss/camss.c | 153 ++++++++++++++++ 5 files changed, 360 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index cebfd947f28e..b114ca37e36e 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -28,6 +28,7 @@ qcom-camss-objs +=3D \ camss-vfe-680.o \ camss-vfe-gen1.o \ camss-vfe-gen3.o \ + camss-vfe-gen4.o \ camss-vfe-vbif.o \ camss-video.o =20 diff --git a/drivers/media/platform/qcom/camss/camss-vfe-gen4.c b/drivers/m= edia/platform/qcom/camss/camss-vfe-gen4.c new file mode 100644 index 000000000000..d73d70898710 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-vfe-gen4.c + * + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen4 + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include + +#include "camss.h" +#include "camss-vfe.h" + +/* VFE-gen4 Bus Register Base Addresses */ +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000) + +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) + +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0x128) + +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x500 + (n) * 0x100) +#define WM_CFG_EN BIT(0) +#define WM_VIR_FRM_EN BIT(1) +#define WM_CFG_MODE BIT(16) +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x504 + (n) * 0x100) +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x508 + (n) * 0x100) +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x50C + (n) * 0x100) +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x514 + (n) * 0x100) +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF) +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x518 + (n) * 0x100) + +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x530 + (n) * 0= x100) +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x534 + (n) * = 0x100) + +/* VFE lite has no such registers */ +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x538 + (n) * 0x10= 0) +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x53C + (n) * 0x1= 00) + +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x560 + (n) * 0x10= 0) +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x564 + (n) = * 0x100) + +/* + * IFE write master client IDs + * + * VIDEO_FULL 0 + * VIDEO_DC4_Y 1 + * VIDEO_DC4_C 2 + * VIDEO_DC16_Y 3 + * VIDEO_DC16_C 4 + * DISPLAY_DS2_Y 5 + * DISPLAY_DS2_C 6 + * FD_Y 7 + * FD_C 8 + * PIXEL_RAW 9 + * STATS_AEC_BG 10 + * STATS_AEC_BHIST 11 + * STATS_TINTLESS_BG 12 + * STATS_AWB_BG 13 + * STATS_AWB_BFW 14 + * STATS_AF_BHIST 15 + * STATS_ALSC_BG 16 + * STATS_FLICKER_BAYERRS 17 + * STATS_TMC_BHIST 18 + * PDAF_0 19 + * PDAF_1 20 + * PDAF_2 21 + * PDAF_3 22 + * RDI0 23 + * RDI1 24 + * RDI2 25 + * RDI3 26 + * RDI4 27 + * + * IFE Lite write master client IDs + * + * RDI0 0 + * RDI1 1 + * RDI2 2 + * RDI3 3 + * GAMMA 4 + * STATES_BE 5 + */ +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n)) + +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *l= ine) +{ + struct v4l2_pix_format_mplane *pix =3D + &line->video_out.active_fmt.fmt.pix_mp; + + wm =3D RDI_WM(wm); + + /* no clock gating at bus input */ + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); + + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); + + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8, + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); + writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF), + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); + writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); + + /* no dropped frames, one irq per frame */ + if (!vfe_is_lite(vfe)) { + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); + } + + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); + + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); + + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) +{ + wm =3D RDI_WM(wm); + writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, + struct vfe_line *line) +{ + wm =3D RDI_WM(wm); + writel(addr >> 8, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); + + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr); +} + +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_i= d) +{ + int port_id =3D line_id; + + camss_reg_update(vfe->camss, vfe->id, port_id, false); +} + +static inline void vfe_reg_update_clear(struct vfe_device *vfe, + enum vfe_line_id line_id) +{ + int port_id =3D line_id; + + camss_reg_update(vfe->camss, vfe->id, port_id, true); +} + +static const struct camss_video_ops vfe_video_ops_gen4 =3D { + .queue_buffer =3D vfe_queue_buffer_v2, + .flush_buffers =3D vfe_flush_buffers, +}; + +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) +{ + vfe->video_ops =3D vfe_video_ops_gen4; +} + +static void vfe_global_reset(struct vfe_device *vfe) +{ + vfe_isr_reset_ack(vfe); +} + +static irqreturn_t vfe_isr(int irq, void *dev) +{ + /* nop */ + return IRQ_HANDLED; +} + +static int vfe_halt(struct vfe_device *vfe) +{ + /* rely on vfe_disable_output() to stop the VFE */ + return 0; +} + +const struct vfe_hw_ops vfe_ops_gen4 =3D { + .global_reset =3D vfe_global_reset, + .hw_version =3D vfe_hw_version, + .isr =3D vfe_isr, + .pm_domain_off =3D vfe_pm_domain_off, + .pm_domain_on =3D vfe_pm_domain_on, + .reg_update =3D vfe_reg_update, + .reg_update_clear =3D vfe_reg_update_clear, + .subdev_init =3D vfe_subdev_init, + .vfe_disable =3D vfe_disable, + .vfe_enable =3D vfe_enable_v2, + .vfe_halt =3D vfe_halt, + .vfe_wm_start =3D vfe_wm_start, + .vfe_wm_stop =3D vfe_wm_stop, + .vfe_buf_done =3D vfe_buf_done, + .vfe_wm_update =3D vfe_wm_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/= platform/qcom/camss/camss-vfe.c index 319d19158988..826ab85a44a1 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -353,6 +353,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 = sink_code, case CAMSS_8550: case CAMSS_8650: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: @@ -525,7 +526,8 @@ int vfe_enable_output_v2(struct vfe_line *line) =20 spin_lock_irqsave(&vfe->output_lock, flags); =20 - ops->reg_update_clear(vfe, line->id); + if (ops->reg_update_clear) + ops->reg_update_clear(vfe, line->id); =20 if (output->state > VFE_OUTPUT_RESERVED) { dev_err(vfe->camss->dev, @@ -552,7 +554,9 @@ int vfe_enable_output_v2(struct vfe_line *line) output->gen2.active_num++; ops->vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line); - ops->reg_update(vfe, line->id); + + if (!vfe->res->reg_update_after_csid_config) + ops->reg_update(vfe, line->id); } =20 spin_unlock_irqrestore(&vfe->output_lock, flags); @@ -2013,6 +2017,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe) case CAMSS_8550: case CAMSS_8650: case CAMSS_8775P: + case CAMSS_KAANAPALI: case CAMSS_X1E80100: ret =3D 16; break; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/= platform/qcom/camss/camss-vfe.h index ae9dad353a37..c402ef170c81 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -133,6 +133,7 @@ struct vfe_isr_ops { =20 struct vfe_subdev_resources { bool is_lite; + bool reg_update_after_csid_config; u8 line_num; bool has_pd; char *pd_name; @@ -249,6 +250,7 @@ extern const struct vfe_hw_ops vfe_ops_340; extern const struct vfe_hw_ops vfe_ops_480; extern const struct vfe_hw_ops vfe_ops_680; extern const struct vfe_hw_ops vfe_ops_gen3; +extern const struct vfe_hw_ops vfe_ops_gen4; =20 int vfe_get(struct vfe_device *vfe); void vfe_put(struct vfe_device *vfe); diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 57d743a6e726..e5cf1e42dbb1 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -159,6 +159,157 @@ static const struct camss_subdev_resources csid_res_k= aanapali[] =3D { } }; =20 +/* In Kaanapali, CAMNOC requires all CPAS_TFEX clocks + * to operate on any TFE Full. + */ +static const struct camss_subdev_resources vfe_res_kaanapali[] =3D { + /* VFE0 - TFE Full */ + { + .clock =3D { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb", + "vfe0_fast_ahb", "vfe0", + "cpas_vfe0", "cpas_vfe1", "cpas_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe0" }, + .interrupt =3D { "vfe0" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "ife0", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE1 - TFE Full */ + { + .clock =3D { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb", + "vfe1_fast_ahb", "vfe1", + "cpas_vfe0", "cpas_vfe1", "cpas_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe1" }, + .interrupt =3D { "vfe1" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "ife1", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE2 - TFE Full */ + { + .clock =3D { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb", + "vfe2_fast_ahb", "vfe2", + "cpas_vfe0", "cpas_vfe1", "cpas_vfe2", + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 360280000, 480000000, 630000000, 716000000, + 833000000 }, + { 0 }, + { 0 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe2" }, + .interrupt =3D { "vfe2" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .reg_update_after_csid_config =3D true, + .has_pd =3D true, + .pd_name =3D "ife2", + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE3 - IFE Lite */ + { + .clock =3D { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb", + "vfe_lite_ahb", "vfe_lite", + "cpas_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe_lite0" }, + .interrupt =3D { "vfe_lite0" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .reg_update_after_csid_config =3D true, + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE4 - IFE Lite */ + { + .clock =3D { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb", + "vfe_lite_ahb", "vfe_lite", + "cpas_vfe_lite", "camnoc_rt_axi", + "camnoc_nrt_axi", "qdss_debug_xo" }, + .clock_rate =3D { { 0 }, + { 0 }, + { 0 }, + { 0 }, + { 266666667, 400000000, 480000000 }, + { 0 }, + { 200000000, 300000000, 400000000, 480000000 }, + { 0 }, + { 0 } }, + .reg =3D { "vfe_lite1" }, + .interrupt =3D { "vfe_lite1" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .reg_update_after_csid_config =3D true, + .hw_ops =3D &vfe_ops_gen4, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, +}; + static const struct resources_icc icc_res_kaanapali[] =3D { { .name =3D "ahb", @@ -5675,10 +5826,12 @@ static const struct camss_resources kaanapali_resou= rces =3D { .pd_name =3D "top", .csiphy_res =3D csiphy_res_kaanapali, .csid_res =3D csid_res_kaanapali, + .vfe_res =3D vfe_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), .csid_num =3D ARRAY_SIZE(csid_res_kaanapali), + .vfe_num =3D ARRAY_SIZE(vfe_res_kaanapali), }; =20 static const struct camss_resources msm8916_resources =3D { --=20 2.34.1 From nobody Sat Jul 25 01:40:44 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66DC53E073E for ; Tue, 21 Jul 2026 04:51:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13ce2ddfb35sm37963183c88.14.2026.07.20.21.51.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 21:51:35 -0700 (PDT) From: Hangxiang Ma Date: Mon, 20 Jul 2026 21:50:41 -0700 Subject: [PATCH v15 8/8] media: qcom: camss: tpg: Add support for v2.4.0 TPG Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260720-kaanapali-camss-v15-8-c0b1c1167c5d@oss.qualcomm.com> References: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> In-Reply-To: <20260720-kaanapali-camss-v15-0-c0b1c1167c5d@oss.qualcomm.com> To: Bryan O'Donoghue , Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfXyk8B2w3iFqLA gUoo9bUjPuw3Yd2Wq/YCq232LIdcUMjh1kDWAvCEAVrS8nGnL5lJvZxu8jBsvWyi0mqBMNdEXdV o3U3wfd9qy4CO6CWSInEsM8f9GyvhMlEPcaxfAq4847z2nKYI1kGw2uHZEC8dxa/rUWwTDmsWPR bvAzfVavpPNPgZSAXT18/NDUsW2eyRQZEnQ+33mZQfBtEjbhxrKVnmqXc9XJmznxASxN6WunuJP 3WECZQXfdYVFWR87JAFI8Y/rK+thLaZBn5uOl3PEDtS2To97FtgxgN1rf58dEjB2RVac43dQVtp is15RFTKurHzWdBc+O8hqWQmZVsa4CWImiE131s2atX/F2latslEgdgSqm1fDD1hHCkObY4WvUh Mh8tu6tJHpKjsbMHEmZLx3VE3zW+kByT355OfGYxmpUb9SgtfrSfPRdWUgTsDMWm5Yk8rzz2Jzx WoMM2l2Zsg6fxf/aj1A== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA0NiBTYWx0ZWRfX2/1jthQ1t4K2 htnplRf1AKhngRbDknh+Fqd2ZgJQ/mRPlUJrZJwLZc/njS1hYPD56/mZkDxbk8R/X1pGqqtAzPY wDCbpWeaI5oRPjRPpIWAP7R8/goIPn0= X-Authority-Analysis: v=2.4 cv=WNpPmHsR c=1 sm=1 tr=0 ts=6a5efada cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=zvpRHedlNIWp6186mRgA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: yJJ5tcc6WbWuvxV3D7zaUrpNGjn_Xa7u X-Proofpoint-ORIG-GUID: yJJ5tcc6WbWuvxV3D7zaUrpNGjn_Xa7u X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 suspectscore=0 spamscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210046 Add support for the TPG found on Kaanapali. This TPG uses hardware version 2.4.0, which drives test-enable and reset through a separate TPG_CTRL_CMD register instead of TPG_CTRL, and routes its output into the CSID gen4 RX via the CSI2 TPG mux. Signed-off-by: Hangxiang Ma --- .../media/platform/qcom/camss/camss-csid-gen4.c | 15 ++++++++++-- drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 27 +++++++++++++++++-= ---- drivers/media/platform/qcom/camss/camss.c | 2 ++ 3 files changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen4.c b/drivers/= media/platform/qcom/camss/camss-csid-gen4.c index 4ff2f41f70f7..bc52e4a1135c 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen4.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen4.c @@ -63,6 +63,8 @@ #define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSI2_RX_CFG0_TPG_MUX_EN BIT(27) +#define CSI2_RX_CFG0_TPG_MUX_SEL GENMASK(29, 28) #define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 #define CSID_CSI2_RX_CFG1 0x884 #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) @@ -140,12 +142,21 @@ static void __csid_reg_update(struct csid_device *csi= d, int port_id) static void __csid_configure_rx(struct csid_device *csid, struct csid_phy_config *phy) { + struct camss *camss =3D csid->camss; int val; =20 val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; - val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) - << CSI2_RX_CFG0_PHY_NUM_SEL; + + if (camss->tpg && csid->tpg_linked && + camss->tpg[phy->csiphy_id].testgen.mode !=3D TPG_PAYLOAD_MODE_DISABLE= D) { + val |=3D FIELD_PREP(CSI2_RX_CFG0_TPG_MUX_SEL, phy->csiphy_id + 1); + val |=3D CSI2_RX_CFG0_TPG_MUX_EN; + } else { + val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + } + writel(val, csid->base + CSID_CSI2_RX_CFG0); =20 val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; diff --git a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c b/drivers/m= edia/platform/qcom/camss/camss-tpg-gen1.c index d29de5f93c18..770a9e5d5ba5 100644 --- a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c +++ b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c @@ -22,6 +22,7 @@ =20 #define TPG_HW_VER_2_0_0 TPG_HW_VER(2, 0, 0) #define TPG_HW_VER_2_1_0 TPG_HW_VER(2, 1, 0) +#define TPG_HW_VER_2_4_0 TPG_HW_VER(2, 4, 0) =20 #define TPG_HW_STATUS 0x4 =20 @@ -33,7 +34,9 @@ # define TPG_CTRL_OVERLAP_SHDR_EN BIT(10) # define TPG_CTRL_NUM_ACTIVE_VC GENMASK(31, 30) =20 -#define TPG_CLEAR 0x1F4 +#define TPG_CTRL_CMD 0x1F4 +# define TPG_CTRL_CMD_TEST_EN BIT(4) +# define TPG_CTRL_CMD_HW_RESET BIT(0) =20 /* TPG VC-based registers */ #define TPG_VC_n_GAIN_CFG(n) (0x60 + (n) * 0x60) @@ -164,18 +167,30 @@ static int tpg_stream_on(struct tpg_device *tpg) } =20 /* Global TPG control */ - val =3D FIELD_PREP(TPG_CTRL_TEST_EN, 1) | - FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) | + val =3D FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) | FIELD_PREP(TPG_CTRL_NUM_ACTIVE_VC, last_vc); - writel(val, tpg->base + TPG_CTRL); + + if (tpg->hw_version >=3D TPG_HW_VER_2_4_0) { + writel(val, tpg->base + TPG_CTRL); + writel(TPG_CTRL_CMD_TEST_EN, tpg->base + TPG_CTRL_CMD); + } else { + val |=3D FIELD_PREP(TPG_CTRL_TEST_EN, 1); + writel(val, tpg->base + TPG_CTRL); + } =20 return 0; } =20 static int tpg_reset(struct tpg_device *tpg) { - writel(0, tpg->base + TPG_CTRL); - writel(1, tpg->base + TPG_CLEAR); + /* + * On TPG older than v2.4.0 test-enable lives in TPG_CTRL, so clear it + * first; v2.4.0+ drives both test-enable and reset through TPG_CTRL_CMD. + */ + if (tpg->hw_version < TPG_HW_VER_2_4_0) + writel(0, tpg->base + TPG_CTRL); + + writel(TPG_CTRL_CMD_HW_RESET, tpg->base + TPG_CTRL_CMD); =20 return 0; } diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index e5cf1e42dbb1..252dc2fe4207 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -5825,11 +5825,13 @@ static const struct camss_resources kaanapali_resou= rces =3D { .version =3D CAMSS_KAANAPALI, .pd_name =3D "top", .csiphy_res =3D csiphy_res_kaanapali, + .tpg_res =3D tpg_res_x1e80100, .csid_res =3D csid_res_kaanapali, .vfe_res =3D vfe_res_kaanapali, .icc_res =3D icc_res_kaanapali, .icc_path_num =3D ARRAY_SIZE(icc_res_kaanapali), .csiphy_num =3D ARRAY_SIZE(csiphy_res_kaanapali), + .tpg_num =3D ARRAY_SIZE(tpg_res_x1e80100), .csid_num =3D ARRAY_SIZE(csid_res_kaanapali), .vfe_num =3D ARRAY_SIZE(vfe_res_kaanapali), }; --=20 2.34.1