From nobody Sat Jul 25 03:20:57 2026 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CAC83AFD01; Mon, 20 Jul 2026 06:29:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784528949; cv=none; b=jq/+cDbMXI5C4SZqPSPsK5t8dTKCVJfXKBiKexizq6XUumHEg71QQsFkdnnHwOWuh3/TnQZMBiva2QRA/Sv50UKCwVl4Jm8IRO8M7XS6YzrZydpPaJWvriPp+vz3zgizZrBOiFu1RR+r4rxnX1TPOeaIPhOO3OrIaA4IhwZxZqU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784528949; c=relaxed/simple; bh=yfsVzJZoxKOmotRG5Co7zwd3WiizVX7Adnc8AZ4LkfI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cFspiH2q0yYTCSC8gdBDVo9iZ4qLjgsXZ9lL9reAxK5gh6YNrqWAhclIMbtcgSKdPTnZmdPd+/Gj20w7e92bAercm1ye5SLpQCcv2Zv5G3YGYIB9buBeFSVidRkWhQISQQ+Rj24lwONMjulYksGB5NYy5Axm4RzZcfmXWFmmo3U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 0792F1A000C; Mon, 20 Jul 2026 08:28:59 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id C2DA31A0013; Mon, 20 Jul 2026 08:28:58 +0200 (CEST) Received: from lsvm11u0000395.swis.ap-northeast-2.aws.nxp.com (lsvm11u0000395.swis.ap-northeast-2.aws.nxp.com [10.52.9.99]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id B33F11800088; Mon, 20 Jul 2026 14:28:56 +0800 (+08) From: Joseph Guo Date: Mon, 20 Jul 2026 15:28:53 +0900 Subject: [PATCH 1/2] dt-bindings: arm: fsl: add i.MX952 FRDM board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260720-imx952_frdm-v1-1-6d145eaaa5c4@nxp.com> References: <20260720-imx952_frdm-v1-0-6d145eaaa5c4@nxp.com> In-Reply-To: <20260720-imx952_frdm-v1-0-6d145eaaa5c4@nxp.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, qijian.guo@oss.nxp.com, justin.jiang@nxp.com, joy.zou@nxp.com, Joseph Guo X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784528934; l=821; i=qijian.guo@nxp.com; s=20250519; h=from:subject:message-id; bh=yfsVzJZoxKOmotRG5Co7zwd3WiizVX7Adnc8AZ4LkfI=; b=bh9r0oonXiQwzq4N8pCtHqD4SmdNvYW7CA9YV9fwVPR0jZ2h3EtLBSd7ICXVGnur0axEhfFIp 6GFamEanO9xCo+8rfwuP25l9Aiu9ZEsBuQr+LfCgPETiVSIi3RQR/e2 X-Developer-Key: i=qijian.guo@nxp.com; a=ed25519; pk=VRjOOFhVecTRwBzK4mt/k3JBnHoYfuXKCm9FM+hHQhs= X-Virus-Scanned: ClamAV using ClamSMTP Add DT compatible string for NXP i.MX952 FRDM board. Signed-off-by: Joseph Guo Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 7b57a6ee1b50dc22ece292d6d9b53b5aa834ee96..f67b3f6d57d3623d41364f852a6= 4802ad2217560 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1536,6 +1536,7 @@ properties: items: - enum: - fsl,imx952-evk # i.MX952 EVK Board + - fsl,imx952-frdm # i.MX952 FRDM Board - const: fsl,imx952 =20 - description: PHYTEC i.MX 95 FPSC based Boards --=20 2.34.1 From nobody Sat Jul 25 03:20:57 2026 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E0453AFAFF; Mon, 20 Jul 2026 06:29:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=92.121.34.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784528955; cv=none; b=ivlV1uX2SdTdq3mo8WJhyCvt4hVklYu28LJr2tYEEZegmdMZSujGxHxoFcjuTVZd/WtDpdZ1H/qieJW94FxRXGniQhVVOaJxaXlf98mPyeTBvztUSRLNNw+3Lr6jW3jt1mAs3I+rVR/sw2PEIkZpsQpYbPV0v7U6+FJirXjAvm4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784528955; c=relaxed/simple; bh=0B4Mwu4vnHkY3lM87J3aMHIP71pxXSOO7xuTaewWZKM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D2NzSX1Nkzi7o+VnLPnWP7vtYk1VY3WhCaVNJxn+h3SJlIU4+XfiwST92/eCtL532Jnxkl/sSsPo4jItcGqFwY7TgwfOcYfPZhCK/XMl+SjXqt1yFZEdjdNY2NmAf+Jkucovvi4K64rxCJlYFHiSfs80aqM0F73HglKMzBqNiSk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; arc=none smtp.client-ip=92.121.34.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 0DE1A200038; Mon, 20 Jul 2026 08:29:01 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 8049D20004D; Mon, 20 Jul 2026 08:29:00 +0200 (CEST) Received: from lsvm11u0000395.swis.ap-northeast-2.aws.nxp.com (lsvm11u0000395.swis.ap-northeast-2.aws.nxp.com [10.52.9.99]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 5A97218000B1; Mon, 20 Jul 2026 14:28:58 +0800 (+08) From: Joseph Guo Date: Mon, 20 Jul 2026 15:28:54 +0900 Subject: [PATCH 2/2] arm64: dts: freescale: add i.MX952 FRDM Board support device tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260720-imx952_frdm-v1-2-6d145eaaa5c4@nxp.com> References: <20260720-imx952_frdm-v1-0-6d145eaaa5c4@nxp.com> In-Reply-To: <20260720-imx952_frdm-v1-0-6d145eaaa5c4@nxp.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, qijian.guo@oss.nxp.com, justin.jiang@nxp.com, joy.zou@nxp.com, Joseph Guo X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784528934; l=22528; i=qijian.guo@nxp.com; s=20250519; h=from:subject:message-id; bh=0B4Mwu4vnHkY3lM87J3aMHIP71pxXSOO7xuTaewWZKM=; b=8lB31OKlLu0LmcOwpTLxtPaaaWGZlGH40mZyhK7RW1sbB/T2XxJM+K6SuJ39Lb8qfAQ4gt0qo BW5p7kZwOYOD4WoA3CoRmS0mJDAEnchulK/d9yyyBPCHIYFmPRQ2fgg X-Developer-Key: i=qijian.guo@nxp.com; a=ed25519; pk=VRjOOFhVecTRwBzK4mt/k3JBnHoYfuXKCm9FM+hHQhs= X-Virus-Scanned: ClamAV using ClamSMTP Add basic device tree support for i.MX952 FRDM Board. The board-common hardware description is placed in imx952-frdm.dtsi so that it can be shared with future i.MX952-based FRDM derivative boards. The following peripherals are enabled: - LPUART1 (console), LPUART5 (BT) - USDHC1, USDHC2, USDHC3, - FlexCAN2, FlexCAN3, - USB1, USB2, - LPI2C2, LPI2C4 - WDOG3 - MICFIL (PDM) - LPSPI3 Signed-off-by: Joseph Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + arch/arm64/boot/dts/freescale/imx952-frdm.dts | 9 + arch/arm64/boot/dts/freescale/imx952-frdm.dtsi | 727 +++++++++++++++++++++= ++++ 3 files changed, 738 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index be3c858f1eeb1a807cb8ac36269c581143f755df..a9554dfc785fc43305ad45bb0b8= 0772041e91737 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -702,6 +702,8 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx95-19x19-verdin-evk.dtb =20 dtb-$(CONFIG_ARCH_MXC) +=3D imx952-evk.dtb =20 +dtb-$(CONFIG_ARCH_MXC) +=3D imx952-frdm.dtb + imx8mm-kontron-dl-dtbs :=3D imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo imx8mm-kontron-bl-lte-dtbs :=3D imx8mm-kontron-bl.dtb imx8mm-kontron-bl-l= te.dtbo =20 diff --git a/arch/arm64/boot/dts/freescale/imx952-frdm.dts b/arch/arm64/boo= t/dts/freescale/imx952-frdm.dts new file mode 100644 index 0000000000000000000000000000000000000000..0b9d74eea37668b455b945b25fe= b7d9c4fa5a439 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-frdm.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; + +#include "imx952.dtsi" +#include "imx952-frdm.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx952-frdm.dtsi b/arch/arm64/bo= ot/dts/freescale/imx952-frdm.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..b9ef6bec2bd5af522bb63f02443= 79524000957c8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-frdm.dtsi @@ -0,0 +1,727 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +#include + +#define BRD_SM_CTRL_SD3_WAKE 0x8000U /*!< PCAL6408A-0 */ +#define BRD_SM_CTRL_M2M_WAKE 0x8003U /*!< PCAL6408A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004U /*!< PCAL6408A-7 */ + +/ { + compatible =3D "fsl,imx952-frdm", "fsl,imx952"; + model =3D "NXP i.MX952 FRDM board"; + + aliases { + gpio0 =3D &gpio1; + gpio1 =3D &gpio2; + gpio2 =3D &gpio3; + gpio3 =3D &gpio4; + gpio4 =3D &gpio5; + i2c0 =3D &lpi2c1; + i2c1 =3D &lpi2c2; + i2c2 =3D &lpi2c3; + i2c3 =3D &lpi2c4; + i2c4 =3D &lpi2c5; + i2c5 =3D &lpi2c6; + i2c6 =3D &lpi2c7; + i2c7 =3D &lpi2c8; + mmc0 =3D &usdhc1; + mmc1 =3D &usdhc2; + serial0 =3D &lpuart1; + serial4 =3D &lpuart5; + spi2 =3D &lpspi3; + }; + + bt_sco_codec: audio-codec-bt-sco { + compatible =3D "linux,bt-sco"; + #sound-dai-cells =3D <1>; + }; + + chosen { + stdout-path =3D &lpuart1; + }; + + dmic: dmic { + compatible =3D "dmic-codec"; + #sound-dai-cells =3D <0>; + num-channels =3D <2>; + }; + + flexcan2_phy: can-phy0 { + compatible =3D "nxp,tja1051"; + #phy-cells =3D <0>; + max-bitrate =3D <8000000>; + silent-gpios =3D <&pcal6416 6 GPIO_ACTIVE_HIGH>; + }; + + flexcan3_phy: can-phy1 { + compatible =3D "nxp,tja1051"; + #phy-cells =3D <0>; + max-bitrate =3D <8000000>; + silent-gpios =3D <&pcal6416 6 GPIO_ACTIVE_HIGH>; + }; + + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "+V1.8_SW"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + }; + + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "+V3.3_SW"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + }; + + reg_5p0v: regulator-5p0v { + compatible =3D "regulator-fixed"; + regulator-name =3D "+V5.0_SW"; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible =3D "regulator-fixed"; + regulator-name =3D "vref_1v8"; + regulator-max-microvolt =3D <1800000>; + regulator-min-microvolt =3D <1800000>; + }; + + reg_dummy: regulator-dummy { + compatible =3D "regulator-fixed"; + regulator-name =3D "dummy"; + }; + + reg_ext_12v: regulator-ext-12v { + compatible =3D "regulator-fixed"; + regulator-name =3D "VCCEXT_12V"; + regulator-max-microvolt =3D <12000000>; + regulator-min-microvolt =3D <12000000>; + vin-supply =3D <®_ext_5v>; + }; + + reg_ext_3v3: regulator-ext-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VCCEXT_3V3"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + gpio =3D <&pcal6416 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_ext_5v: regulator-ext-5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "VCCEXT_5V"; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + gpio =3D <&pcal6416 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_m2_pwr: regulator-m2-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "M.2-power"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + gpio =3D <&pcal6416 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "VDD_SD2_3V3"; + off-on-delay-us =3D <12000>; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names =3D "default"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + gpio =3D <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "WLAN_EN"; + regulator-max-microvolt =3D <3300000>; + regulator-min-microvolt =3D <3300000>; + vin-supply =3D <®_m2_pwr>; + gpio =3D <&pcal6416 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us =3D <20000>; + }; + + reg_usb_vbus: regulator-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "USB_VBUS"; + regulator-max-microvolt =3D <5000000>; + regulator-min-microvolt =3D <5000000>; + gpio =3D <&pcal6416 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + linux_cma: linux,cma { + compatible =3D "shared-dma-pool"; + alloc-ranges =3D <0 0x80000000 0 0x7f000000>; + reusable; + size =3D <0 0x3c000000>; + linux,cma-default; + }; + }; + + sound-bt-sco { + compatible =3D "simple-audio-card"; + simple-audio-card,bitclock-inversion; + simple-audio-card,bitclock-master =3D <&btcpu>; + simple-audio-card,format =3D "dsp_a"; + simple-audio-card,frame-master =3D <&btcpu>; + simple-audio-card,name =3D "bt-sco-audio"; + + simple-audio-card,codec { + sound-dai =3D <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + dai-tdm-slot-num =3D <2>; + dai-tdm-slot-width =3D <16>; + sound-dai =3D <&sai5>; + }; + }; + + sound-micfil { + compatible =3D "fsl,imx-audio-card"; + model =3D "micfil-audio"; + + pri-dai-link { + format =3D "i2s"; + link-name =3D "micfil hifi"; + + codec { + sound-dai =3D <&dmic>; + }; + + cpu { + sound-dai =3D <&micfil>; + }; + }; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&pcal6416 8 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0 0x80000000>; + }; +}; + +&adc1 { + vref-supply =3D <®_vref_1v8>; + status =3D "okay"; +}; + +&asrc1 { + assigned-clocks =3D <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_ASRC1>; + assigned-clock-parents =3D <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates =3D <3932160000>, <3612672000>, + <393216000>, <361267200>, <49152000>; + fsl,asrc-rate =3D <48000>; + status =3D "okay"; +}; + +&asrc2 { + assigned-clocks =3D <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_ASRC2>; + assigned-clock-parents =3D <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates =3D <3932160000>, <3612672000>, + <393216000>, <361267200>, <49152000>; + fsl,asrc-rate =3D <48000>; + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2>; + phys =3D <&flexcan2_phy>; + status =3D "okay"; +}; + +&flexcan3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan3>; + phys =3D <&flexcan3_phy>; + status =3D "okay"; +}; + +&lpi2c2 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_lpi2c2>; + pinctrl-names =3D "default"; + status =3D "okay"; + + pcal6416: gpio@20 { + compatible =3D "nxp,pcal6416"; + reg =3D <0x20>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&gpio5>; + interrupts =3D <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells =3D <2>; + gpio-controller; + pinctrl-0 =3D <&pinctrl_pcal6416>; + pinctrl-names =3D "default"; + vcc-supply =3D <®_3p3v>; + + /* When low, select CAN; When high, select gpio. */ + can-gpio-sel-hog { + gpios =3D <4 GPIO_ACTIVE_HIGH>; + gpio-hog; + output-low; + }; + }; +}; + +&lpi2c4 { + clock-frequency =3D <400000>; + pinctrl-0 =3D <&pinctrl_lpi2c4>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ptn5110: tcpc@50 { + compatible =3D "nxp,ptn5110", "tcpci"; + reg =3D <0x50>; + interrupt-parent =3D <&gpio5>; + interrupts =3D <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&pinctrl_ptn5110>; + pinctrl-names =3D "default"; + + typec_con: connector { + compatible =3D "usb-c-connector"; + data-role =3D "dual"; + label =3D "USB-C"; + op-sink-microwatt =3D <0>; + power-role =3D "dual"; + self-powered; + sink-pdos =3D ; + source-pdos =3D ; + try-power-role =3D "sink"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + typec1_dr_sw: endpoint { + remote-endpoint =3D <&usb1_drd_sw>; + }; + }; + }; + }; + }; +}; + +&lpspi3 { + cs-gpios =3D <&gpio2 8 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pinctrl_lpspi3>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&lpuart1 { + /* console */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&lpuart5 { + /* BT */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart5>; + status =3D "okay"; + + bluetooth { + compatible =3D "nxp,88w8987-bt"; + }; +}; + +&micfil { + assigned-clocks =3D <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_PDM>; + assigned-clock-parents =3D <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates =3D <3932160000>, <3612672000>, + <393216000>, <361267200>, <49152000>; + pinctrl-0 =3D <&pinctrl_pdm>; + pinctrl-1 =3D <&pinctrl_pdm_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "okay"; +}; + +&sai5 { + assigned-clocks =3D <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_SAI5>; + assigned-clock-parents =3D <0>, <0>, <0>, <0>, <&scmi_clk IMX952_CLK_AUDI= OPLL1>; + assigned-clock-rates =3D <3932160000>, <3612672000>, <393216000>, <361267= 200>, <12288000>; + #sound-dai-cells =3D <0>; + pinctrl-0 =3D <&pinctrl_sai5>; + pinctrl-names =3D "default"; + fsl,sai-mclk-direction-output; + status =3D "okay"; +}; + +&scmi_iomuxc { + pinctrl_flexcan2: flexcan2grp { + fsl,pins =3D < + IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x39e + IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x39e + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins =3D < + IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_CAN3_TX 0x39e + IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_CAN3_RX 0x39e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins =3D < + IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins =3D < + IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x40000b9e + IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins =3D < + IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPIO2_IO_8 0x39e + IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPSPI3_SIN 0x39e + IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPSPI3_SOUT 0x39e + IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPSPI3_SCK 0x39e + >; + }; + + pinctrl_pcal6416: pcal6416grp { + fsl,pins =3D < + IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins =3D < + IMX952_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_0 0x31e + >; + }; + + pinctrl_pdm_sleep: pdmsleepgrp { + fsl,pins =3D < + IMX952_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_8 0x31e + IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_9 0x31e + >; + }; + + pinctrl_ptn5110: ptn5110grp { + fsl,pins =3D < + IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_GPIO5_IO_2 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins =3D < + IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins =3D < + IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x31e + IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x31e + IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x31e + IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x31e + >; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins =3D < + IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_TPM3_CH0 0x51e + IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e + >; + }; + + pinctrl_tpm4: tpm4grp { + fsl,pins =3D < + IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_TPM4_CH2 0x51e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins =3D < + IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x31e + IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x31e + IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x31e + IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x159e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x139e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x139e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x139e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x139e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x139e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x139e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x139e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x139e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x139e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x159e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_USDHC3_CLK 0x158e + IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_USDHC3_CMD 0x138e + IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_USDHC3_DATA0 0x138e + IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_USDHC3_DATA1 0x138e + IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_USDHC3_DATA2 0x138e + IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_USDHC3_CLK 0x158e + IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_USDHC3_CMD 0x138e + IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_USDHC3_DATA0 0x138e + IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_USDHC3_DATA1 0x138e + IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_USDHC3_DATA2 0x138e + IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_USDHC3_CLK 0x158e + IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_USDHC3_CMD 0x138e + IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_USDHC3_DATA0 0x138e + IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_USDHC3_DATA1 0x138e + IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_USDHC3_DATA2 0x138e + IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_USDHC3_DATA3 0x138e + >; + }; +}; + +&scmi_misc { + nxp,ctrl-ids =3D ; +}; + +&tpm3 { + pinctrl-0 =3D <&pinctrl_tpm3>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&tpm4 { + pinctrl-0 =3D <&pinctrl_tpm4>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&usb1 { + adp-disable; + disable-over-current; + dr_mode =3D "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust =3D <7>; + samsung,picophy-pre-emp-curr-control =3D <3>; + status =3D "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint =3D <&typec1_dr_sw>; + }; + }; +}; + +&usb2 { + disable-over-current; + dr_mode =3D "host"; + vbus-supply =3D <®_usb_vbus>; + status =3D "okay"; +}; + +&usdhc1 { + bus-width =3D <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + pinctrl-3 =3D <&pinctrl_usdhc1>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + status =3D "okay"; +}; + +&usdhc2 { + bus-width =3D <4>; + cd-gpios =3D <&gpio3 0 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply =3D <®_usdhc2_vmmc>; + fsl,cd-gpio-wakeup-disable; + status =3D "okay"; +}; + +&usdhc3 { + bus-width =3D <4>; + keep-power-in-suspend; + mmc-pwrseq =3D <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + pinctrl-3 =3D <&pinctrl_usdhc3>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply =3D <®_usdhc3_vmmc>; + wakeup-source; + status =3D "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status =3D "okay"; +}; --=20 2.34.1