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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-930b52dcd31sm810651485a.2.2026.07.20.00.56.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 00:56:19 -0700 (PDT) From: Yongxing Mou Date: Mon, 20 Jul 2026 15:56:08 +0800 Subject: [PATCH] drm/msm/dpu: Fix DMA SSPP REC block offsets on DPU v13 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260720-dpu-v13-dma-sspp-rec-fix-v1-1-10d69b4875e7@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAJfUXWoC/x2MSQqAMAwAvyI5G6gtuH1FPJQm1RzU0qAI4t8tH mdg5gHlLKwwVg9kvkTl2As0dQVh9fvCKFQYrLGt6axBSidejUPaPKqmhJkDRrnRDa73HUUXI0H JU+ai//U0v+8HWZaJK2oAAAA= X-Change-ID: 20260720-dpu-v13-dma-sspp-rec-fix-3938a7df3ffd To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784534173; l=3956; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=UIa+Xcp/itVmIeS+C8X4mGvcA9fV/ITHOdiF/RHRt5Q=; b=3aWsg+3stCwWnO78PjKfVT8bMaiyFogXBiDrsdNG16X9UwUDn0wfsB8rhajdXeTWOaiW+6OdN BGK7395fSz2C5GWYFMfduSnQ9qs5Vi2erF5bB6daVMqhpji636JObMv X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-ORIG-GUID: OzV-MMG2woQAi4jTsMfGlP533GG6m7jn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIwMDA4NiBTYWx0ZWRfX6VbvoJLhMcx8 G8y37pkQ/5V0VrGIm6rKiL0Yx00DPaluOSwDm1DIU0ArModrQRmNvZstMks/05q53O2er3lTLyW Pa9gZ3ERNFq40PZmeYDTUf4kR20EnoiZFkg1HUKtfIKrXEEpZtGw/RRA9K6K128JJkLl6Qh9e4Q hg44leSqsBwAfPX6Gt/LWWXroYYJ3Yxz2vNbFEaKGH6TkluNbwMDAV14KZz3hotQpzO7MUw4otc N/2aR8WNAGnYabajEEapo1vD1BWytLgDGacQH/ZxYZYFLnuxNGQ5NN83wuuCW6I+aWMeul1fvMN Y+qrposkAshaO9dRuXOEc1QS6+kJmKdKMD9ZuGDlmtpwP5HdHiSc1I4AaD0WLFxyQv2bpPsDJrQ CWf5IDNpi8DoV7KsJX1vaVW0fmGi0flUW36PvDnQ75SKYKwOfIQXeimyWdIPt5WGdaFlgXXre9w 3V6IOGQw7+BCV4uBgsA== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIwMDA4NiBTYWx0ZWRfX/snyecOoBUNK beMoA8eZXKFotVLcBh0h5jdygWLTy22S89r9zx97NVZ2tFoM4qZ8VyFZkesrg5rQ4+R0wf/jWRY PRt3vnFimVyfzYnd11zqi5sRzhmOTWI= X-Proofpoint-GUID: OzV-MMG2woQAi4jTsMfGlP533GG6m7jn X-Authority-Analysis: v=2.4 cv=bv58wkai c=1 sm=1 tr=0 ts=6a5dd4a5 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=OlMwNCVCb-L7xj7jIJUA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_01,2026-07-17_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 priorityscore=1501 spamscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607200086 On DPU v13, the DMA SSPP REC0 and REC1 blocks are located at offsets 0x1000 and 0x3000 from the SSPP common base. The existing DMA SSPP sub-block descriptor does not initialize sspp_rec0_blk and sspp_rec1_blk, causing REC register accesses to be performed at offset 0 instead of the corresponding REC block. As a result, DMA SSPP pipes are not programmed correctly and fail to produce output. Introduce a DPU v13 specific DMA SSPP descriptor with the correct REC block offsets and use it for all DMA SSPPs in the Kaanapali catalog. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h | 12 ++++++----= -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ++++++++++= ++ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h b/d= rivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h index 06da1583fb1e..85f455a9f29c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h @@ -86,42 +86,42 @@ static const struct dpu_sspp_cfg kaanapali_sspp[] =3D { .name =3D "sspp_8", .id =3D SSPP_DMA0, .base =3D 0x97000, .len =3D 0x84, .features =3D DMA_SDM845_MASK_SDMA, - .sblk =3D &dpu_dma_sblk, + .sblk =3D &dpu_dma_sblk_v13, .xin_id =3D 1, .type =3D SSPP_TYPE_DMA, }, { .name =3D "sspp_9", .id =3D SSPP_DMA1, .base =3D 0xa0000, .len =3D 0x84, .features =3D DMA_SDM845_MASK_SDMA, - .sblk =3D &dpu_dma_sblk, + .sblk =3D &dpu_dma_sblk_v13, .xin_id =3D 5, .type =3D SSPP_TYPE_DMA, }, { .name =3D "sspp_10", .id =3D SSPP_DMA2, .base =3D 0xa9000, .len =3D 0x84, .features =3D DMA_SDM845_MASK_SDMA, - .sblk =3D &dpu_dma_sblk, + .sblk =3D &dpu_dma_sblk_v13, .xin_id =3D 9, .type =3D SSPP_TYPE_DMA, }, { .name =3D "sspp_11", .id =3D SSPP_DMA3, .base =3D 0xb2000, .len =3D 0x84, .features =3D DMA_SDM845_MASK_SDMA, - .sblk =3D &dpu_dma_sblk, + .sblk =3D &dpu_dma_sblk_v13, .xin_id =3D 13, .type =3D SSPP_TYPE_DMA, }, { .name =3D "sspp_12", .id =3D SSPP_DMA4, .base =3D 0xbb000, .len =3D 0x84, .features =3D DMA_CURSOR_SDM845_MASK_SDMA, - .sblk =3D &dpu_dma_sblk, + .sblk =3D &dpu_dma_sblk_v13, .xin_id =3D 14, .type =3D SSPP_TYPE_DMA, }, { .name =3D "sspp_13", .id =3D SSPP_DMA5, .base =3D 0xc4000, .len =3D 0x84, .features =3D DMA_CURSOR_SDM845_MASK_SDMA, - .sblk =3D &dpu_dma_sblk, + .sblk =3D &dpu_dma_sblk_v13, .xin_id =3D 15, .type =3D SSPP_TYPE_DMA, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 2e10add84fd7..9a993cdfab85 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -303,6 +303,16 @@ static const u32 wb2_formats_rgb_yuv[] =3D { .num_formats =3D ARRAY_SIZE(plane_formats), \ } =20 +#define _DMA_SBLK_V13() \ + { \ + .sspp_rec0_blk =3D {.name =3D "sspp_rec0", \ + .base =3D 0x1000, .len =3D 0x180,}, \ + .sspp_rec1_blk =3D {.name =3D "sspp_rec1", \ + .base =3D 0x3000, .len =3D 0x180,}, \ + .format_list =3D plane_formats, \ + .num_formats =3D ARRAY_SIZE(plane_formats), \ + } + static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 =3D { .rot_maxheight =3D 1088, .rot_num_formats =3D ARRAY_SIZE(rotation_v2_formats), @@ -353,6 +363,8 @@ static const struct dpu_sspp_sub_blks dpu_rgb_sblk =3D = _RGB_SBLK(); =20 static const struct dpu_sspp_sub_blks dpu_dma_sblk =3D _DMA_SBLK(); =20 +static const struct dpu_sspp_sub_blks dpu_dma_sblk_v13 =3D _DMA_SBLK_V13(); + /************************************************************* * MIXER sub blocks config *************************************************************/ --- base-commit: bee763d5f341b99cf472afeb508d4988f62a6ca1 change-id: 20260720-dpu-v13-dma-sspp-rec-fix-3938a7df3ffd Best regards, --=20 Yongxing Mou