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Sun, 19 Jul 2026 14:13:44 -0700 (PDT) From: =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Brian Masney , Andre Przywara , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= Subject: [PATCH v1 1/4] clk: sunxi-ng: add cycle-masking divider (maskdiv) clock type Date: Sun, 19 Jul 2026 23:13:16 +0200 Message-ID: <20260719211319.982285-2-juanmanuellopezcarrillo@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> References: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Some mod clocks do not divide their parent with a linear M+1 divider: the M factor masks (swallows) M pulses out of every 2^width parent cycles, so the average output rate is rate =3D parent * (2^width - M) / 2^width and the surviving pulses keep the parent period. The A523/T527 GPU clock (GPU_CLK_REG, 0x670) is such a divider: "FACTOR_M: mask M cycles at 16 cycles", GPU_CLK =3D Clock Source * ((16-M)/16) (T527 user manual v0.92, section 2.7.6.58). Modelling these registers with the linear ccu_div type programs a faster clock than requested for every M > 0 (e.g. M=3D1 on a 800 MHz parent yields 750 MHz, not 400 MHz). Add a small ccu type implementing the masking semantics. Because the masked output is not an even pulse train, determine_rate prefers, among the parents that reach the requested rate, the one needing the least masking. set_rate_and_parent follows the same ordering rule as clk_composite_set_rate_and_parent() so no intermediate configuration overshoots both the old and the new rate. Signed-off-by: Juan Manuel L=C3=B3pez Carrillo --- drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu_maskdiv.c | 199 +++++++++++++++++++++++++++++ drivers/clk/sunxi-ng/ccu_maskdiv.h | 71 ++++++++++ 3 files changed, 271 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu_maskdiv.c create mode 100644 drivers/clk/sunxi-ng/ccu_maskdiv.h diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index a1c4087d7..26313083c 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -10,6 +10,7 @@ sunxi-ccu-y +=3D ccu_reset.o # Base clock types sunxi-ccu-y +=3D ccu_div.o sunxi-ccu-y +=3D ccu_frac.o +sunxi-ccu-y +=3D ccu_maskdiv.o sunxi-ccu-y +=3D ccu_gate.o sunxi-ccu-y +=3D ccu_mux.o sunxi-ccu-y +=3D ccu_mult.o diff --git a/drivers/clk/sunxi-ng/ccu_maskdiv.c b/drivers/clk/sunxi-ng/ccu_= maskdiv.c new file mode 100644 index 000000000..2d3cccf08 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_maskdiv.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2026 Juan Manuel L=C3=B3pez Carrillo + * + * Cycle-masking divider: the M factor masks M pulses out of every + * 2^width parent cycles instead of dividing the parent rate, so + * + * rate =3D parent * (2^width - M) / 2^width + * + * The masked output is not an even pulse train: the surviving pulses + * keep the parent period. Rate selection therefore prefers, among the + * parents that reach the requested rate, the one needing the least + * masking. + */ + +#include +#include +#include + +#include "ccu_gate.h" +#include "ccu_maskdiv.h" + +static unsigned long ccu_maskdiv_calc_rate(unsigned long parent_rate, + unsigned int m, unsigned int width) +{ + unsigned int n =3D 1 << width; + + return div_u64((u64)parent_rate * (n - m), n); +} + +/* + * Smallest M (least masking) whose output does not exceed the requested + * rate; masking everything (M =3D=3D 2^width) is never returned. + */ +static unsigned int ccu_maskdiv_find_m(unsigned long parent_rate, + unsigned long rate, unsigned int width) +{ + unsigned int n =3D 1 << width; + u64 kept; + + if (!parent_rate || rate >=3D parent_rate) + return 0; + + kept =3D div64_ul((u64)rate * n, parent_rate); + if (!kept) + kept =3D 1; + + return n - (unsigned int)kept; +} + +static void ccu_maskdiv_disable(struct clk_hw *hw) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + + return ccu_gate_helper_disable(&cmd->common, cmd->enable); +} + +static int ccu_maskdiv_enable(struct clk_hw *hw) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + + return ccu_gate_helper_enable(&cmd->common, cmd->enable); +} + +static int ccu_maskdiv_is_enabled(struct clk_hw *hw) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + + return ccu_gate_helper_is_enabled(&cmd->common, cmd->enable); +} + +static unsigned long ccu_maskdiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + unsigned int m; + u32 reg; + + reg =3D readl(cmd->common.base + cmd->common.reg); + m =3D (reg >> cmd->shift) & ((1 << cmd->width) - 1); + + return ccu_maskdiv_calc_rate(parent_rate, m, cmd->width); +} + +static int ccu_maskdiv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + unsigned long best_rate =3D 0, best_parent_rate =3D 0; + struct clk_hw *best_parent =3D NULL; + unsigned int best_m =3D UINT_MAX; + unsigned int i; + + for (i =3D 0; i < clk_hw_get_num_parents(hw); i++) { + struct clk_hw *parent =3D clk_hw_get_parent_by_index(hw, i); + unsigned long parent_rate, new_rate; + unsigned int m; + + if (!parent) + continue; + + parent_rate =3D clk_hw_get_rate(parent); + m =3D ccu_maskdiv_find_m(parent_rate, req->rate, cmd->width); + new_rate =3D ccu_maskdiv_calc_rate(parent_rate, m, cmd->width); + + if (new_rate > req->rate) + continue; + + /* Closest rate first; on ties, the least masking */ + if (new_rate > best_rate || + (new_rate =3D=3D best_rate && m < best_m)) { + best_rate =3D new_rate; + best_parent_rate =3D parent_rate; + best_parent =3D parent; + best_m =3D m; + } + } + + if (!best_parent) + return -EINVAL; + + req->best_parent_hw =3D best_parent; + req->best_parent_rate =3D best_parent_rate; + req->rate =3D best_rate; + + return 0; +} + +static int ccu_maskdiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + unsigned int m; + unsigned long flags; + u32 reg; + + m =3D ccu_maskdiv_find_m(parent_rate, rate, cmd->width); + + spin_lock_irqsave(cmd->common.lock, flags); + + reg =3D readl(cmd->common.base + cmd->common.reg); + reg &=3D ~GENMASK(cmd->shift + cmd->width - 1, cmd->shift); + writel(reg | (m << cmd->shift), cmd->common.base + cmd->common.reg); + + spin_unlock_irqrestore(cmd->common.lock, flags); + + return 0; +} + +static u8 ccu_maskdiv_get_parent(struct clk_hw *hw) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + + return ccu_mux_helper_get_parent(&cmd->common, &cmd->mux); +} + +static int ccu_maskdiv_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_maskdiv *cmd =3D hw_to_ccu_maskdiv(hw); + + return ccu_mux_helper_set_parent(&cmd->common, &cmd->mux, index); +} + +static int ccu_maskdiv_set_rate_and_parent(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate, u8 index) +{ + /* + * Same ordering rule as clk_composite_set_rate_and_parent(): if + * switching the mux with the current M would overshoot the + * requested rate, program the divider first, so the + * intermediate rate never exceeds both the old and the new + * rate. + */ + if (ccu_maskdiv_recalc_rate(hw, parent_rate) > rate) { + ccu_maskdiv_set_rate(hw, rate, parent_rate); + ccu_maskdiv_set_parent(hw, index); + } else { + ccu_maskdiv_set_parent(hw, index); + ccu_maskdiv_set_rate(hw, rate, parent_rate); + } + + return 0; +} + +const struct clk_ops ccu_maskdiv_ops =3D { + .disable =3D ccu_maskdiv_disable, + .enable =3D ccu_maskdiv_enable, + .is_enabled =3D ccu_maskdiv_is_enabled, + + .get_parent =3D ccu_maskdiv_get_parent, + .set_parent =3D ccu_maskdiv_set_parent, + + .determine_rate =3D ccu_maskdiv_determine_rate, + .recalc_rate =3D ccu_maskdiv_recalc_rate, + .set_rate =3D ccu_maskdiv_set_rate, + .set_rate_and_parent =3D ccu_maskdiv_set_rate_and_parent, +}; +EXPORT_SYMBOL_NS_GPL(ccu_maskdiv_ops, "SUNXI_CCU"); diff --git a/drivers/clk/sunxi-ng/ccu_maskdiv.h b/drivers/clk/sunxi-ng/ccu_= maskdiv.h new file mode 100644 index 000000000..3cbfce064 --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu_maskdiv.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026 Juan Manuel L=C3=B3pez Carrillo + */ + +#ifndef _CCU_MASKDIV_H_ +#define _CCU_MASKDIV_H_ + +#include + +#include "ccu_common.h" +#include "ccu_mux.h" + +/* + * struct ccu_maskdiv - cycle-masking ("fractional") divider + * + * This divider does not divide the parent clock: it masks (swallows) M + * pulses out of every 2^width parent cycles, so the average output rate + * is + * + * rate =3D parent * (2^width - M) / 2^width + * + * with the remaining pulses keeping the parent period. The A523/T527 + * GPU clock (GPU_CLK_REG, 0x670) is such a divider: "FACTOR_M: mask M + * cycles at 16 cycles", GPU_CLK =3D Clock Source * ((16-M)/16) (T527 user + * manual v0.92, section 2.7.6.58). + * + * @shift: shift of the M field in the register + * @width: width of the M field; the mask window is 2^width cycles + */ +struct ccu_maskdiv { + u32 enable; + + u8 shift; + u8 width; + + struct ccu_mux_internal mux; + struct ccu_common common; +}; + +#define SUNXI_CCU_MASKDIV_HW_WITH_MUX_TABLE_GATE(_struct, _name, \ + _parents, _table, \ + _reg, \ + _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags) \ + struct ccu_maskdiv _struct =3D { \ + .enable =3D _gate, \ + .shift =3D _mshift, \ + .width =3D _mwidth, \ + .mux =3D _SUNXI_CCU_MUX_TABLE(_muxshift, _muxwidth, \ + _table), \ + .common =3D { \ + .reg =3D _reg, \ + .hw.init =3D CLK_HW_INIT_PARENTS_HW(_name, \ + _parents, \ + &ccu_maskdiv_ops, \ + _flags), \ + }, \ + } + +static inline struct ccu_maskdiv *hw_to_ccu_maskdiv(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_maskdiv, common); +} + +extern const struct clk_ops ccu_maskdiv_ops; + +#endif /* _CCU_MASKDIV_H_ */ --=20 2.47.3 From nobody Sat Jul 25 03:20:30 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 794F9312825 for ; Sun, 19 Jul 2026 21:13:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784495631; cv=none; b=s97b4+COGu6P/a2fpU14dBhcgBdtvdwEnySifEdz9T7XweVhnMwx9bgpTptYKIx9h5GyiTwtqzI26igG7oHfPwlt1XFx2+rDncNrDVtTOUu+l+YhEx0Se2jefkZRPf2OWp5nN2rT+xhcLIO77UB+02HAzm3S0hwuibgOUWQzr50= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784495631; c=relaxed/simple; bh=OIQ9wV1fytaPWVFvAnMGv/HqNSfH3VqUaIN7P0RyrC8=; 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Sun, 19 Jul 2026 14:13:47 -0700 (PDT) Received: from localhost.localdomain ([2a0d:3344:2841:7708:a101:2b8a:f76:a00f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49549a3e2a9sm224108815e9.4.2026.07.19.14.13.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jul 2026 14:13:46 -0700 (PDT) From: =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Brian Masney , Andre Przywara , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= Subject: [PATCH v1 2/4] clk: sunxi-ng: sun55i-a523: GPU clock divider is fractional, not linear Date: Sun, 19 Jul 2026 23:13:17 +0200 Message-ID: <20260719211319.982285-3-juanmanuellopezcarrillo@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> References: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The GPU mod clock (0x670) was modelled as a linear M+1 divider, but the M factor of this register is a cycle-masking divider: GPU_CLK =3D Clock Source * ((16-M)/16) (T527 user manual v0.92, section 2.7.6.58). With the linear model every OPP that needed M > 0 silently ran the GPU faster than requested. Measured on an Orange Pi 4A (T527) with the Mali cycle counter against the programmed register: OPP request programmed real rate 150 MHz 600M, M=3D3 487.5 MHz 200 MHz 800M, M=3D3 650 MHz 300 MHz 600M, M=3D1 562.5 MHz 400 MHz 800M, M=3D1 750 MHz 600 MHz 600M, M=3D0 600 MHz i.e. the "400 MHz" OPP ran the GPU at 750 MHz, 25% above the vendor ceiling of 600 MHz, at the low-OPP voltage. Thermal throttling to "400 MHz" actually overclocked the GPU. Switch the clock to the maskdiv type. With least-masking preference the vendor OPP set now resolves to 600/400/300/200 MHz taken undivided from their periph outputs and 150 MHz =3D pll-periph0-200M * 12/16, all verified exact on hardware with the same cycle-counter method. Drop pll-periph0-800M from the selectable parents (the mux table skips hardware index 1): the vendor BSP removed it from its parent list with the comment "If GPU use pll-peri0-800m, gpu will occur job fault", and with the masking semantics every vendor OPP matches exactly from the 800M parent first, so it would otherwise always be chosen. Also drop CLK_SET_RATE_PARENT: every OPP is reachable from the fixed pll-periph0 outputs, and pll-gpu must never be reprogrammed through this mux. Once the GPU moves off pll-gpu the PLL is no longer prepared, so it loses the rate protection of CLK_SET_RATE_GATE; a propagated rate request would then reprogram the PLL while its gate is off (the lock bit never asserts, 70 ms poll timeout per transition) and switch the running GPU onto it before it locks. Fixes: 6702d17f54a8 ("clk: sunxi-ng: a523: add video mod clocks") Signed-off-by: Juan Manuel L=C3=B3pez Carrillo --- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 32 +++++++++++++++++++++----- 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/= ccu-sun55i-a523.c index 20dad06b3..979e53e63 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c @@ -21,6 +21,7 @@ =20 #include "ccu_div.h" #include "ccu_gate.h" +#include "ccu_maskdiv.h" #include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_nk.h" @@ -442,18 +443,37 @@ static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb= _hws, 0x63c, BIT(0), 0); =20 static const struct clk_hw *gpu_parents[] =3D { &pll_gpu_clk.common.hw, - &pll_periph0_800M_clk.common.hw, &pll_periph0_600M_clk.hw, &pll_periph0_400M_clk.hw, &pll_periph0_300M_clk.hw, &pll_periph0_200M_clk.hw, }; =20 -static SUNXI_CCU_M_HW_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, - 0, 4, /* M */ - 24, 3, /* mux */ - BIT(31), /* gate */ - CLK_SET_RATE_PARENT); +/* + * Mux index 1 (pll-periph0-800M) is skipped: the vendor BSP removed it + * from the parent list ("If GPU use pll-peri0-800m, gpu will occur job + * fault"), and with the masking divider every OPP would match exactly + * from it first. + */ +static const u8 gpu_mux_table[] =3D { 0, 2, 3, 4, 5 }; + +/* + * The M factor is a cycle-masking (fractional) divider, not a linear + * one: rate =3D source * (16 - M) / 16 (T527 manual, GPU_CLK_REG). + * + * No CLK_SET_RATE_PARENT: every GPU OPP is reachable from the fixed + * pll-periph0 outputs, and pll-gpu must never be reprogrammed through thi= s mux. + * Once the GPU moves off pll-gpu the PLL is no longer prepared, so it los= es + * the rate protection of CLK_SET_RATE_GATE; a propagated rate request wou= ld + * then reprogram the PLL while its gate is off (the lock bit never assert= s, + * 70 ms timeout) and switch the running GPU onto it before it locks. + */ +static SUNXI_CCU_MASKDIV_HW_WITH_MUX_TABLE_GATE(gpu_clk, "gpu", gpu_parent= s, + gpu_mux_table, 0x670, + 0, 4, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); =20 static SUNXI_CCU_GATE_HWS(bus_gpu_clk, "bus-gpu", ahb_hws, 0x67c, BIT(0), = 0); =20 --=20 2.47.3 From nobody Sat Jul 25 03:20:30 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30FA030EF9B for ; Sun, 19 Jul 2026 21:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784495635; cv=none; b=P6S3ciWx6CxmhceJbgv7LnuVR1SMWA9HAasWwrcVABGUxfTWmnPmu9kxsnY03x1Itobk5jI31P6d84DBZ9sIZjj2ahz5VvXkq4LxcRvTO3cy0OmXLQDKohVoKGIQgFgr5BIqj+16rd1LKVJmVifFvJVX81P8VvZPnks02zjjKP0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784495635; c=relaxed/simple; bh=DDsOXp+Z72kK9qdiLJoanRdwCGRm/6FA5U02/PGt8IU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Sun, 19 Jul 2026 14:13:48 -0700 (PDT) From: =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Brian Masney , Andre Przywara , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= Subject: [PATCH v1 3/4] clk: sunxi-ng: sun55i-a523: reparent GPU while pll-gpu changes rate Date: Sun, 19 Jul 2026 23:13:18 +0200 Message-ID: <20260719211319.982285-4-juanmanuellopezcarrillo@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> References: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Register the existing sunxi-ng mux notifier on pll-gpu so the GPU mod clock is parked on the fixed pll-periph0-600M output while the PLL is being reprogrammed, and switched back once it has locked, following the cpux precedent of other sunxi SoCs. The mux switch is glitch-free per the T527 manual (GPU_CLK_REG, "The clock selection supports glitch-free switch"). Nothing retunes pll-gpu at runtime today (the mux does not propagate rate requests and all standard OPPs resolve to pll-periph0 outputs), but the higher speed-bin operating points (648-792 MHz) will need pll-gpu as a live parent, and any direct clk_set_rate() on the PLL is now safe. Signed-off-by: Juan Manuel L=C3=B3pez Carrillo --- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/= ccu-sun55i-a523.c index 979e53e63..4341eb66c 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c @@ -1667,6 +1667,17 @@ static const u32 pll_regs[] =3D { SUN55I_A523_PLL_NPU_REG, }; =20 +/* + * Park the GPU on the fixed pll-periph0-600M output while pll-gpu + * changes rate; the mux switch is glitch-free (T527 manual, GPU_CLK_REG). + */ +static struct ccu_mux_nb sun55i_a523_gpu_nb =3D { + .common =3D &gpu_clk.common, + .cm =3D &gpu_clk.mux, + .delay_us =3D 1, + .bypass_index =3D 1, /* pll-periph0-600M */ +}; + static int sun55i_a523_ccu_probe(struct platform_device *pdev) { void __iomem *reg; @@ -1698,6 +1709,10 @@ static int sun55i_a523_ccu_probe(struct platform_dev= ice *pdev) if (ret) return ret; =20 + /* Reparent the GPU during pll-gpu rate changes */ + ccu_mux_notifier_register(pll_gpu_clk.common.hw.clk, + &sun55i_a523_gpu_nb); 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Sun, 19 Jul 2026 14:13:51 -0700 (PDT) From: =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Brian Masney , Andre Przywara , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= Subject: [PATCH v1 4/4] arm64: dts: allwinner: t527-orangepi-4a: add GPU OPP table Date: Sun, 19 Jul 2026 23:13:19 +0200 Message-ID: <20260719211319.982285-5-juanmanuellopezcarrillo@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> References: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add the Mali-G57 operating points from the vendor BSP universal table (150/200/300/400/600 MHz) so panfrost devfreq can scale the GPU instead of running at the boot clock. All operating points use 920 mV: the BSP table specifies 900 mV for every universal OPP, but on this board the GPU rail (AXP717 DCDC2, vdd-gpu-sys) is a fixed 920 mV supply, so the OPP voltage states the actual rail value and voltage transitions are no-ops. The higher speed-bin points of the BSP (648-792 MHz) are not included: they are gated by a SID efuse bin and need pll-gpu as a live parent. Depends on the sun55i-a523 GPU clock divider fix (the OPP rates are only produced correctly with the cycle-masking divider model); validated on hardware with the Mali cycle counter: 149/199/300/399/597 MHz measured under load, thermal-emulation throttling included. Signed-off-by: Juan Manuel L=C3=B3pez Carrillo --- .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 055be86e5..0fd73a1bb 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -30,6 +30,35 @@ ext_osc32k: ext-osc32k-clk { clock-output-names =3D "ext_osc32k"; }; =20 + gpu_opp_table: opp-table-gpu { + compatible =3D "operating-points-v2"; + + opp-150000000 { + opp-hz =3D /bits/ 64 <150000000>; + opp-microvolt =3D <920000>; + }; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + opp-microvolt =3D <920000>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + opp-microvolt =3D <920000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + opp-microvolt =3D <920000>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <920000>; + }; + }; + leds { compatible =3D "gpio-leds"; =20 @@ -116,6 +145,7 @@ &gmac1 { =20 &gpu { mali-supply =3D <®_dcdc2>; + operating-points-v2 =3D <&gpu_opp_table>; status =3D "okay"; }; =20 --=20 2.47.3