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Sun, 19 Jul 2026 02:34:17 -0700 (PDT) From: Pengyu Luo To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: inux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, guf296@126.com, Pengyu Luo Subject: [PATCH 1/2] dt-bindings: arm: qcom: Document Lenovo Legion Y700 Gen4 Date: Sun, 19 Jul 2026 17:32:25 +0800 Message-ID: <20260719093226.197740-2-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260719093226.197740-1-mitltlatltl@gmail.com> References: <20260719093226.197740-1-mitltlatltl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible for the SM8750-based Lenovo Legion Y700 Gen4, using its codename, elden. Signed-off-by: Pengyu Luo Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index c7c9a9279684..e1ade271e712 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1160,6 +1160,7 @@ properties: =20 - items: - enum: + - lenovo,elden - qcom,sm8750-mtp - qcom,sm8750-qrd - const: qcom,sm8750 --=20 2.54.0 From nobody Sat Jul 25 03:46:06 2026 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17D5E1A9F97 for ; Sun, 19 Jul 2026 09:34:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.182 ARC-Seal: i=1; a=rsa-sha256; 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Sun, 19 Jul 2026 02:34:22 -0700 (PDT) Received: from nuvole ([2408:8456:3214:35e7:8e03:79a6:7390:9fc3]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84c2adcaa0bsm4022342b3a.20.2026.07.19.02.34.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jul 2026 02:34:21 -0700 (PDT) From: Pengyu Luo To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: inux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, guf296@126.com, Pengyu Luo Subject: [PATCH 2/2] arm64: dts: qcom: sm8750: Add Lenovo Legion Y700 Gen4 Date: Sun, 19 Jul 2026 17:32:26 +0800 Message-ID: <20260719093226.197740-3-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260719093226.197740-1-mitltlatltl@gmail.com> References: <20260719093226.197740-1-mitltlatltl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add an initial devicetree for the Lenovo Legion Y700 Gen4, which is based on sm8750-qrd. Supported features: - Altmode - Backlight - Battery & Charge (Full speed) - Buttons - Framebuffer (Require mdss and dispcc to be disabled) - USB (Two ports) Downstream supported features: - Display (8/10 bits) (Pending [1]) - GPU - Touchscreen Unsupported features: - BT & WIFI - Cameras & Flash - Microphones & Speakers (Downstream available, pending test [2]) - Sensors (Downstream available, pending test [3]) - Vibrators (Downstream available, pending test [2]) [1]: https://lore.kernel.org/dri-devel/20260709142846.12463-1-mitltlatltl@g= mail.com [2]: https://github.com/GUF296/linux/commits/codex/tb321fu-full-remediation= -20260715 [3]: https://github.com/linux-msm/hexagonrpc Signed-off-by: Pengyu Luo --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm8750-lenovo-elden.dts | 1097 +++++++++++++++++ 2 files changed, 1098 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8750-lenovo-elden.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index e05414290d8e..cb93708e0415 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -405,6 +405,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-hdk-rear-camera-car= d.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8650-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sm8750-lenovo-elden.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm8750-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D talos-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8750-lenovo-elden.dts b/arch/arm64/= boot/dts/qcom/sm8750-lenovo-elden.dts new file mode 100644 index 000000000000..c67c00ea45a0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8750-lenovo-elden.dts @@ -0,0 +1,1096 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025-2026 Pengyu Luo + */ + +/dts-v1/; + +#include +#include +#include +#include "sm8750.dtsi" +#include "pm8550.dtsi" +#define PMK8550VE_SID 8 +#include "pm8550ve.dtsi" +#include "pmih0108.dtsi" +#include "pmk8550.dtsi" +#include "sm8750-pmics.dtsi" + +/ { + model =3D "Lenovo Legion Y700 Gen4"; + compatible =3D "lenovo,elden", "qcom,sm8750"; + chassis-type =3D "tablet"; + + aliases { + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + i2c9 =3D &i2c9; + i2c10 =3D &i2c10; + serial1 =3D &uart14; + }; + + /* mandatory, ABL requires the chosen node to boot */ + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + framebuffer: framebuffer@fc800000 { + compatible =3D "simple-framebuffer"; + reg =3D <0x0 0xfc800000 0x0 0x2b00000>; + width =3D <1904>; + height =3D <3040>; + stride =3D <(1904 * 4)>; + format =3D "a8r8g8b8"; + }; + }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <76800000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32000>; + #clock-cells =3D <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible =3D "fixed-factor-clock"; + #clock-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult =3D <1>; + clock-div =3D <2>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&volume_up_n>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + linux,code =3D ; + gpios =3D <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval =3D <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible =3D "qcom,sm8750-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + orientation-gpios =3D <&tlmm 61 GPIO_ACTIVE_HIGH>; + + /* Long edge */ + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint =3D <&fsa4480_sbu_mux>; + }; + }; + }; + }; + + /* Short edge */ + connector@1 { + compatible =3D "usb-c-connector"; + reg =3D <1>; + + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_c2_in: endpoint { + remote-endpoint =3D <&usb_dwc3_hs2>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_hs_sbu: endpoint { + remote-endpoint =3D <&fsa4480_hs_sbu_mux>; + }; + }; + }; + }; + }; + + reserved-memory { + /* + * Use this to tell the BL to initialize the display related + * resources, so we can use efifb. Please 's/-/_/' + */ + splash-region { + reg =3D <0 0xfc800000 0 0x2b00000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_iovdd_1p8: regulator-dsi-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vreg_iovdd_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 161 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&iovdd_reg_en>; + pinctrl-names =3D "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_vsp_6p1: regulator-vsp-6p1 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vreg_vsp_6p1"; + regulator-min-microvolt =3D <6100000>; + regulator-max-microvolt =3D <6100000>; + + gpio =3D <&tlmm 72 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&vsp_reg_en>; + pinctrl-names =3D "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_vsn_5p8: regulator-vsn-5p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vreg_vsn_5p8"; + regulator-min-microvolt =3D <5800000>; + regulator-max-microvolt =3D <5800000>; + + gpio =3D <&tlmm 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&vsn_reg_en>; + pinctrl-names =3D "default"; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l1-l4-l10-supply =3D <&vreg_s3g_1p8>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l3-supply =3D <&vreg_s7i_1p2>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob1>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l11-supply =3D <&vreg_s7i_1p2>; + vdd-l12-supply =3D <&vreg_s3g_1p8>; + vdd-l15-supply =3D <&vreg_s3g_1p8>; + vdd-l17-supply =3D <&vreg_bob2>; + + qcom,pmic-id =3D "b"; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <4000000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2704000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name =3D "vreg_l1b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3048000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name =3D "vreg_l4b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name =3D "vreg_l5b_3p1"; + regulator-min-microvolt =3D <3100000>; + regulator-max-microvolt =3D <3148000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name =3D "vreg_l7b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name =3D "vreg_l8b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name =3D "vreg_l10b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name =3D "vreg_l14b_3p2"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name =3D "vreg_l16b_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s7i_1p2>; + vdd-l2-supply =3D <&vreg_s1d_0p97>; + vdd-l3-supply =3D <&vreg_s1d_0p97>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "d"; + + vreg_s1d_0p97: smps1 { + regulator-name =3D "vreg_s1d_0p97"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_s3d_1p2: smps3 { + regulator-name =3D "vreg_s3d_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1300000>; + regulator-initial-mode =3D ; + }; + + vreg_s4d_0p85: smps4 { + regulator-name =3D "vreg_s4d_0p85"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1036000>; + regulator-initial-mode =3D ; + }; + + vreg_l1d_1p2: ldo1 { + regulator-name =3D "vreg_l1d_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2d_0p88: ldo2 { + regulator-name =3D "vreg_l2d_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3d_0p88: ldo3 { + regulator-name =3D "vreg_l3d_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s1d_0p97>; + vdd-l2-supply =3D <&vreg_s7i_1p2>; + vdd-l3-supply =3D <&vreg_s3g_1p8>; + vdd-s5-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "f"; + + vreg_s5f_0p5: smps5 { + regulator-name =3D "vreg_s5f_0p5"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_0p88: ldo1 { + regulator-name =3D "vreg_l1f_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2f_1p2: ldo2 { + regulator-name =3D "vreg_l2f_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3f_1p8: ldo3 { + regulator-name =3D "vreg_l3f_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + }; + + regulators-3 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s1d_0p97>; + vdd-l2-supply =3D <&vreg_s3g_1p8>; + vdd-l3-supply =3D <&vreg_s7i_1p2>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "g"; + + vreg_s1g_0p5: smps1 { + regulator-name =3D "vreg_s1g_0p5"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <700000>; + regulator-initial-mode =3D ; + }; + + vreg_s3g_1p8: smps3 { + regulator-name =3D "vreg_s3g_1p8"; + regulator-min-microvolt =3D <1856000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s4g_0p75: smps4 { + regulator-name =3D "vreg_s4g_0p75"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <900000>; + regulator-initial-mode =3D ; + }; + + vreg_l1g_0p91: ldo1 { + regulator-name =3D "vreg_l1g_0p91"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <936000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2g_1p8: ldo2 { + regulator-name =3D "vreg_l2g_1p8"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1860000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name =3D "vreg_l3g_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1256000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s7i_1p2>; + vdd-l2-supply =3D <&vreg_s7i_1p2>; + vdd-l3-supply =3D <&vreg_s1d_0p97>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "i"; + + vreg_s7i_1p2: smps7 { + regulator-name =3D "vreg_s7i_1p2"; + regulator-min-microvolt =3D <1224000>; + regulator-max-microvolt =3D <1340000>; + regulator-initial-mode =3D ; + }; + + vreg_s8i_0p9: smps8 { + regulator-name =3D "vreg_s8i_0p9"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <972000>; + regulator-initial-mode =3D ; + }; + + vreg_l1i_1p2: ldo1 { + regulator-name =3D "vreg_l1i_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name =3D "vreg_l2i_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l3i_0p88: ldo3 { + regulator-name =3D "vreg_l3i_0p88"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-5 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s1d_0p97>; + vdd-l2-supply =3D <&vreg_s7i_1p2>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "j"; + + vreg_s2j_1p1: smps2 { + regulator-name =3D "vreg_s2j_1p1"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_s3j_1p1: smps3 { + regulator-name =3D "vreg_s3j_1p1"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_l1j_0p91: ldo1 { + regulator-name =3D "vreg_l1j_0p91"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name =3D "vreg_l2j_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&gpi_dma2 { + status =3D "okay"; +}; + +&i2c5 { + status =3D "okay"; + + typec-mux@42 { + compatible =3D "fcs,fsa4480"; + reg =3D <0x42>; + + vcc-supply =3D <&vreg_bob1>; + + mode-switch; + orientation-switch; + + port { + fsa4480_hs_sbu_mux: endpoint { + remote-endpoint =3D <&pmic_glink_hs_sbu>; + }; + }; + }; + + typec-mux@43 { + compatible =3D "fcs,fsa4480"; + reg =3D <0x43>; + + vcc-supply =3D <&vreg_bob1>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint =3D <&pmic_glink_sbu>; + }; + }; + }; + + eusb_repeater: redriver@4f { + compatible =3D "nxp,ptn3222"; /* PTN3222DUK */ + reg =3D <0x4f>; + #phy-cells =3D <0>; + + vdd3v3-supply =3D <&vreg_l5b_3p1>; + vdd1v8-supply =3D <&vreg_l15b_1p8>; + + reset-gpios =3D <&pm8550ve_gpios 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&eusb_reset_n>, <&eusb_mux_default>; + pinctrl-names =3D "default"; + }; +}; + +&i2c6 { + status =3D "okay"; + + /* haptic_hv_l@5a haptic_hv_r@5b */ +}; + +&i2c9 { + status =3D "okay"; + + /* aw882xx_smartpa@34 @37 */ +}; + +&i2c10 { + status =3D "okay"; + + /* i2c_wl2868c@2F */ + + /* + * bias@3e, as9702 or aw37504 + * + * gpio72/gpio73: enable pin for OUTP/OUTN + * In practical, register programming is not required for as9702 + * + * as9702: (REG02H[7:0]=3D0xf1) + * reg: 0x00 0x01 0x03 + * val: 0x15 0x12 0x73 + * + * aw37504: (REG04H[1:0]=3D0x01) + * reg: 0x00 0x01 0x03 0x04 + * val: 0x15 0x12 0x43 0x09 + */ + + backlight: backlight@76 { + compatible =3D "awinic,aw99706"; + reg =3D <0x76>; + + enable-gpio =3D <&tlmm 88 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&aw99706_bl_active>; + pinctrl-names =3D "default"; + + default-brightness =3D <511>; + max-brightness =3D <4095>; + + awinic,dim-mode =3D <1>; + awinic,sw-freq-hz =3D <750000>; + awinic,sw-ilmt-microamp =3D <3000000>; + awinic,uvlo-thres-microvolt =3D <2200000>; + awinic,iled-max-microamp =3D <30000>; + awinic,ramp-ctl =3D <3>; + }; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + remote-endpoint =3D <&usb_dp_qmpphy_dp_in>; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l3g_1p2>; + + qcom,dual-dsi-mode; + qcom,sync-dual-dsi; + qcom,master-dsi; + + status =3D "okay"; + + /* panel: csot,pp8807hb1-1 */ +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l3i_0p88>; + phy-type =3D ; + + status =3D "okay"; +}; + +&mdss_dsi1 { + /* Bonded DSI, source to dsi0_phy PLL */ + clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC1_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + + vdda-supply =3D <&vreg_l3g_1p2>; + + qcom,dual-dsi-mode; + qcom,sync-dual-dsi; + + status =3D "okay"; +}; + +&mdss_dsi1_phy { + vdds-supply =3D <&vreg_l3i_0p88>; + phy-type =3D ; + + status =3D "okay"; +}; + +&pcie0 { + vdda-supply =3D <&vreg_l1f_0p88>; + vddpe-3v3-supply =3D <&vreg_l3g_1p2>; + + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l1f_0p88>; + vdda-pll-supply =3D <&vreg_l3g_1p2>; + + status =3D "okay"; +}; + +&pcieport0 { + wake-gpios =3D <&tlmm 104 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&tlmm 102 GPIO_ACTIVE_LOW>; + + /* WCN7861, id: pci17cb,110e */ +}; + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins =3D "gpio6"; + function =3D "normal"; + bias-pull-up; + input-enable; + power-source =3D <1>; + }; +}; + +&pm8550ve_gpios { + eusb_reset_n: eusb-reset-n-state { + pins =3D "gpio6"; + function =3D "normal"; + bias-disable; + power-source =3D <1>; + qcom,drive-strength =3D <2>; + }; +}; + +&pmih0108_eusb2_repeater { + vdd18-supply =3D <&vreg_l15b_1p8>; + vdd3-supply =3D <&vreg_l5b_3p1>; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&qupv3_1 { + status =3D "okay"; +}; + +&qupv3_2 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/sm8750/LENOVO/elden/adsp.mbn", + "qcom/sm8750/LENOVO/elden/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/sm8750/LENOVO/elden/cdsp.mbn", + "qcom/sm8750/LENOVO/elden/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + +&spi4 { + status =3D "okay"; + + /* novatek@0 */ +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 55 GPIO_ACTIVE_HIGH>; + + vmmc-supply =3D <&vreg_l9b_2p9>; + vqmmc-supply =3D <&vreg_l8b_1p8>; + + no-sdio; + no-mmc; + + pinctrl-0 =3D <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 =3D <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&tlmm { + /* For CDT: <32 3> <37 2> <77 1>; */ + /* reserved for secure world */ + gpio-reserved-ranges =3D <39 1>, <74 1>; + + aw99706_bl_active: aw99706-bl-active-state { + pins =3D "gpio88"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + eusb_mux_default: eusb-mux-default-state { + pins =3D "gpio29"; + function =3D "gpio"; + drive-strength =3D <2>; + output-high; /* Unconditionally enable */ + bias-pull-down; + }; + + iovdd_reg_en: iovdd-reg-en-state { + pins =3D "gpio161"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-up; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins =3D "gpio55"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + vsp_reg_en: vsp-reg-en-state { + pins =3D "gpio72"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-pull-up; + }; + + vsn_reg_en: vsn-reg-en-state { + pins =3D "gpio73"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-pull-up; + }; +}; + +&uart14 { + status =3D "okay"; + + /* WCN7861-BT */ +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l1j_0p91>; + vdda-pll-supply =3D <&vreg_l3g_1p2>; + + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 215 GPIO_ACTIVE_LOW>; + + vcc-supply =3D <&vreg_l17b_2p5>; + vcc-max-microamp =3D <1300000>; + vccq-supply =3D <&vreg_l1d_1p2>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&usb { + dr_mode =3D "otg"; + maximum-speed =3D "super-speed-plus-gen2x1"; + + status =3D "okay"; + + ports { + /* + * USB2.0 is shared for two ports, set pinctrl eusb_mux_default + * to select the repeter. Plugging out one of them will reset + * the DWC3, which causes both of them to be disconnected. + */ + port@0 { + reg =3D <0>; + + usb_dwc3_hs: endpoint { + remote-endpoint =3D <&pmic_glink_hs_in>; + }; + }; + + port@2 { + reg =3D <2>; + + usb_dwc3_hs2: endpoint { + remote-endpoint =3D <&pmic_glink_hs_c2_in>; + }; + }; + }; +}; + +&usb_dp_qmpphy { + vdda-phy-supply =3D <&vreg_l3g_1p2>; + vdda-pll-supply =3D <&vreg_l2d_0p88>; + + mode-switch; + orientation-switch; + + status =3D "okay"; +}; + +&usb_dp_qmpphy_dp_in { + remote-endpoint =3D <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss_in>; +}; + +&usb_hsphy { + vdd-supply =3D <&vreg_l2d_0p88>; + vdda12-supply =3D <&vreg_l3g_1p2>; + + phys =3D <&eusb_repeater>; + + status =3D "okay"; +}; --=20 2.54.0