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[77.7.18.194]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49549c96f19sm193053245e9.9.2026.07.18.23.36.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 18 Jul 2026 23:36:30 -0700 (PDT) From: Karl Mehltretter To: Russell King , Greg Kroah-Hartman , Jiri Slaby Cc: linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , linux-rt-devel@lists.linux.dev, Toshiyuki Sato , Petr Mladek , John Ogness , Karl Mehltretter Subject: [PATCH 1/2] serial: amba-pl011: unprepare console clock on unregister Date: Sun, 19 Jul 2026 08:35:01 +0200 Message-Id: <20260719063502.18852-2-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20260719063502.18852-1-kmehltretter@gmail.com> References: <20260719063502.18852-1-kmehltretter@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pl011_console_setup() calls clk_prepare() on the UART clock, but the console provides no matching teardown, so the clock is never unprepared when the console is unregistered -- via the sysfs "console" attribute or a driver unbind. Each re-registration prepares the clock again, leaking one prepare reference per cycle. Even where preparing the clock has no hardware effect, the stale reference leaves the clock framework's prepare count unbalanced. On providers whose prepare operation enables hardware, the leaked reference may also keep the UART clock running after unregister. Add a console .exit() callback that clk_unprepare()s the clock, balancing the clk_prepare() in pl011_console_setup(). Fixes: 4b4851c65d92 ("clk: amba-pl011: convert to clk_prepare()/clk_unprepa= re()") Assisted-by: Claude:claude-fable-5 Signed-off-by: Karl Mehltretter --- The i.MX console had the same missing teardown, fixed in 9768a37cec37 ("serial: imx: disable console clocks on unregister"). Measured on QEMU raspi (bcm2835), whose UART clock is a real gateable CPRMAN clock: recycling the console via /sys/class/tty/ttyAMA0/console, the uart clock's prepare_count (/sys/kernel/debug/clk/uart/ clk_prepare_count) climbs by one per cycle -- 2 -> 8 over six cycles -- without this patch, and stays at 2 with it. drivers/tty/serial/amba-pl011.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl01= 1.c index 8ed91e1da22b..1aa43994a3cd 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -2552,6 +2552,15 @@ static int pl011_console_setup(struct console *co, c= har *options) return uart_set_options(&uap->port, co, baud, parity, bits, flow); } =20 +static int pl011_console_exit(struct console *co) +{ + struct uart_amba_port *uap =3D amba_ports[co->index]; + + clk_unprepare(uap->clk); + + return 0; +} + /** * pl011_console_match - non-standard console matching * @co: registering console @@ -2705,6 +2714,7 @@ static struct console amba_console =3D { .name =3D "ttyAMA", .device =3D uart_console_device, .setup =3D pl011_console_setup, + .exit =3D pl011_console_exit, .match =3D pl011_console_match, .write_atomic =3D pl011_console_write_atomic, .write_thread =3D pl011_console_write_thread, --=20 2.53.0 From nobody Sat Jul 25 03:46:50 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A83C377A81 for ; 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[77.7.18.194]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49549c96f19sm193053245e9.9.2026.07.18.23.36.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 18 Jul 2026 23:36:34 -0700 (PDT) From: Karl Mehltretter To: Russell King , Greg Kroah-Hartman , Jiri Slaby Cc: linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , linux-rt-devel@lists.linux.dev, Toshiyuki Sato , Petr Mladek , John Ogness , Karl Mehltretter Subject: [PATCH 2/2] serial: amba-pl011: keep console clock enabled for atomic writes Date: Sun, 19 Jul 2026 08:35:02 +0200 Message-Id: <20260719063502.18852-3-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20260719063502.18852-1-kmehltretter@gmail.com> References: <20260719063502.18852-1-kmehltretter@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" pl011_console_write_atomic() runs from nbcon atomic context, where sleeping is not allowed. It calls clk_enable(), which takes the common-clk enable_lock. Under PREEMPT_RT that is a sleeping lock: clk_enable_lock() first tries spin_trylock_irqsave(), but on contention falls back to spin_lock_irqsave(), so an atomic-context printk on an RT kernel with a clk-backed pl011 can trip: BUG: sleeping function called from invalid context at spinlock_rt.c:48 __might_resched from rt_spin_lock rt_spin_lock from clk_enable_lock clk_enable_lock from clk_enable clk_enable from pl011_console_write_atomic ... from vprintk_emit This was found and reproduced on 32-bit ARM with PREEMPT_RT. In addition, write_atomic() may be invoked from NMI context and is documented to avoid locking. Since clk_enable() acquires the common-clock enable_lock, removing it from the callback also avoids a potentially unsafe NMI lock acquisition. An nbcon atomic-capable console must be printable from any context, so the clock cannot be gated between writes. Enable the clock while the console is registered: use clk_prepare_enable() in pl011_console_setup(), release it via clk_disable_unprepare() in the console .exit() callback, and drop the per-write clk_enable()/clk_disable() pairs from write_atomic() and write_thread(). Keeping UARTCLK enabled may increase idle power on platforms where it would otherwise be gated between console writes. Fixes: 2eb2608618ce ("serial: amba-pl011: Implement nbcon console") Assisted-by: Claude:claude-fable-5 Signed-off-by: Karl Mehltretter --- The PREEMPT_RT splat above was reproduced on 32-bit ARM (versatilepb, ARM926EJ-S / ARMv5TE), Linux 7.2.0-rc3 based, CONFIG_PREEMPT_RT=3Dy CONFIG_HZ=3D1000, by driving an atomic-context printk; with this patch the clk_enable() -> rt_spin_lock() splat is gone. Tested on QEMU raspi (bcm2835, gateable CPRMAN UART clock) with the full series applied: recycling the console via /sys/class/tty/ttyAMA0/console keeps both prepare_count and enable_count balanced (2/2 across six cycles), and console output resumes after each re-registration. Suspend/resume was not exercised (no platform suspend under the QEMU model). drivers/tty/serial/amba-pl011.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl01= 1.c index 1aa43994a3cd..4facd1b350d5 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -2523,7 +2523,11 @@ static int pl011_console_setup(struct console *co, c= har *options) /* Allow pins to be muxed in and configured */ pinctrl_pm_select_default_state(uap->port.dev); =20 - ret =3D clk_prepare(uap->clk); + /* + * Keep the clock enabled while registered because write_atomic() may + * run in NMI context and must not acquire the clock framework lock. + */ + ret =3D clk_prepare_enable(uap->clk); if (ret) return ret; =20 @@ -2556,7 +2560,7 @@ static int pl011_console_exit(struct console *co) { struct uart_amba_port *uap =3D amba_ports[co->index]; =20 - clk_unprepare(uap->clk); + clk_disable_unprepare(uap->clk); =20 return 0; } @@ -2630,8 +2634,6 @@ pl011_console_write_atomic(struct console *co, struct= nbcon_write_context *wctxt if (!nbcon_enter_unsafe(wctxt)) return; =20 - clk_enable(uap->clk); - if (!uap->vendor->always_enabled) { old_cr =3D pl011_read(uap, REG_CR); pl011_write((old_cr & ~UART011_CR_CTSEN) | (UART01x_CR_UARTEN | UART011_= CR_TXE), @@ -2648,8 +2650,6 @@ pl011_console_write_atomic(struct console *co, struct= nbcon_write_context *wctxt if (!uap->vendor->always_enabled) pl011_write(old_cr, uap, REG_CR); =20 - clk_disable(uap->clk); - nbcon_exit_unsafe(wctxt); } =20 @@ -2662,8 +2662,6 @@ pl011_console_write_thread(struct console *co, struct= nbcon_write_context *wctxt if (!nbcon_enter_unsafe(wctxt)) return; =20 - clk_enable(uap->clk); - if (!uap->vendor->always_enabled) { old_cr =3D pl011_read(uap, REG_CR); pl011_write((old_cr & ~UART011_CR_CTSEN) | (UART01x_CR_UARTEN | UART011_= CR_TXE), @@ -2692,8 +2690,6 @@ pl011_console_write_thread(struct console *co, struct= nbcon_write_context *wctxt if (!uap->vendor->always_enabled) pl011_write(old_cr, uap, REG_CR); =20 - clk_disable(uap->clk); - nbcon_exit_unsafe(wctxt); } =20 --=20 2.53.0